CN110943605A - Control method and device of totem-pole power factor correction circuit - Google Patents
Control method and device of totem-pole power factor correction circuit Download PDFInfo
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Abstract
The embodiment of the invention provides a control method and a device of a totem-pole power factor correction circuit, wherein the method comprises the following steps: in a power frequency period, acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of an inductor in a totem-pole power factor correction circuit at each moment, wherein a connecting line of the upper peak value reference voltage values forms an upper envelope line, and a connecting line of the lower peak value reference voltage values forms a lower envelope line; obtaining the current of the inductor, and converting the current into voltage; comparing the voltage with the upper peak reference voltage value and the lower peak reference voltage value respectively; and controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
Description
Technical Field
The invention relates to the technical field of power electronic control, in particular to a control method and a control device of a totem-pole power factor correction circuit.
Background
Totem-pole power factor correction circuits are typically controlled using either Continuous Current Mode (CCM) or critical discontinuous Mode (CRM). Under the control of a continuous current mode, a switching device works in a hard switching state, the switching loss is large, the switching device is not suitable for high-frequency switching, and the inductor of a PFC (power factor correction) circuit is large in size. In order to reduce the inductance of the PFC, increase the switching frequency, and realize soft switching of the switching device, a critical discontinuous mode needs to be adopted. The critical discontinuous mode generally adopts a conduction time (Ton) control method, that is, the conduction time (Ton) of the main switching device is controlled to control the peak value of the inductive triangular wave current.
The principle of the conduction time control method of the totem-pole PFC critical discontinuous mode is as follows: the on-time (Ton) of the main switching device is adjusted and calculated according to the input alternating voltage, the output actual direct voltage and the output target current voltage. When the inductor triangle wave current drops to zero (or some negative current), the main switching device starts to conduct, the inductor current rises and lasts for Ton time, then the main switching device is closed, the current starts to drop until the inductor triangle wave current drops to zero (or some negative current) again, and the main switching device conducts again. The control is carried out in a cyclic mode in such a period.
Specifically, fig. 1 shows a schematic diagram of the method for controlling the on-time of the totem-pole PFC critical interruption mode under the waveform with positive half-cycle input ac voltage, wherein ILVGS _ main is a gate PWM signal of the main switching device, which is a triangular wave current of the PFC inductor. I isZCDThe zero-crossing comparison line of the inductive current (a certain negative current is adopted in the practical application of the soft switch). When the main switching device is turned off, the current drops, when the current drops to IZCD, the PWM signal of the main switching device is triggered to be turned on through the comparison circuit, then the inductive current starts to rise, the main switching device is continuously turned on for Ton, then the main switching device is turned off, and then the inductive current starts to dropAnd entering the next period. The control method mainly controls the peak value of the inductor current by controlling the continuous on-time (Ton) of the main switching device, thereby controlling the average current of the inductor. The on-time (Ton) can be adjusted by the voltage loop, and the variation trend of the Ton in the positive half cycle of the power frequency is shown in the upper right small graph of fig. 1.
However, in the above-described method for controlling the on-time in the totem-pole PFC critical discontinuous mode, the on-time of the main switching device is the subject of control, and therefore the peak value of the inductor current depends on the instantaneous ac voltage input at that time. If the input instantaneous ac voltage contains harmonics, distortion or even kicks, the peak value of the inductor current will deviate from the control target value. Under extremely severe working conditions, even current runaway may occur. The control effect of the control method is closely related to the waveform of the input alternating voltage. In practical application, the voltage waveform of the power grid may contain harmonic waves, distortion, sudden jump and the like, so that the control method has poor control robustness and weak anti-interference capability in practical application.
Disclosure of Invention
The embodiment of the invention provides a control method of a totem-pole power factor correction circuit, which aims to solve the technical problems of poor control robustness and weak anti-interference capability in a totem-pole PFC critical discontinuous mode in the prior art. The method comprises the following steps:
in a power frequency period, acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of an inductor in a totem-pole power factor correction circuit at each moment, wherein a connecting line of the upper peak value reference voltage value forms an upper envelope curve, a connecting line of the lower peak value reference voltage value forms a lower envelope curve, the upper peak value reference voltage value is obtained by converting an upper current peak value allowed by the inductor into voltage, and the lower peak value reference voltage value is obtained by converting a lower current peak value allowed by the inductor into voltage;
obtaining the current of the inductor, and converting the current into voltage;
comparing the voltage with the upper peak reference voltage value and the lower peak reference voltage value respectively;
and controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
The embodiment of the invention also provides a control device of the totem-pole power factor correction circuit, which is used for solving the technical problems of poor control robustness and weak anti-interference capability in the totem-pole PFC critical discontinuous mode in the prior art. The device includes:
a reference voltage obtaining module, configured to obtain, in a power frequency cycle, an upper peak reference voltage value and a lower peak reference voltage value of an inductor in a totem-pole power factor correction circuit at each time, where a connection line of the upper peak reference voltage values forms an upper envelope, a connection line of the lower peak reference voltage values forms a lower envelope, the upper peak reference voltage value is obtained by converting an upper current peak allowed by the inductor into a voltage, and the lower peak reference voltage value is obtained by converting a lower current peak allowed by the inductor into a voltage;
the voltage acquisition module is used for acquiring the current of the inductor and converting the current into voltage;
the comparison module is used for respectively comparing the voltage with the upper peak value reference voltage value and the lower peak value reference voltage value in magnitude;
and the control module is used for controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
The embodiment of the present invention further provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements any of the above methods for controlling the totem-pole power factor correction circuit. The method solves the technical problems of poor control robustness and weak anti-interference capability of a totem-pole PFC critical discontinuous mode in the prior art.
An embodiment of the present invention further provides a computer-readable storage medium storing a computer program for executing the control method of any totem-pole power factor correction circuit described above. The method solves the technical problems of poor control robustness and weak anti-interference capability of a totem-pole PFC critical discontinuous mode in the prior art.
In the embodiment of the invention, the upper peak value reference voltage value and the lower peak value reference voltage value of the inductor at each moment in the power frequency period are obtained, the voltage obtained by converting the current of the inductor is compared with the upper peak value reference voltage value and the lower peak value reference voltage value in size, and finally, the on-off of a main switching element in the totem-pole power factor correction circuit is controlled according to the comparison result, so that the voltage obtained by converting the current of the inductor is controlled in the range formed by the upper envelope line and the lower envelope line, the current of the inductor is controlled in the range formed by the current corresponding to the upper envelope line and the current corresponding to the lower envelope line, the current of the inductor is not influenced by the phenomena of ripples, spikes, waveform distortion and the like in the input alternating current voltage and the output direct current voltage, the control robustness is greatly enhanced, and the anti-interference capability is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating a method for controlling the turn-on time of a totem-pole PFC critical break mode in the prior art;
fig. 2 is a flowchart of a control method of a totem-pole power factor correction circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a reference voltage value generation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an upper envelope and a lower envelope provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of a principle of controlling the on and off of a main switching device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of controlling inductor current according to an embodiment of the present invention;
fig. 7 is a basic circuit diagram of a totem-pole power factor correction circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an interleaved parallel circuit of a totem-pole power factor correction circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a control interleaving parallel circuit according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a delay compensated envelope provided by an embodiment of the present invention;
fig. 11 is a block diagram of a control device of a totem-pole power factor correction circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
In an embodiment of the present invention, a method for controlling a totem-pole power factor correction circuit is provided, as shown in fig. 2, the method includes:
step 201: in a power frequency period, acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of an inductor in a totem-pole power factor correction circuit at each moment, wherein a connecting line of the upper peak value reference voltage value forms an upper envelope curve, a connecting line of the lower peak value reference voltage value forms a lower envelope curve, the upper peak value reference voltage value is obtained by converting an upper current peak value allowed by the inductor into voltage, and the lower peak value reference voltage value is obtained by converting a lower current peak value allowed by the inductor into voltage;
step 202: obtaining the current of the inductor, and converting the current into voltage;
step 203: comparing the voltage with the upper peak reference voltage value and the lower peak reference voltage value respectively;
step 204: and controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
As can be seen from the process shown in fig. 2, in the embodiment of the present invention, by obtaining the upper peak reference voltage value and the lower peak reference voltage value at each time of the inductance in the power frequency cycle, further comparing the voltage obtained by converting the current of the inductor with the upper peak reference voltage value and the lower peak reference voltage value, and finally, controlling the on-off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, the voltage obtained by converting the current of the inductor is controlled in the range formed by the upper envelope line and the lower envelope line, thereby realizing that the current of the inductor is controlled in the range of the current corresponding to the upper envelope line and the current corresponding to the lower envelope line, the current of the inductor is not influenced by the phenomena of ripples, spikes, waveform distortion and the like in the input alternating current voltage and the output direct current voltage, the control robustness is greatly enhanced, and the anti-interference capability is improved.
In specific implementation, the upper peak reference voltage value is obtained by converting the current upper peak value allowed by the inductor into voltage, and the lower peak reference voltage value is obtained by converting the current lower peak value allowed by the inductor into voltage.
Specifically, the principle of obtaining the upper peak reference voltage value and the lower peak reference voltage value is described with reference to fig. 3, and the adjustment is performed according to the error between the target value of the output dc voltage and the actually fed back output dc voltage, and the output of the regulator (e.g., PI) is the target inductor average current effective value. Detecting the phase angle of the input AC voltage, averaging based on the phase angle of the input AC voltage and the target inductanceAnd the current effective value is calculated by a multiplier to obtain the instantaneous value of the target inductor average current. Then, the instantaneous value of the target inductor average current is added to the absolute value I of the minimum negative current value required for realizing soft switching through an addernegObtaining the current upper peak value allowed by the inductor, and converting the current upper peak value allowed by the inductor into voltage to obtain an upper peak value reference voltage value; and adding the minimum negative current value required by realizing soft switching to the lower peak value of the current allowed by the inductor to obtain the lower peak value of the current allowed by the inductor, and converting the lower peak value of the current allowed by the inductor into voltage to obtain a lower peak value reference voltage value.
In specific implementation, after an upper peak reference voltage value and a lower peak reference voltage value are obtained, as shown in fig. 4, the upper peak reference voltage value is greater than the lower peak reference voltage value, a connection line of the upper peak reference voltage value in a power frequency cycle forms an upper envelope line a, a connection line of the lower peak reference voltage value in the power frequency cycle forms a lower envelope line B, a part of the upper envelope line a in a positive half cycle of the power frequency cycle is a sine curve of a positive half shaft, and a part of the lower envelope line B in the positive half cycle of the power frequency cycle is a straight line with a negative value; the part of the lower envelope line B in the negative half cycle of the power frequency cycle is a sine curve with a negative half shaft, and the part of the upper envelope line A in the negative half cycle of the power frequency cycle is a straight line with a positive value.
In specific implementation, in this embodiment, the upper peak reference voltage value is calculated by the following formula (1):
calculating the lower peak reference voltage value by the following formula (2):
wherein, VCmp1Is the upper peak reference voltage value; vCmp2Is the lower peak reference voltage value; i isrefIs the target average inductive current effective value; i isnegTo achieve soft switchingTurning off the absolute value of the required minimum negative current; k is the corresponding proportionality coefficient between the current and the voltage of the inductor; ω is the angular frequency of the voltage; t is time.
In specific implementation, the current of the inductor can be detected through the sampling resistor, and then the current is converted into voltage. Specifically, the collected current may be amplified by an operational amplifier circuit, and then the amplified current may be converted into a voltage.
In specific implementation, after obtaining the upper peak reference voltage value and the lower peak reference voltage value, in order to implement controlling on and off of the main switching device in the totem-pole power factor correction circuit according to the comparison result, in this embodiment, the method includes:
in the positive half cycle of a power frequency cycle, when the voltage is greater than the upper peak value reference voltage value, controlling a main switching device of the positive half cycle in the totem-pole power factor correction circuit to be switched off, and when the voltage is less than the lower peak value reference voltage value, controlling a main switching device of the positive half cycle in the totem-pole power factor correction circuit to be switched on;
and in the negative half cycle of the power frequency cycle, when the inversion voltage of the voltage is greater than the inversion voltage of the lower peak value reference voltage value, controlling the main switching element in the negative half cycle of the totem-pole power factor correction circuit to be switched off, and when the inversion voltage of the voltage is less than the inversion voltage of the upper peak value reference voltage value, controlling the main switching element in the negative half cycle of the totem-pole power factor correction circuit to be switched on.
In specific implementation, as shown in fig. 5 (taking a positive half cycle as an example), the comparison between the voltage and the upper peak reference voltage value and the lower peak reference voltage value can be implemented through the following circuit structures, and then the on and off of the main switching device in the totem-pole power factor correction circuit is controlled according to the comparison result:
the first comparator is used for comparing the voltage with the upper peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputting a first rising edge signal when the voltage is greater than the upper peak value reference voltage value;
the input end of the pulse signal generator (for example, a PWM generator) is connected to the output end of the first comparator, and the pulse signal generator is configured to output a first turn-off signal according to the first rising edge signal to control the main switching device of the positive half cycle in the totem-pole power factor correction circuit to turn off, and control the complementary switching device to turn on;
the second comparator compares the voltage with the lower peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputs a first falling edge signal when the voltage is smaller than the lower peak value reference voltage value;
the input end of the pulse signal generator is also connected with the output end of the second comparator, and the pulse signal generator is also used for outputting a first turn-on signal according to the first falling edge signal to control the main switching element of the positive half cycle in the totem-pole power factor correction circuit to be turned on and control the complementary switching element to be turned off;
the first comparator is further configured to compare the inverted voltage of the voltage with the inverted voltage of the lower peak reference voltage value in a negative half cycle of a power frequency cycle, and output a second rising edge signal when the inverted voltage of the voltage is greater than the inverted voltage of the lower peak reference voltage value;
the pulse signal generator is also used for generating a second turn-off signal according to the second rising edge signal to control the turn-off of a main switching device of a negative half cycle in the totem-pole power factor correction circuit and control the turn-on of a complementary switching device at the same time;
the second comparator is further configured to compare an inverted voltage of the voltage with an inverted voltage of the upper peak reference voltage value, and output a second falling edge signal when the inverted voltage of the voltage is smaller than the inverted voltage of the upper peak reference voltage value;
the pulse signal generator is further configured to output a second turn-on signal according to the second falling edge signal to control the main switching device of the negative half cycle in the totem-pole power factor correction circuit to be turned on, and control the complementary switching device to be turned off.
In specific implementation, the on and off of the main switching device in the totem-pole power factor correction circuit are controlled through the comparison result, so that the current of the inductor is controlled, for example, the change of the current of the inductor is described by taking the positive half cycle of a power frequency cycle as an example, as shown in fig. 6, ILThe gate PWM signal triggers the main switch device to turn off when the first comparator outputs a rising edge signal, and triggers the complementary switch device to turn on when the second comparator outputs a falling edge signal. I isZCDThe zero-crossing comparison line of the inductive current (a certain negative current is adopted in the practical application of the soft switch). I isSinThe peak value of the inductive current is compared with the line. When the main switching device is turned off, the current decreases, and when the current decreases to IZCDWhen the main switch device is triggered to turn on, the inductor current starts to rise. When the current rises to ISinWhen the current reaches the preset value, the main switching device is triggered to be turned off, and then the inductive current begins to fall to enter the next period. The control method mainly comprises the following steps of controlling IZCDAnd ISinThe lines are compared to control the envelope of the inductor current and thus the average inductor current. I isSinAnd IZCDThe two comparison lines constitute the upper and lower envelope lines of the present invention. I isZCDNormally controlled to be dc to achieve soft switching of the main switching device, ISinDerived from voltage loop regulation, ISinAnd IZCDThe trend of the change in the positive half cycle of the power frequency is shown in the upper right small graph in fig. 6.
In one embodiment, the main switching device in the totem-pole power factor correction circuit has two configurations, for example, as shown in fig. 7, the main switching device is composed of a set of half-bridge configurations (S)1And S2) Composed of multiple circuits connected in parallel, each circuit being composed of a set of half-bridge structures (S), as shown in FIG. 81-xAnd S2-x(x ═ 1.. n)) and an inductor is connected to the midpoint of each half-bridge structure(e.g., L)1、L2……Ln) Separate independent control of the switching on and off of the main switching devices in each set of half-bridge configurations may be achieved, for example,
respectively acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of the inductor in each circuit at each moment;
obtaining the current of an inductor in each circuit, and converting the current into voltage;
comparing the voltage corresponding to the inductor in each circuit with the upper peak value reference voltage value and the lower peak value reference voltage value corresponding to the inductor in the circuit respectively;
and controlling the on and off of the main switching devices in the half-bridge structures of the circuit according to the comparison result of each circuit, wherein the on of the main switching devices in the two adjacent half-bridge structures has a phase difference of 360/n, wherein n is the total number of parallel circuits in the main switching devices, and the voltage corresponding to the inductance of the circuit is controlled within the range formed by the upper envelope line and the lower envelope line of the circuit.
Specifically, as shown in fig. 9, the turn-on phase difference of the main switching device in the kth path with respect to the main switching device in the 1 st path can be calculated by detecting the delay of the rising edge signal of the main switching device in the kth path with respect to the rising edge signal of the main switching device in the 1 st path. And (3) calculating an error value by taking the difference between the phase difference and a target phase difference (360/n x k), calculating to obtain an adjustment voltage of the envelope reference voltage through a proportional regulator, and superposing the adjustment voltage on the envelope reference voltage to obtain a final envelope reference voltage value of the kth path.
In particular, in order to reduce the effect of delay and improve the accuracy of control, in this embodiment, the upper peak reference voltage value and the lower peak reference voltage value are compensated for delay, for example,
calculating a total delay value generated in a process from current collection of the inductor to control on and off of the main switching device (for example, including delay generated in the process due to links such as sampling, conditioning, voltage comparison, generation of a trigger pulse signal and the like of the inductor current);
calculating a current change value of the current of the inductor caused by the total delay value according to an input alternating current voltage instantaneous value of the totem-pole power factor correction circuit, an output direct current voltage instantaneous value of the totem-pole power factor correction circuit, the inductance value of the inductor and the total delay value;
converting the current change value into a voltage change of an upper peak reference voltage value and a voltage change of a lower peak reference voltage value;
superposing the voltage variation of the upper peak value reference voltage value on the upper peak value reference voltage value to obtain the upper peak value reference voltage value after delay compensation; and superposing the voltage variation of the lower peak value reference voltage value on the lower peak value reference voltage value to obtain the lower peak value reference voltage value after delay compensation.
In concrete implementation, in the present embodiment, the voltage variation of the peak reference voltage value is calculated by the following equation (3):
the voltage variation amount of the lower peak reference voltage value is calculated by the following formula (4):
wherein, is Δ VCmp1A voltage variation amount that is an upper peak reference voltage value; Δ VCmp2A voltage variation amount that is a lower peak reference voltage value; vinThe instantaneous value of the input alternating voltage of the totem-pole power factor correction circuit is obtained; voutThe instantaneous value of the output direct current voltage of the totem-pole power factor correction circuit is obtained; l isPFCAn inductance value of the inductor; t isdFor controlling the switching-on of the main switching device from the current collection of the inductorAnd a total delay value resulting from the process of shutting down; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
Specifically, the upper peak reference voltage value after the delay compensation is obtained by the following formula (5):
V’Cmp1＝VCmp1+ΔVCmp1(5)
obtaining the time-delay compensated lower peak reference voltage value by the following formula (6):
V’Cmp2＝VCmp2+ΔVCmp2(6)
in specific implementation, taking the power frequency positive half cycle as an example, as shown in fig. 10, a compensated upper envelope a '(shown by a solid line in fig. 10) is formed by connecting time-delay compensated upper peak reference voltage values, a compensated lower envelope B' (shown by a solid line in fig. 10) is formed by connecting time-delay compensated lower peak reference voltage values, a dotted line a in fig. 10 is the upper envelope before compensation, and a dotted line B in fig. 10 is the lower envelope before compensation.
However, it is to be noted that, as shown in fig. 10, after the delay compensation, in a region where the input ac voltage is small, the lower peak reference voltage value in the lower envelope may be larger than the upper peak reference voltage value in the upper envelope. This case is not compatible with the control logic of the dual envelope control, so the present application introduces a minimum width between the upper and lower envelopes, adjusts the delay compensated upper peak reference voltage value and the delay compensated lower peak reference voltage value according to the minimum width, for example,
obtaining an allowable minimum difference value between an upper peak value reference voltage value after delay compensation and a lower peak value reference voltage value after delay compensation, wherein the minimum difference value represents the minimum width between an upper envelope line and a lower envelope line;
adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency period according to the minimum difference value to obtain an adjusted lower peak value reference voltage value; and adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency period according to the minimum difference value to obtain the adjusted upper peak value reference voltage value, wherein the minimum width between the adjusted lower envelope line and the adjusted upper envelope line in the power frequency period is greater than or equal to the minimum difference value.
Adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency cycle by the following formula:
adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle by the following formula:
wherein, V "Cmp1The adjusted upper peak value reference voltage value; v'Cmp2The adjusted lower peak value reference voltage value; v'Cmp1The reference voltage value of the upper peak value after the time delay compensation of the negative half cycle in the power frequency cycle; v'Cmp2The lower peak value reference voltage value is the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle; vGapMinIs the minimum difference; ω is the angular frequency of the voltage; t is time.
In this embodiment, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements the control method of the totem-pole power factor correction circuit as described in any of the above.
In the present embodiment, there is provided a computer-readable storage medium storing a computer program for executing the control method of the totem-pole power factor correction circuit as described above.
Based on the same inventive concept, the embodiment of the present invention further provides a control device of a totem-pole power factor correction circuit, as described in the following embodiments. Because the principle of the totem-pole power factor correction circuit for solving the problems is similar to the control method of the totem-pole power factor correction circuit, the implementation of the control device of the totem-pole power factor correction circuit can refer to the implementation of the control method of the totem-pole power factor correction circuit, and repeated parts are not repeated. As used hereinafter, the term "unit" or "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 11 is a block diagram of a structure of a control device of a totem-pole power factor correction circuit according to an embodiment of the present invention, and as shown in fig. 11, the control device includes:
a reference voltage obtaining module 1101, configured to obtain, in a power frequency cycle, an upper peak reference voltage value and a lower peak reference voltage value of an inductor in a totem-pole power factor correction circuit at each time, where a connection line of the upper peak reference voltage values forms an upper envelope, a connection line of the lower peak reference voltage values forms a lower envelope, the upper peak reference voltage value is obtained by converting an upper current peak allowed by the inductor into a voltage, and the lower peak reference voltage value is obtained by converting a lower current peak allowed by the inductor into a voltage;
a voltage obtaining module 1102, configured to obtain a current of the inductor, and convert the current into a voltage;
a comparing module 1103, configured to compare the voltage with the upper peak reference voltage value and the lower peak reference voltage value respectively;
and the control module 1104 is configured to control on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, and control the voltage within a range formed by the upper envelope line and the lower envelope line.
In one embodiment, the upper peak reference voltage value is greater than the lower peak reference voltage value, and within a positive half cycle of a power frequency cycle, the upper envelope curve is a sine curve of a positive half shaft, and the lower envelope curve is a straight line; in the negative half cycle of the power frequency cycle, the lower envelope curve is a sine curve of a negative half shaft, and the upper envelope curve is a straight line.
In one embodiment, the reference voltage acquisition module calculates the upper peak reference voltage value by the following equation:
the reference voltage acquisition module calculates the lower peak reference voltage value by the following formula:
wherein, VCmp1Is the upper peak reference voltage value; vCmp2Is the lower peak reference voltage value; i isrefIs the target average inductive current effective value; i isnegThe absolute value of the minimum negative current required to achieve soft switching; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
In one embodiment, the comparison module comprises a first comparator and a second comparator, and the control module comprises a pulse signal generator, wherein,
the first comparator is used for comparing the voltage with the upper peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputting a first rising edge signal when the voltage is greater than the upper peak value reference voltage value;
the input end of the pulse signal generator is connected with the output end of the first comparator, and the pulse signal generator is used for outputting a first turn-off signal according to the first rising edge signal to control the turn-off of a main switching device in a positive half cycle in the totem-pole power factor correction circuit;
the second comparator compares the voltage with the lower peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputs a first falling edge signal when the voltage is smaller than the lower peak value reference voltage value;
the input end of the pulse signal generator is also connected with the output end of the second comparator, and the pulse signal generator is also used for outputting a first turn-on signal according to the first falling edge signal to control the turn-on of a main switching device in the positive half cycle of the totem-pole power factor correction circuit;
the first comparator is further configured to compare the inverted voltage of the voltage with the inverted voltage of the lower peak reference voltage value in a negative half cycle of a power frequency cycle, and output a second rising edge signal when the inverted voltage of the voltage is greater than the inverted voltage of the lower peak reference voltage value;
the pulse signal generator is further used for generating a second turn-off signal according to the second rising edge signal to control the turn-off of a main switching device of a negative half cycle in the totem-pole power factor correction circuit;
the second comparator is further configured to compare an inverted voltage of the voltage with an inverted voltage of the upper peak reference voltage value, and output a second falling edge signal when the inverted voltage of the voltage is smaller than the inverted voltage of the upper peak reference voltage value;
the pulse signal generator is further configured to output a second turn-on signal according to the second falling edge signal to control the turn-on of the negative half-cycle main switching device in the totem-pole power factor correction circuit.
In one embodiment, when the main switching device in the totem-pole power factor correction circuit is formed by connecting multiple circuits in parallel, each circuit is formed by a group of half-bridge structures, and an inductor is connected to the midpoint of each group of half-bridge structures, wherein,
the reference voltage acquisition module is further used for respectively acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of the inductor in each circuit at each moment;
the voltage acquisition module is also used for acquiring the current of the inductor in each circuit and converting the current into voltage;
the comparison module is also used for respectively comparing the voltage corresponding to the inductor in each circuit with the upper peak value reference voltage value and the lower peak value reference voltage value corresponding to the inductor in the circuit;
the control module is further configured to control turning on and off of the main switching device in the half-bridge structure of each circuit according to the comparison result of each circuit, and a phase difference exists between turning on of the main switching devices in the two adjacent half-bridge structures, where the phase difference is 360/n, where n is the total number of parallel circuits in the main switching devices, and the voltage corresponding to the inductance of the circuit is controlled within a range formed by an upper envelope line and a lower envelope line of the circuit.
In one embodiment, further comprising:
the time delay calculation module is used for calculating a total time delay value generated from the current collection of the inductor to the process of controlling the on and off of the main switching device;
a current change value calculation module, configured to calculate a current change value of the current of the inductor caused by the total delay value according to an input ac voltage instantaneous value of the totem-pole power factor correction circuit, an output dc voltage instantaneous value of the totem-pole power factor correction circuit, an inductance value of the inductor, and the total delay value;
the voltage variation calculation module is used for converting the current variation into a voltage variation of an upper peak reference voltage value and a voltage variation of a lower peak reference voltage value;
the delay compensation module is used for superposing the voltage variation of the upper peak value reference voltage value on the upper peak value reference voltage value to obtain the upper peak value reference voltage value after delay compensation; and superposing the voltage variation of the lower peak value reference voltage value on the lower peak value reference voltage value to obtain the lower peak value reference voltage value after delay compensation.
In one embodiment, the voltage variation calculation module calculates the voltage variation of the peak reference voltage value by the following equation:
the voltage variation calculating module calculates a voltage variation of the lower peak reference voltage value by the following formula:
wherein, is Δ VCmp1A voltage variation amount that is an upper peak reference voltage value; Δ VCmp2A voltage variation amount that is a lower peak reference voltage value; vinThe instantaneous value of the input alternating voltage of the totem-pole power factor correction circuit is obtained; voutThe instantaneous value of the output direct current voltage of the totem-pole power factor correction circuit is obtained; l isPFCAn inductance value of the inductor; t isdA total delay value generated from the current collection of the inductor to the process of controlling the on and off of the main switching device; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
In one embodiment, further comprising:
a minimum difference value obtaining module, configured to obtain a minimum difference value allowed between the delay-compensated upper peak reference voltage value and the delay-compensated lower peak reference voltage value, where the minimum difference value represents a minimum width between the upper envelope line and the lower envelope line;
the reference voltage adjusting module is used for adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle according to the minimum difference value to obtain an adjusted lower peak value reference voltage value; and adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency period according to the minimum difference value to obtain the adjusted upper peak value reference voltage value, wherein the minimum width between the adjusted lower envelope line and the adjusted upper envelope line in the power frequency period is greater than or equal to the minimum difference value.
In one embodiment, the reference voltage adjusting module adjusts the delayed compensated upper peak reference voltage value of the negative half cycle in the power frequency cycle by the following formula:
the reference voltage adjusting module adjusts the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle through the following formula:
wherein, V "Cmp1The adjusted upper peak value reference voltage value; v'Cmp2The adjusted lower peak value reference voltage value; v'Cmp1The reference voltage value of the upper peak value after the time delay compensation of the negative half cycle in the power frequency cycle; v'Cmp2The lower peak value reference voltage value is the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle; vGapMinIs the minimum difference; ω is the angular frequency of the voltage; t is time.
In another embodiment, a software is provided, which is used to execute the technical solutions described in the above embodiments and preferred embodiments.
In another embodiment, a storage medium is provided, in which the software is stored, and the storage medium includes but is not limited to: optical disks, floppy disks, hard disks, erasable memory, etc.
The embodiment of the invention realizes the following technical effects: the voltage obtained by converting the current of the inductor is controlled in the range formed by an upper envelope line and a lower envelope line, so that the current of the inductor is controlled in the range formed by the current corresponding to the upper envelope line and the current corresponding to the lower envelope line, the current of the inductor is not influenced by the phenomena of ripples, spikes, waveform distortion and the like in input alternating current voltage and output direct current voltage, the control robustness is greatly enhanced, and the anti-interference capability is improved.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A control method of a totem-pole power factor correction circuit is characterized by comprising the following steps:
in a power frequency period, acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of an inductor in a totem-pole power factor correction circuit at each moment, wherein a connecting line of the upper peak value reference voltage value forms an upper envelope curve, a connecting line of the lower peak value reference voltage value forms a lower envelope curve, the upper peak value reference voltage value is obtained by converting an upper current peak value allowed by the inductor into voltage, and the lower peak value reference voltage value is obtained by converting a lower current peak value allowed by the inductor into voltage;
obtaining the current of the inductor, and converting the current into voltage;
comparing the voltage with the upper peak reference voltage value and the lower peak reference voltage value respectively;
and controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result, and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
2. The method of controlling a totem-pole power factor correction circuit of claim 1, wherein the upper peak reference voltage value is greater than the lower peak reference voltage value, the upper envelope curve being a sine curve of positive half-axes and the lower envelope curve being a straight line during the positive half-cycle of the power frequency cycle; in the negative half cycle of the power frequency cycle, the lower envelope curve is a sine curve of a negative half shaft, and the upper envelope curve is a straight line.
3. The method of controlling a totem-pole power factor correction circuit according to claim 1,
calculating the upper peak reference voltage value by the following formula:
calculating the lower peak reference voltage value by the following formula:
wherein, VCmp1Is the upper peak reference voltage value; vCmp2Is the lower peak reference voltage value; i isrefIs the target average inductive current effective value; i isnegThe absolute value of the minimum negative current required to achieve soft switching; k is the corresponding proportionality coefficient between the current and the voltage of the inductor; ω is the angular frequency of the voltage; t is time.
4. The method of controlling a totem-pole power factor correction circuit according to claim 1, wherein controlling on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result comprises:
in the positive half cycle of a power frequency cycle, when the voltage is greater than the upper peak value reference voltage value, controlling a main switching device of the positive half cycle in the totem-pole power factor correction circuit to be switched off, and when the voltage is less than the lower peak value reference voltage value, controlling a main switching device of the positive half cycle in the totem-pole power factor correction circuit to be switched on;
and in the negative half cycle of the power frequency cycle, when the inversion voltage of the voltage is greater than the inversion voltage of the lower peak value reference voltage value, controlling the main switching element in the negative half cycle of the totem-pole power factor correction circuit to be switched off, and when the inversion voltage of the voltage is less than the inversion voltage of the upper peak value reference voltage value, controlling the main switching element in the negative half cycle of the totem-pole power factor correction circuit to be switched on.
5. The method of controlling a totem-pole power factor correction circuit according to claim 1, wherein when the main switching devices of the totem-pole power factor correction circuit are formed by connecting a plurality of circuits in parallel, each circuit is formed by a set of half-bridge structures, and an inductor is connected to a midpoint of each set of half-bridge structures, wherein,
respectively acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of the inductor in each circuit at each moment;
obtaining the current of an inductor in each circuit, and converting the current into voltage;
comparing the voltage corresponding to the inductor in each circuit with the upper peak value reference voltage value and the lower peak value reference voltage value corresponding to the inductor in the circuit respectively;
and controlling the on and off of the main switching devices in the half-bridge structures of the circuit according to the comparison result of each circuit, wherein the on of the main switching devices in the two adjacent half-bridge structures has a phase difference of 360/n, wherein n is the total number of parallel circuits in the main switching devices, and the voltage corresponding to the inductance of the circuit is controlled within the range formed by the upper envelope line and the lower envelope line of the circuit.
6. The method for controlling a totem-pole power factor correction circuit according to any one of claims 1 to 5, further comprising:
calculating a total delay value generated from the current collection of the inductor to the process of controlling the on and off of the main switching device;
calculating a current change value of the current of the inductor caused by the total delay value according to an input alternating current voltage instantaneous value of the totem-pole power factor correction circuit, an output direct current voltage instantaneous value of the totem-pole power factor correction circuit, the inductance value of the inductor and the total delay value;
converting the current change value into a voltage change of an upper peak reference voltage value and a voltage change of a lower peak reference voltage value;
superposing the voltage variation of the upper peak value reference voltage value on the upper peak value reference voltage value to obtain the upper peak value reference voltage value after delay compensation; and superposing the voltage variation of the lower peak value reference voltage value on the lower peak value reference voltage value to obtain the lower peak value reference voltage value after delay compensation.
7. The method of controlling a totem-pole power factor correction circuit according to claim 6,
calculating a voltage variation amount of the peak reference voltage value by the following equation:
the voltage variation amount of the lower peak reference voltage value is calculated by the following formula:
wherein, is Δ VCmp1A voltage variation amount that is an upper peak reference voltage value; Δ VCmp2A voltage variation amount that is a lower peak reference voltage value; vinThe instantaneous value of the input alternating voltage of the totem-pole power factor correction circuit is obtained; voutThe instantaneous value of the output direct current voltage of the totem-pole power factor correction circuit is obtained; l isPFCAn inductance value of the inductor; t isdFor current collection from the inductor to control the mainA total delay value generated in the process of turning on and off the switching device; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
8. The method of controlling a totem-pole power factor correction circuit of claim 6, further comprising:
obtaining an allowable minimum difference value between an upper peak value reference voltage value after delay compensation and a lower peak value reference voltage value after delay compensation, wherein the minimum difference value represents the minimum width between an upper envelope line and a lower envelope line;
adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency period according to the minimum difference value to obtain an adjusted lower peak value reference voltage value; and adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency period according to the minimum difference value to obtain the adjusted upper peak value reference voltage value, wherein the minimum width between the adjusted lower envelope line and the adjusted upper envelope line in the power frequency period is greater than or equal to the minimum difference value.
9. The method of controlling a totem-pole power factor correction circuit of claim 8,
adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency cycle by the following formula:
adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle by the following formula:
wherein, V ″)Cmp1The adjusted upper peak value reference voltage value; v ″)Cmp2The adjusted lower peak value reference voltage value; v'Cmp1For a power frequency cycleThe upper peak value reference voltage value after the delay compensation of the negative half cycle in the period; v'Cmp2The lower peak value reference voltage value is the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle; vGapMinIs the minimum difference; ω is the angular frequency of the voltage; t is time.
10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of controlling the totem-pole power factor correction circuit of any one of claims 1 to 9 when executing the computer program.
11. A computer-readable storage medium storing a computer program for executing the method for controlling the totem-pole power factor correction circuit according to any one of claims 1 to 9.
12. A control device for a totem-pole power factor correction circuit, comprising:
a reference voltage obtaining module, configured to obtain, in a power frequency cycle, an upper peak reference voltage value and a lower peak reference voltage value of an inductor in a totem-pole power factor correction circuit at each time, where a connection line of the upper peak reference voltage values forms an upper envelope, a connection line of the lower peak reference voltage values forms a lower envelope, the upper peak reference voltage value is obtained by converting an upper current peak allowed by the inductor into a voltage, and the lower peak reference voltage value is obtained by converting a lower current peak allowed by the inductor into a voltage;
the voltage acquisition module is used for acquiring the current of the inductor and converting the current into voltage;
the comparison module is used for respectively comparing the voltage with the upper peak value reference voltage value and the lower peak value reference voltage value in magnitude;
and the control module is used for controlling the on and off of a main switching device in the totem-pole power factor correction circuit according to the comparison result and controlling the voltage in a range formed by the upper envelope line and the lower envelope line.
13. The control device of a totem-pole power factor correction circuit of claim 12, wherein the upper peak reference voltage value is greater than the lower peak reference voltage value, the upper envelope curve being a sine curve of positive half-axes and the lower envelope curve being a straight line in the positive half-cycle of the power frequency cycle; in the negative half cycle of the power frequency cycle, the lower envelope curve is a sine curve of a negative half shaft, and the upper envelope curve is a straight line.
14. The control device of a totem-pole power factor correction circuit of claim 12,
the reference voltage acquisition module calculates the upper peak reference voltage value by the following formula:
the reference voltage acquisition module calculates the lower peak reference voltage value by the following formula:
wherein, VCmp1Is the upper peak reference voltage value; vCmp2Is the lower peak reference voltage value; i isrefIs the target average inductive current effective value; i isnegThe absolute value of the minimum negative current required to achieve soft switching; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
15. The apparatus of claim 12, wherein the comparison module comprises a first comparator and a second comparator, and the control module comprises a pulse signal generator, wherein
The first comparator is used for comparing the voltage with the upper peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputting a first rising edge signal when the voltage is greater than the upper peak value reference voltage value;
the input end of the pulse signal generator is connected with the output end of the first comparator, and the pulse signal generator is used for outputting a first turn-off signal according to the first rising edge signal to control the turn-off of a main switching device in a positive half cycle in the totem-pole power factor correction circuit;
the second comparator compares the voltage with the lower peak value reference voltage value in the positive half cycle of the power frequency cycle, and outputs a first falling edge signal when the voltage is smaller than the lower peak value reference voltage value;
the input end of the pulse signal generator is also connected with the output end of the second comparator, and the pulse signal generator is also used for outputting a first turn-on signal according to the first falling edge signal to control the turn-on of a main switching device in the positive half cycle of the totem-pole power factor correction circuit;
the first comparator is further configured to compare the inverted voltage of the voltage with the inverted voltage of the lower peak reference voltage value in a negative half cycle of a power frequency cycle, and output a second rising edge signal when the inverted voltage of the voltage is greater than the inverted voltage of the lower peak reference voltage value;
the pulse signal generator is further used for generating a second turn-off signal according to the second rising edge signal to control the turn-off of a main switching device of a negative half cycle in the totem-pole power factor correction circuit;
the second comparator is further configured to compare an inverted voltage of the voltage with an inverted voltage of the upper peak reference voltage value, and output a second falling edge signal when the inverted voltage of the voltage is smaller than the inverted voltage of the upper peak reference voltage value;
the pulse signal generator is further configured to output a second turn-on signal according to the second falling edge signal to control the turn-on of the negative half-cycle main switching device in the totem-pole power factor correction circuit.
16. The apparatus for controlling a totem-pole power factor correction circuit according to claim 12, wherein when the main switching device of the totem-pole power factor correction circuit is formed by connecting a plurality of circuits in parallel, each circuit is formed by a set of half-bridge structures, and an inductor is connected to a midpoint of each set of half-bridge structures, wherein,
the reference voltage acquisition module is further used for respectively acquiring an upper peak value reference voltage value and a lower peak value reference voltage value of the inductor in each circuit at each moment;
the voltage acquisition module is also used for acquiring the current of the inductor in each circuit and converting the current into voltage;
the comparison module is also used for respectively comparing the voltage corresponding to the inductor in each circuit with the upper peak value reference voltage value and the lower peak value reference voltage value corresponding to the inductor in the circuit;
the control module is further configured to control turning on and off of the main switching device in the half-bridge structure of each circuit according to the comparison result of each circuit, and a phase difference exists between turning on of the main switching devices in the two adjacent half-bridge structures, where the phase difference is 360/n, where n is the total number of parallel circuits in the main switching devices, and the voltage corresponding to the inductance of the circuit is controlled within a range formed by an upper envelope line and a lower envelope line of the circuit.
17. The control device of the totem-pole power factor correction circuit according to any one of claims 12 to 16, further comprising:
the time delay calculation module is used for calculating a total time delay value generated from the current collection of the inductor to the process of controlling the on and off of the main switching device;
a current change value calculation module, configured to calculate a current change value of the current of the inductor caused by the total delay value according to an input ac voltage instantaneous value of the totem-pole power factor correction circuit, an output dc voltage instantaneous value of the totem-pole power factor correction circuit, an inductance value of the inductor, and the total delay value;
the voltage variation calculation module is used for converting the current variation into a voltage variation of an upper peak reference voltage value and a voltage variation of a lower peak reference voltage value;
the delay compensation module is used for superposing the voltage variation of the upper peak value reference voltage value on the upper peak value reference voltage value to obtain the upper peak value reference voltage value after delay compensation; and superposing the voltage variation of the lower peak value reference voltage value on the lower peak value reference voltage value to obtain the lower peak value reference voltage value after delay compensation.
18. The control device of a totem-pole power factor correction circuit of claim 17,
the voltage variation calculating module calculates a voltage variation of the peak reference voltage value by the following formula:
the voltage variation calculating module calculates a voltage variation of the lower peak reference voltage value by the following formula:
wherein, is Δ VCmp1A voltage variation amount that is an upper peak reference voltage value; Δ VCmp2A voltage variation amount that is a lower peak reference voltage value; vinThe instantaneous value of the input alternating voltage of the totem-pole power factor correction circuit is obtained; voutThe instantaneous value of the output direct current voltage of the totem-pole power factor correction circuit is obtained; l isPFCAn inductance value of the inductor; t isdA total delay value generated from the current collection of the inductor to the process of controlling the on and off of the main switching device; k is a corresponding proportionality coefficient between the current of the inductor and a reference voltage value; ω is the angular frequency of the voltage; t is time.
19. The control device of a totem-pole power factor correction circuit of claim 17, further comprising:
a minimum difference value obtaining module, configured to obtain a minimum difference value allowed between the delay-compensated upper peak reference voltage value and the delay-compensated lower peak reference voltage value, where the minimum difference value represents a minimum width between the upper envelope line and the lower envelope line;
the reference voltage adjusting module is used for adjusting the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle according to the minimum difference value to obtain an adjusted lower peak value reference voltage value; and adjusting the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency period according to the minimum difference value to obtain the adjusted upper peak value reference voltage value, wherein the minimum width between the adjusted lower envelope line and the adjusted upper envelope line in the power frequency period is greater than or equal to the minimum difference value.
20. The control device of a totem-pole power factor correction circuit of claim 19,
the reference voltage adjusting module adjusts the upper peak value reference voltage value after the delay compensation of the negative half cycle in the power frequency cycle through the following formula:
the reference voltage adjusting module adjusts the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle through the following formula:
wherein, V ″)Cmp1The adjusted upper peak value reference voltage value; v ″)Cmp2The adjusted lower peak value reference voltage value; v'Cmp1For the upper peak value after the delay compensation of the negative half cycle in the power frequency cycleA reference voltage value; v'Cmp2The lower peak value reference voltage value is the lower peak value reference voltage value after the delay compensation of the positive half cycle in the power frequency cycle; vGapMinIs the minimum difference; ω is the angular frequency of the voltage; t is time.
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