CN115692207A - Package substrate and manufacturing method thereof - Google Patents
Package substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN115692207A CN115692207A CN202110857608.6A CN202110857608A CN115692207A CN 115692207 A CN115692207 A CN 115692207A CN 202110857608 A CN202110857608 A CN 202110857608A CN 115692207 A CN115692207 A CN 115692207A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- solder mask
- plating
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 97
- 229910052751 metal Inorganic materials 0.000 claims abstract description 97
- 229910000679 solder Inorganic materials 0.000 claims abstract description 68
- 238000007747 plating Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 239000007788 liquid Substances 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A method for manufacturing a package substrate comprises the following steps: providing a circuit substrate, which comprises an insulating layer and a conducting layer arranged on the insulating layer, wherein the conducting layer comprises a plurality of metal pads; pressing an anti-plating dry film on one side of the conductive layer, which is far away from the insulating layer; exposing and developing the plating-resistant dry film to form a plurality of annular holes, wherein parts of the metal pads are respectively exposed out of the annular holes; forming a plurality of metal rings in the plurality of annular holes, each metal ring being connected to one metal pad; removing the plating-resistant dry film to expose the conductive layer and the plurality of metal rings; and forming a solder mask layer on one side of the circuit substrate, which is provided with the conducting layer, wherein the solder mask layer is provided with a solder mask opening, and the plurality of metal pads and the plurality of metal rings are accommodated in the solder mask opening. The invention also relates to a packaging substrate.
Description
Technical Field
The invention relates to the field of packaging substrates, in particular to a packaging substrate applied to chip packaging and a manufacturing method thereof.
Background
The flip chip technology is to make the active area of the chip face the package substrate, and to realize the interconnection with the package substrate through the solder balls arranged in an array on the chip. The surface of the packaging substrate facing the chip is provided with bonding pads arranged in an array and a solder mask layer with solder mask openings, and the bonding pads are positioned in the solder mask openings. Typically, the solder mask openings are arranged in an array and are aligned with the pads one to one. As chip die become more complex, the number of solder balls on the chip increases dramatically, resulting in smaller and smaller pad sizes and, in turn, smaller and smaller solder mask openings. When the size of the solder resist opening is too small (less than 70 μm), it is liable to cause solder resist residue to fall onto the pad located in the solder resist opening, increasing the risk that the chip and the pad do not make good contact.
Disclosure of Invention
In view of the above, the present invention provides a package substrate that solves the above technical problems.
A method for manufacturing the package substrate is also provided to solve the above technical problems.
One aspect of the present application provides a method for manufacturing a package substrate, which includes the following steps:
providing a circuit substrate, which comprises an insulating layer and a conducting layer arranged on the insulating layer, wherein the conducting layer comprises a plurality of metal pads;
pressing an anti-plating dry film on one side of the conductive layer, which is far away from the insulating layer;
exposing and developing the plating-resistant dry film to form a plurality of annular holes, wherein parts of the metal pads are respectively exposed out of the annular holes;
forming a plurality of metal rings in the plurality of annular holes, each metal ring being connected to one metal pad;
removing the plating-resistant dry film to expose the conductive layer and the plurality of metal rings;
and forming a solder mask layer on one side of the circuit substrate, which is provided with the conducting layer, wherein the solder mask layer is provided with a solder mask opening, and the metal pads and the metal rings are accommodated in the solder mask opening.
The application on the other hand provides a packaging substrate, including circuit substrate, set up in circuit substrate one side and with a plurality of metal pads that circuit substrate electricity is connected and be located the solder mask layer in the circuit substrate outside, the solder mask layer has a solder mask opening, a plurality of metal pads follow the solder mask opening exposes, and every metal pad is gone up the protruding becket that is equipped with, the becket holding is in the solder mask opening.
According to the packaging substrate and the manufacturing method thereof, the plurality of the welding pads are arranged in one welding-proof opening, so that the size of the welding-proof opening can be large enough, and the problem caused by the fact that the size of the welding-proof opening is too small is solved; the metal pad is provided with a metal ring for accommodating the solder balls, so that the risk of contact short circuit of the adjacent solder balls caused by spreading of the solder balls in the reflow soldering process can be reduced; and when the metal ring is formed in the annular hole by the pattern electroplating process, the height of the metal ring can be adjusted to adapt to chips with different pin sizes/solder ball sizes.
Drawings
Fig. 1 to 8 are schematic cross-sectional views illustrating a manufacturing process of a package substrate according to an embodiment of the present disclosure.
Fig. 9A is a schematic structural diagram of a bonding pad according to an embodiment of the present application.
Fig. 9B is a top view of the pad shown in fig. 9A.
Fig. 10 is a schematic cross-sectional view of an electronic assembly according to an embodiment of the present application.
Description of the main elements
Plating resist dry film 30
Solder mask opening 501
Solder mask ink 51
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following embodiments and features of the embodiments may be combined with or substituted for each other without conflict.
Referring to fig. 1 to 8, a first embodiment of the present invention provides a method for manufacturing a package substrate 100, which includes the following steps:
step S1, referring to fig. 1, a circuit substrate 10 is provided, which includes an insulating layer 11 and two conductive layers 12 disposed on two opposite surfaces of the insulating layer 11. The two conductive layers 12 are electrically connected by a conductive structure 13 that penetrates the insulating layer 11. The conductive structure 13 may be a conductive hole or a conductive pillar. In other embodiments, the number of the conductive layers 12 may be one, and the application is not limited thereto.
The conductive layer 12 includes a plurality of metal pads 121 and a plurality of conductive line patterns 122. The plurality of metal pads 121 are electrically connected to the plurality of conductive line patterns 122.
The insulating layer 11 is a dielectric material commonly used in the art, such as a polyimide substrate, epoxy resin, etc. The material of the conductive layer 12 may include, but is not limited to, copper, gold, silver, etc.
Step S2, referring to fig. 2, a metal plating layer 20 is coated on the surface of the conductive layer 12 by a magnetron sputtering process.
The metal plating layer 20 serves as a conductive substrate, and the material thereof may include, but is not limited to, copper, gold, silver, and the like. The metal plating layer 20 completely covers the metal pad 121 and the exposed surface of the conductive line pattern 122 not in contact with the insulating layer 11.
In some embodiments, the metal plating 20 has a thickness of 0.2 μm.
In step S3, referring to fig. 3, an anti-plating dry film 30 is pressed on a side of the conductive layer 12 away from the insulating layer 11. The plating resist film 30 completely covers the conductive layer 12 and fills gaps between the metal pads 121 and the conductive line patterns 122.
The plating-resistant dry film 30 is a photosensitive dry film for selective electroplating or chemical plating. The plating resist film 30 has high resolution. The thickness of the plating resistant dry film 30 is determined by the model, in the present embodiment, the model of the plating resistant dry film 30 is LDF438, and the thickness of the plating resistant dry film 30 is 25 to 40 μm.
Step S4, referring to fig. 4, exposing and developing the plating resist film 30 to form a plurality of annular holes 301, wherein the metal plating layers 20 covering the metal pads 121 are exposed from the plurality of annular holes 301, respectively. The plurality of annular holes 301 and the plurality of metal pads 121 correspond one to one.
The distance between two adjacent annular holes 301 can be adjusted according to actual requirements. In the present embodiment, the pitch between two adjacent annular holes 301 is 20 μm.
The exposure process adopts ultraviolet light for exposure, and the exposure energy is determined by the type of a dry film and the thickness of the dry film. In this embodiment, the anti-plating dry film 30 is exposed by an LDI exposure machine, and the exposure energy of the exposure machine is 70mJ.
The developing process can adopt weak alkali developing solution to develop the dry film. The developing capacity of the developing solution is 10-30 mu m.
In step S5, referring to fig. 5, a metal ring 40 is formed in the annular hole 301 by a pattern plating process. Wherein each metal ring 40 is formed on a corresponding metal pad 121, and each metal pad 121 and the corresponding metal ring 40 together constitute a bonding pad of the package substrate. In the present embodiment, each metal ring 40 is formed on a portion of the metal plating layer 20 located on the corresponding metal pad 121. In other embodiments, the metal plating layer 20 may be omitted, and each metal ring 40 may be directly formed on the corresponding metal pad 121.
The height of the metal ring 40 is less than or equal to the thickness of the plating resistant film 30.
Step S6, referring to fig. 6, the plating resist film is removed to expose the conductive layer 12 and the pad.
The plating-resistant dry film can be directly torn off, but is not limited thereto.
It is understood that after step S6, the following steps are also included: the metal plating 20 not covered by the metal ring 40 is removed to further expose the conductive layer 12.
In this embodiment, the metal plating layer 20 is removed by a micro-etching process.
Step S7, referring to fig. 8, forming a solder mask layer 50 covering the conductive layer 12 and the insulating layer 11 on the side of the circuit substrate 10 provided with the conductive layer 12 to obtain the package substrate 100, wherein the solder mask layer 50 has a plurality of solder mask openings 501, and each solder mask opening 501 accommodates a plurality of pads.
A plurality of pads are disposed in one solder mask opening 501, so that the size of the solder mask opening 501 can be sufficiently large, reducing the problem caused by the undersize of the solder mask opening.
The total height of the metal pads 121 and the corresponding metal rings 40 is less than or equal to the depth of the solder mask openings 501.
In the present embodiment, the solder mask layer 50 is made of a liquid photosensitive solder mask ink. Specifically, step S7 includes:
step S71, referring to fig. 7, printing liquid photosensitive solder mask ink 51 on the surface of the conductive layer 12 and the gap between the conductive trace pattern 122 and the metal pad 121; pre-baking to pre-cure the surface of the liquid photosensitive solder mask ink 51;
step S72, please refer to fig. 8, in which a cross-linking reaction occurs in a partial area of the liquid photosensitive solder mask ink by selective UV exposure; removing the area of the liquid photosensitive solder mask ink which is not subjected to the cross-linking reaction through a developing process to form the solder mask opening 501; and finally, heating and curing the liquid photosensitive solder mask ink to obtain the solder mask layer 50.
Referring to fig. 9A and 9B, the metal ring 40 protrudes from the metal pad 121, and the edge of the metal ring 40 does not extend beyond the edge of the metal pad 121. The outer diameter D and the thickness W of the metal ring 40 can be adjusted by adjusting the resolution of the plating-resistant dry film 30, the thickness of the plating-resistant dry film 30 and the developing parameters when the annular hole is formed by developing, and the height H of the metal ring 40 can be adjusted by adjusting the current density in the pattern electroplating process so as to adapt to chips with different pin sizes/tin ball sizes.
Referring to fig. 10, in some embodiments, after step S7, the following steps are further included: the chip 70 is flip-chip mounted on a plurality of pads located in one solder resist opening 501. The chip 70 is connected to the metal pads 121 via solder balls 60.
In this embodiment, the solder ball 60 is a solder ball, and is soldered on the metal pad 121 by a reflow soldering process. The solder balls 60 are accommodated in the space surrounded by the metal ring 40 and the metal pad 121, and the solder balls are wrapped by the metal ring 40, so that the risk of contact short circuit of adjacent solder balls caused by spreading of the solder balls in the reflow soldering process can be reduced.
In this embodiment, the chip 70 is an integrated passive device chip, and the passive device includes but is not limited to an inductor, a capacitor, a resistor, a filter, an antenna, a passive rf circuit, and the like.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.
Claims (10)
1. A manufacturing method of a package substrate is characterized by comprising the following steps:
providing a circuit substrate, which comprises an insulating layer and a conducting layer arranged on the insulating layer, wherein the conducting layer comprises a plurality of metal pads;
pressing an anti-plating dry film on one side of the conductive layer, which is far away from the insulating layer;
exposing and developing the plating-resistant dry film to form a plurality of annular holes, wherein parts of the metal pads are respectively exposed out of the annular holes;
forming a plurality of metal rings in the plurality of annular holes, each metal ring being connected to one metal pad;
removing the plating resistance dry film to expose the conductive layer and the plurality of metal rings;
and forming a solder mask layer on one side of the circuit substrate, which is provided with the conducting layer, wherein the solder mask layer is provided with a solder mask opening, and the metal pads and the metal rings are accommodated in the solder mask opening.
2. The method for manufacturing a package substrate according to claim 1, wherein before the step of pressing a plating resist film on a side of the conductive layer away from the insulating layer, the method further comprises:
and covering a metal plating layer on the exposed surface of the conductive layer, wherein the plurality of metal rings are formed on the metal plating layer.
3. The method for manufacturing a package substrate according to claim 2, further comprising, after the step of removing the plating resist film to expose the conductive layer and the metal rings:
and removing the metal plating layer which is not covered by the metal ring.
4. The method of claim 1, wherein a total height of each metal pad and the corresponding metal ring is less than or equal to a depth of the solder mask opening.
5. The method of claim 1, wherein a plurality of metal rings are formed in the plurality of annular holes by a pattern plating process.
6. The method for manufacturing the package substrate according to claim 5, wherein the height of the metal ring is less than or equal to the thickness of the plating resistance film.
7. A packaging substrate is characterized by comprising a circuit substrate, a plurality of metal pads and a solder mask layer, wherein the metal pads are arranged on one side of the circuit substrate and electrically connected with the circuit substrate, the solder mask layer is positioned on the outer side of the circuit substrate, the solder mask layer is provided with a solder mask opening, the metal pads are exposed out of the solder mask opening, each metal pad is convexly provided with a metal ring, and the metal rings are accommodated in the solder mask opening.
8. The package substrate of claim 7, wherein a total height of each metal pad and corresponding metal ring is less than or equal to a depth of the solder mask opening.
9. The package substrate of claim 7, wherein each metal pad is sandwiched with a metal plating layer between the corresponding metal ring.
10. The package substrate of claim 7, wherein each metal pad is sandwiched with a metal plating layer between the corresponding metal ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110857608.6A CN115692207A (en) | 2021-07-28 | 2021-07-28 | Package substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110857608.6A CN115692207A (en) | 2021-07-28 | 2021-07-28 | Package substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115692207A true CN115692207A (en) | 2023-02-03 |
Family
ID=85058742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110857608.6A Pending CN115692207A (en) | 2021-07-28 | 2021-07-28 | Package substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115692207A (en) |
-
2021
- 2021-07-28 CN CN202110857608.6A patent/CN115692207A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6041495A (en) | Method of manufacturing a circuit board having metal bumps and a semiconductor device package comprising the same | |
| US7705456B2 (en) | Semiconductor package substrate | |
| US7151050B2 (en) | Method for fabricating electrical connection structure of circuit board | |
| US20060219567A1 (en) | Fabrication method of conductive bump structures of circuit board | |
| KR20110003453A (en) | Structure of circuit board and method for fabricating the same | |
| US20140027893A1 (en) | Circuit substrate for mounting chip, method for manufacturing same and chip package having same | |
| US20080185711A1 (en) | Semiconductor package substrate | |
| US7419897B2 (en) | Method of fabricating circuit board having different electrical connection structures | |
| US7553750B2 (en) | Method for fabricating electrical conductive structure of circuit board | |
| US20040012097A1 (en) | Structure and method for fine pitch flip chip substrate | |
| US20090102050A1 (en) | Solder ball disposing surface structure of package substrate | |
| US7216424B2 (en) | Method for fabricating electrical connections of circuit board | |
| US7627946B2 (en) | Method for fabricating a metal protection layer on electrically connecting pad of circuit board | |
| US9021690B2 (en) | Method of manufacturing printed circuit board having buried solder bump | |
| KR20100120574A (en) | Manufacturing method of flip chip-micro bump in semiconductor package | |
| US7135377B1 (en) | Semiconductor package substrate with embedded resistors and method for fabricating same | |
| US7323762B2 (en) | Semiconductor package substrate with embedded resistors and method for fabricating the same | |
| TWI419630B (en) | Embedded printed circuit board and method of manufacturing the same | |
| US8186043B2 (en) | Method of manufacturing a circuit board | |
| KR100894178B1 (en) | Method for manufacturing printed circuit board | |
| US7544599B2 (en) | Manufacturing method of solder ball disposing surface structure of package substrate | |
| CN101783302B (en) | Method for forming pre-welding material of packaging base plate | |
| US20080083115A1 (en) | Method for repairing metal finish layer on surface of electrical connection pad of circuit board | |
| JP2009099730A (en) | Solder ball arrangement-side surface structure of package board, and its manufacturing method | |
| CN115692207A (en) | Package substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240204 Address after: 066004 No. 18-2, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province Applicant after: Liding semiconductor technology Qinhuangdao Co.,Ltd. Country or region after: China Applicant after: Liding semiconductor technology (Shenzhen) Co.,Ltd. Address before: No.18, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province 066004 Applicant before: Qi Ding Technology Qinhuangdao Co.,Ltd. Country or region before: China Applicant before: Liding semiconductor technology (Shenzhen) Co.,Ltd. |
|
| TA01 | Transfer of patent application right |