CN115632034A - eMMC module package structure and manufacturing method thereof - Google Patents
eMMC module package structure and manufacturing method thereof Download PDFInfo
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- CN115632034A CN115632034A CN202211637458.9A CN202211637458A CN115632034A CN 115632034 A CN115632034 A CN 115632034A CN 202211637458 A CN202211637458 A CN 202211637458A CN 115632034 A CN115632034 A CN 115632034A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 238000004806 packaging method and process Methods 0.000 claims abstract description 33
- 238000003860 storage Methods 0.000 claims abstract description 14
- 238000005538 encapsulation Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 83
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000002390 adhesive tape Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000006303 photolysis reaction Methods 0.000 description 1
- 230000015843 photosynthesis, light reaction Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
Abstract
The application discloses an eMMC module packaging structure and a manufacturing method thereof, wherein the eMMC module packaging structure comprises at least two layers of circuit layer substrates, a cavity structure is further formed in each substrate, a main control chip and a passive component are arranged in the cavity structure, pins of the main control chip and the passive component are electrically connected with the circuit layer on the surface of the substrate, a storage chip is arranged on one surface of each substrate, the storage chip is electrically connected with the circuit layer on the surface of the substrate in a lead bonding mode, and a plastic sealing layer is located on one surface of the substrate, provided with the storage chip, and wraps the storage chip. Inside main control chip and passive components and parts are buried in the base plate, saved the space on base plate surface, can hold large tracts of land memory chip, compare in the packaging structure who raises memory chip at present, the packaging structure of this application embodiment can reduce encapsulation thickness for the eMMC chip is more frivolous.
Description
Technical Field
The application relates to the field of semiconductor processes, in particular to an eMMC module packaging structure and a manufacturing method thereof.
Background
The eMMC (Embedded Multi Media Card) is an Embedded memory standard specification established by the MMC association, and the standard specification packaging size is 11.5mm × 13mm, and is also specially designed for mobile phones and mobile Embedded products, and it adopts a unified MMC standard interface to package a high-density memory chip and a main control chip in a BGA (Ball Grid Array, ball Grid Array packaging technology) chip.
Along with the increase of the capacity of the eMMC, the area of a storage chip inside the eMMC is larger and larger, and even reaches 90% of the packaging area of the eMMC, so that the main control chip of the eMMC is not placed reasonably, and the wiring work of a substrate cannot be finished. Although the memory chip can be raised by a bare chip or a DAF (Die Attach Film) in the industry so that the main control chip obtains a sufficient wire loop height and a sufficient wiring space, such a structure increases the overall package thickness, increases the cost due to an increase in the package process, and risks of plastic package voids.
Disclosure of Invention
The embodiment of the application provides an eMMC module packaging structure and a manufacturing method thereof, which can reduce the packaging thickness.
In a first aspect, an embodiment of the present application provides an eMMC module package structure, including:
the circuit board comprises a substrate, wherein the substrate is at least a two-layer circuit layer substrate, the substrate is also provided with a cavity structure, a main control chip and a passive component are arranged in the cavity structure, and pins of the main control chip and the passive component are electrically connected with a circuit layer on the surface of the substrate;
the memory chip is arranged on one surface of the substrate and is electrically connected with the circuit layer on the surface of the substrate in a lead bonding mode;
and the plastic packaging layer is positioned on one surface of the substrate, which is provided with the storage chip, and wraps the storage chip.
In an embodiment, the main control chip and the passive component are not higher than any surface of the substrate, and the cavity structure is filled with an encapsulating material to form an encapsulating body.
In one embodiment, a surface of the encapsulation body is flush with a surface of the circuit layer of the substrate.
In an embodiment, the two circuit layers of the substrate include an upper circuit layer located on the upper surface of the substrate and a lower circuit layer located on the lower surface of the substrate, the substrate further includes a first via hole penetrating through the upper and lower surfaces, and the upper circuit layer and the lower circuit layer are electrically connected through the first via hole.
In an embodiment, the pins of the main control chip and the passive component face downward and are electrically connected to the lower circuit layer, or the pins of the main control chip and the passive component face upward and are electrically connected to the upper circuit layer.
In an embodiment, the main control chip and the passive component are disposed near the lower surface of the substrate, and the main control chip and the passive component are electrically connected to the upper circuit layer through the second via hole under the condition that the pins of the main control chip and the passive component face upward.
In an embodiment, an area of the memory chip is more than 70% of a package area corresponding to the molding layer.
In a second aspect, an embodiment of the present application provides a method for manufacturing an eMMC module package structure, which is used to manufacture the eMMC module package structure of the first aspect; the manufacturing method comprises the following steps:
forming a cavity structure on a double-sided copper-clad substrate, and applying an adhesive layer on the lower surface of the double-sided copper-clad substrate;
adhering a main control chip and a passive component from the upper surface of the double-sided copper-clad substrate to the cavity structure;
completely filling the cavity structure with an encapsulating material to form an encapsulating body for encapsulating the main control chip and the passive component;
removing the adhesive layer, and manufacturing circuit layers on the upper surface and the lower surface of the double-sided copper-clad substrate;
arranging a memory chip on the upper surface of the double-sided copper-clad substrate, and completing the connection of the memory chip and the circuit layer in a lead bonding mode;
carrying out plastic package on the storage chip to form a plastic package layer;
and forming a solder ball on the lower surface of the double-sided copper-clad substrate.
In an embodiment, after the cavity structure is completely filled with the encapsulating material, the method further includes:
and removing the packaging material higher than the upper surface of the double-sided copper-clad substrate to enable the surface of the packaging body and the upper surface of the double-sided copper-clad substrate to be in the same plane.
In one embodiment, when the pins of the main control chip and the passive component are placed downwards in the cavity structure, the pins of the main control chip and the passive component are electrically connected with the circuit layer on the lower surface of the double-sided copper-clad substrate;
when the pins of the main control chip and the passive component are placed in the cavity structure in an upward direction, after the cavity structure is completely filled with the encapsulating material, the method further includes:
and forming a second via hole on the encapsulating body according to the positions of the pins of the main control chip and the passive component, so that the pins of the main control chip and the passive component are electrically connected with the circuit layer on the upper surface of the double-sided copper-clad substrate through the second via hole.
The eMMC module packaging structure and the manufacturing method thereof provided by the embodiment of the application have at least the following beneficial effects: compared with the conventional packaging structure for the elevated memory chip, the packaging structure can reduce the packaging thickness, so that the eMMC chip is lighter and thinner; on the other hand, the main control chip and the passive component are not connected to the circuit board of the substrate in a lead bonding mode any more, but are connected to the circuit board on the surface of the substrate inside the substrate, so that the transmission path is shortened, and the performance of the chip is improved; in addition, a passive component of the copper terminal can be adopted, so that the copper terminal and the circuit layer can be integrally formed, and the reliability problem is avoided.
Drawings
FIG. 1 is a schematic diagram of a package structure of an elevated memory chip of a prior art solution;
fig. 2 is a schematic view of a module package structure with a downward lead according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a module package structure with its leads facing upward according to an embodiment of the present application;
FIGS. 4-12 are flow diagrams of a method for manufacturing a lead-down condition according to an embodiment of the present application;
fig. 13 to 19 are flow charts of a manufacturing method for a pin-up situation according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be understood that, in this application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
It should be understood that in the description of the embodiments of the present application, a plurality (or a plurality) means two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number.
Referring to the packaging solution shown in fig. 1, a bare chip or DAF is used to raise the memory chip, so that the main control chip obtains sufficient wire loop height and wiring space, which obviously results in increased packaging thickness, relatively complex process, and risk of plastic package voids (in fig. 1, the reference numerals are: main control chip 1, memory chip 2, passive component 3, bare chip 4, substrate 5, plastic package layer 6, and solder balls 8). Accordingly, the embodiment of the application provides an eMMC module packaging structure and a manufacturing method thereof.
Referring to fig. 2 and 3, an embodiment of a first aspect of the present application provides an eMMC module package structure, including:
the circuit board comprises a substrate 7 which is at least a two-layer circuit layer substrate, wherein the substrate 7 is further provided with a cavity structure 71, a main control chip 1 and a passive component 3 are arranged in the cavity structure 71, and pins of the main control chip 1 and the passive component 3 are electrically connected with a circuit layer on the surface of the substrate 7;
the memory chip 2 is arranged on one surface of the substrate 7, and the memory chip 2 is electrically connected with the circuit layer on the surface of the substrate 7 in a wire bonding mode;
and the plastic packaging layer 6 is positioned on one surface of the substrate 7, which is provided with the memory chip 2, and wraps the memory chip 2.
The cavity structure 71 is formed in the substrate 7, and a through structure may be formed on the substrate 7 as the cavity structure 71 by stamping or laser grooving. Structurally, the main control chip 1 and the passive component 3 (including circuit devices such as resistors and inductors) are placed in the cavity structure 71, and the cavity structure 71 is filled with an encapsulating material, so that an encapsulating body for encapsulating the main control chip 1 and the passive component 3 is obtained. In this way, the main control chip 1 and the passive component 3 can not occupy the space on the surface of the substrate 7, and the memory chip 2 can be arranged on the surface of the substrate 7. Compared with the existing solution of raising the memory chip 2, the embodiment of the application can reduce the height after packaging, so that the eMMC chip is lighter and thinner.
The main control chip 1 and the passive component 3 are not higher than any surface of the substrate 7, and the cavity structure 71 is filled with an encapsulating material to form an encapsulating body. And the surface of the encapsulation is flush with the surface of the wiring layer of the substrate 7. Make main control chip 1 and passive components and parts 3 can bury completely inside base plate 7 like this, the surface of the encapsulated body is owing to flush with the surface on the circuit layer of base plate 7, consequently can directly arrange memory chip 2 above base plate 7 and need not memory chip 2 dodge the position at encapsulated body place, has improved packaging structure's internal utilization.
It is understood that the two circuit layers of the substrate 7 include an upper circuit layer 73 located on the upper surface of the substrate 7 and a lower circuit layer 72 located on the lower surface of the substrate 7, the substrate 7 further includes a first via hole 74 penetrating through the upper and lower surfaces, and the upper circuit layer 73 and the lower circuit layer 72 are electrically connected through the first via hole 74. The upper circuit layer 73 is used to connect the memory chip 2, and the lower circuit layer 72 is used to match with the external leads (such as solder balls) formed after the package. The main control chip 1 and the passive component 3 are connected to the upper circuit layer 73 or the lower circuit layer 72 according to the difference of the orientation (upward or downward) when they are placed in the cavity structure 71. The upper circuit layer 73 and the lower circuit layer 72 are electrically connected through the first via hole 74, such that the memory chip 2, the upper circuit layer 73 and the lower circuit layer 72 are electrically connected.
The placing mode of main control chip 1 and passive components and parts 3 divide into two kinds in this application, and one kind is that the pin of main control chip 1 and passive components and parts 3 is down, and another kind is that the pin of main control chip 1 and passive components and parts 3 is up. The pins of the main control chip 1 and the passive component 3 are electrically connected to the lower circuit layer 72 when the pins face downward, as shown in fig. 2, and the pins of the main control chip 1 and the passive component 3 are electrically connected to the upper circuit layer 73 when the pins face upward, as shown in fig. 3.
Since the main control chip 1 and the passive component 3 need to be fixed in the cavity structure 71 in the manufacturing process, the main control chip 1 and the passive component 3 are disposed near the lower surface of the substrate 7 in the actual package structure. At this time, if the pin is upward, the main control chip 1 and the passive component 3 are away from the upper circuit layer 73 by a certain distance, and the pins of the upper circuit layer 73, the main control chip 1 and the passive component 3 need to be communicated through the second via hole 75.
For the lower circuit layer 72, since the package pins need to be led out during the plastic package process, gold fingers can be arranged and solder balls can be arranged on the OSP windows as the package pins by using an OSP (Organic solder resist film) process. The memory specification established according to eMMC requires 153 solder balls.
The area of the memory chip 2 is more than 70% of the corresponding packaging area of the plastic packaging layer 6, so that the area utilization rate of the packaging structure is ensured.
Based on the foregoing eMMC module package structure according to the first aspect, a second aspect of the present application provides a manufacturing method, for manufacturing the eMMC module package structure according to the first aspect, which includes the following steps, as shown in fig. 4 to fig. 19:
step S100, forming a cavity structure 93 on a double-sided copper-clad substrate 9, and applying an adhesive layer on the lower surface of the double-sided copper-clad substrate 9;
step S200, adhering the main control chip 1 and the passive component 3 from the upper surface of the double-sided copper-clad substrate 9 to the cavity structure 93;
step S300, completely filling the cavity structure 93 with an encapsulating material to form an encapsulating body 95 for encapsulating the main control chip 1 and the passive component 3;
step S400, removing the adhesive layer, and manufacturing circuit layers on the upper surface and the lower surface of the double-sided copper-clad substrate 9;
step S500, arranging the memory chip 2 on the upper surface of the double-sided copper-clad substrate 9, and completing the connection of the memory chip 2 and the circuit layer in a lead bonding mode;
step S600, carrying out plastic packaging on the storage chip 2 to form a plastic packaging layer;
in step S700, solder balls are formed on the lower surface of the double-sided copper-clad substrate 9.
The double-sided copper-clad substrate 9 in the above steps is equivalent to the substrate and the upper and lower circuit layers in the first embodiment, and since the thickness of the upper and lower circuit layers is very small, the height of the elevated memory chip 2 in the existing solution can be ignored, so the description will be continued in the following description according to the first embodiment.
In order to make the surface of the encapsulant 95 flush with the surface of the double-sided copper-clad substrate 9, step S300 further includes, after the cavity structure 93 is completely filled with an encapsulant:
step S301, removing the encapsulant higher than the upper surface of the double-sided copper-clad substrate 9, so that the surface of the encapsulant 95 and the upper surface of the double-sided copper-clad substrate 9 are on the same plane.
As can be seen from the foregoing, different eMMC module package structures are presented for different orientations of the main control chip 1 and the passive component 3, and therefore, there are some differences in corresponding manufacturing methods.
When the pins of the main control chip 1 and the passive component 3 are placed downwards in the cavity structure 93, the pins of the main control chip 1 and the passive component 3 are electrically connected with the circuit layer on the lower surface of the double-sided copper-clad substrate 9;
when the pins of the main control chip 1 and the passive component 3 are placed in the cavity structure 93 upward, the step S300 further includes, after the cavity structure 93 is completely filled with the encapsulating material:
step S302, forming a second via hole on the encapsulant 95 according to the positions of the pins of the main control chip 1 and the passive component 3, so that the pins of the main control chip 1 and the passive component 3 are electrically connected to the circuit layer on the upper surface of the double-sided copper-clad substrate 9 through the second via hole.
The above-mentioned preparation method is detailed as follows: preparing a double-sided copper-clad substrate 9, wherein the copper-clad substrate 9 is composed of a core board 91 (equivalent to a simple substrate) and a copper layer 92; forming a cavity structure 93 on the copper-clad substrate 9 in a stamping or laser grooving mode; applying an adhesive tape 94 on one surface of the copper-clad substrate 9; the main control chip 1 and the passive component 3 are accurately adhered into the cavity structure 93 through a chip mounter, and the upper core of the main control chip 1 is divided into a face down type and a face up type according to different structures, wherein the face down type is firstly described (fig. 4 to fig. 12); completely filling the cavity structure 93 with an encapsulating material in a laminating or liquid coating mode to form an encapsulating body 95, wherein the encapsulating body 95 completely comprises the main control chip 1 and the passive component 3, and then removing the redundant encapsulating body 95 by grinding or plasma thinning process to expose the surface of the copper layer 92, wherein the upper surface of the encapsulating body 95 and the copper surface are positioned on the same plane; the adhesive tape 94 is completely peeled off by losing the adhesiveness of the adhesive tape 94 by means of photolysis or pyrolysis. Forming a circuit layer, a first via hole 96 and a solder mask layer 98 by a substrate manufacturing process, wherein the substrate manufacturing process comprises drilling, chemical copper deposition, electroplating, hole plugging, pattern transfer, circuit layer manufacturing, solder mask layer 98 manufacturing and chemical surface treatment, so as to form a chip embedded substrate; placing the memory chips 22 on the substrate surface by a core-loading manner, wherein all the adhesive materials are thin DAF or silver paste, and the number of the memory chips 2 is at least one; the I/O of the memory chip 2 is connected with a bonding golden finger on the substrate by a metal wire in a pressure welding mode, and the commonly used bonding metal wire comprises a series of metal wires with good conductivity and plasticity, such as a gold wire, a silver alloy wire, a copper wire and the like; and applying a plastic packaging layer through a plastic packaging process to completely encapsulate the memory chip 2, and then applying solder balls on the other side of the substrate, so that the memory chip is conveniently connected with a PCB (printed circuit board) in a surface mounting reflow soldering manner.
For the case that the upper core of the main control chip 1 adopts a face up placement manner, the manufacturing process is substantially the same (fig. 13 to fig. 19), after the encapsulant 95 is formed, the terminal surfaces of the main control chip 1 and the passive component 3 are exposed by laser, and then the blind hole is filled to form a second via hole, and the second via hole is connected with the upper circuit layer 97.
The main control chip 1 and the passive component 3 are embedded in the substrate, so that the surface space is saved, a large-area storage chip 2 can be accommodated, and the packaging thickness can be thinner.
The electrical connection mode of the main control chip 1 which is commonly used at present is a mode of wire bonding, the packaging structure of the embodiment of the application cancels the connection structure of wire bonding, and directly adopts the connection of the I/O of the main control chip 1 and the circuit layer, thereby shortening the transmission path and improving the performance of the chip.
The conventional passive component 3 adopts a tin terminal, but the passive component 3 with the tin terminal is influenced by storage conditions and has different rework operation modes, so that the problem of short circuit reliability is easily caused. The structure of the embodiment of the application can adopt the passive component 3 of the copper terminal, and the terminal and the circuit layer are integrally formed, so that the reliability problem is avoided.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are to be included within the scope of the present invention defined by the claims.
Claims (10)
1. The utility model provides a eMMC module packaging structure which characterized in that: comprises that
The circuit board comprises a substrate, at least two circuit layer substrates, and a cavity structure, wherein a main control chip and a passive component are arranged in the cavity structure, and pins of the main control chip and the passive component are electrically connected with the circuit layer on the surface of the substrate;
the memory chip is arranged on one surface of the substrate and is electrically connected with the circuit layer on the surface of the substrate in a wire bonding mode;
and the plastic packaging layer is positioned on one surface of the substrate, which is provided with the storage chip, and wraps the storage chip.
2. The eMMC module package structure of claim 1, wherein the master chip and the passive component are not higher than any surface of the substrate, and the cavity structure is filled with an encapsulation material to form an encapsulation.
3. The eMMC module package structure of claim 2, wherein a surface of the encapsulant is flush with a surface of the circuit layer of the substrate.
4. The eMMC module package structure of claim 1, wherein the two circuit layers of the substrate include an upper circuit layer on the upper surface of the substrate and a lower circuit layer on the lower surface of the substrate, the substrate further including a first via hole through the upper and lower surfaces, the upper and lower circuit layers being electrically connected by the first via hole.
5. The eMMC module package structure of claim 4, wherein the pins of the master chip and the passive component face downward and are electrically connected to the lower circuit layer, or wherein the pins of the master chip and the passive component face upward and are electrically connected to the upper circuit layer.
6. The eMMC module package structure of claim 5, wherein the master chip and the passive component are disposed proximate to a lower surface of the substrate, the master chip and the passive component being electrically connected to the upper circuit layer through a second via hole with pins of the master chip and the passive component facing up.
7. The eMMC module package structure of claim 1, wherein an area of the memory chip is greater than 70% of a package area corresponding to the molding layer.
8. A method of fabricating an eMMC module package structure, the eMMC module package structure being configured to be fabricated according to any one of claims 1 to 7, the method comprising:
forming a cavity structure on a double-sided copper-clad substrate, and applying an adhesive layer on the lower surface of the double-sided copper-clad substrate;
adhering a main control chip and a passive component from the upper surface of the double-sided copper-clad substrate to the cavity structure;
completely filling the cavity structure with an encapsulating material to form an encapsulating body for encapsulating the main control chip and the passive component;
removing the adhesive layer, and manufacturing circuit layers on the upper surface and the lower surface of the double-sided copper-clad substrate;
arranging a memory chip on the upper surface of the double-sided copper-clad substrate, and completing the connection of the memory chip and the circuit layer in a lead bonding mode;
carrying out plastic packaging on the storage chip to form a plastic packaging layer;
and forming a solder ball on the lower surface of the double-sided copper-clad substrate.
9. The method of manufacturing according to claim 8, further comprising, after completely filling the cavity structure with an encapsulating material:
and removing the encapsulating material higher than the upper surface of the double-sided copper-clad substrate to enable the surface of the encapsulating body and the upper surface of the double-sided copper-clad substrate to be positioned on the same plane.
10. The manufacturing method of claim 8, wherein when the pins of the main control chip and the passive component are placed downward in the cavity structure, the pins of the main control chip and the passive component are electrically connected with the circuit layer on the lower surface of the double-sided copper-clad substrate;
when the pins of the main control chip and the passive component are placed in the cavity structure in an upward direction, after the cavity structure is completely filled with an encapsulating material, the method further includes:
and forming a second via hole on the encapsulating body according to the pin positions of the main control chip and the passive component, so that the pins of the main control chip and the passive component are electrically connected with the circuit layer on the upper surface of the double-sided copper-clad substrate through the second via hole.
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