CN115621232B - Power semiconductor device packaging structure and power semiconductor device module - Google Patents
Power semiconductor device packaging structure and power semiconductor device module Download PDFInfo
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- CN115621232B CN115621232B CN202211405492.3A CN202211405492A CN115621232B CN 115621232 B CN115621232 B CN 115621232B CN 202211405492 A CN202211405492 A CN 202211405492A CN 115621232 B CN115621232 B CN 115621232B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000002788 crimping Methods 0.000 claims abstract description 65
- 230000005489 elastic deformation Effects 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229910010293 ceramic material Inorganic materials 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- 230000006835 compression Effects 0.000 abstract description 10
- 238000007906 compression Methods 0.000 abstract description 10
- 230000017525 heat dissipation Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
The invention provides a power semiconductor device packaging structure and a power semiconductor device module. The power semiconductor device package structure includes: the power chip is connected with the first crimping electrode module through the elastic electrode; the lining plate is arranged on one side surface of the first electrode, and the insulating plate and the power chip are positioned on the same side surface of the first electrode; the second electrode of the chip and the third electrode of the chip are respectively and electrically connected to different lining plates; one end of the elastic electrode is suitable for being elastically connected with one of the lining plates, and the other end of the elastic electrode is connected with the second electrode of the device or the third electrode of the device; the elastic electrode is suitable for elastically stretching along the direction of the second compression joint electrode module to the first compression joint electrode module; the first crimping electrode module and the second crimping electrode module are suitable for opposite movement by applying external force, and electric conduction with the power chip is realized through elastic deformation of the elastic electrode.
Description
Technical Field
The invention relates to the technical field of power device packaging, in particular to a power semiconductor device packaging structure and a power semiconductor device module.
Background
There are currently two main types of packages for high voltage power semiconductor devices, one is a solder type device and one is a crimp type device. The crimping type device has various advantages such as higher power density, stronger heat dissipation capacity, stronger power cycle tolerance capacity and the like. However, for the crimping device with multiple chips connected in parallel, pressure equalization control is an outstanding technical problem, and pressure imbalance can cause a series of problems, such as increased contact thermal resistance, increased current dispersion, chip cracking and the like, and finally, the device can be disabled.
With the development of third generation semiconductor materials, high-voltage SiC power semiconductor chips are continuously developed, but are limited by the defects of the SiC materials, the chip area cannot be generally large, and the size is generally smaller. Small-sized chips are currently difficult to package using crimping. Because of the small size and difficult positioning of the chip, the elastic electrode pressing block is extremely easy to press to the chip terminal to cause chip failure, and for packaging of high-voltage power semiconductor devices, how to realize the press-connection packaging of small-size chips, especially SiC chips, is a prominent problem.
Disclosure of Invention
The invention provides a power semiconductor device packaging structure, which solves the problem that a high-voltage power chip, particularly a SiC chip, is difficult to adopt crimping packaging.
The invention provides a power semiconductor device packaging structure, comprising: the first crimping electrode module comprises a device first electrode and an electrode frame which is positioned around the device first electrode; the power chip is arranged on the first crimping electrode module; the first electrode of the power chip is electrically connected with the first electrode of the device; the second crimping electrode module is arranged opposite to the first crimping electrode module; the second crimping electrode module comprises a device second electrode and a device third electrode, the device second electrode is suitable for being electrically connected with the chip second electrode of the power chip, and the device third electrode is suitable for being electrically connected with the chip third electrode of the power chip; the second crimping electrode module further comprises a device shell which is arranged in a surrounding mode, and the device second electrode and the device third electrode are arranged at the bottom of the device shell; the device shell is suitable for surrounding and sleeved outside the electrode frame; the lining plate is arranged on one side surface of the first electrode of the device, and the lining plate and the power chip are positioned on the same side surface of the first electrode of the device; the second electrode of the chip and the third electrode of the chip are respectively and electrically connected to different lining plates; one end of the elastic electrode is suitable for being elastically connected with one of the lining plates, and the other end of the elastic electrode is connected with the second electrode of the device or the third electrode of the device; the elastic electrode is suitable for elastically stretching along the direction of the second compression joint electrode module to the first compression joint electrode module; the first crimping electrode module and the second crimping electrode module are suitable for opposite movement by applying external force, and electric conduction with the power chip is realized through elastic deformation of the elastic electrode.
Optionally, the height of the electrode frame is less than or equal to the height of the device housing; when the second crimping electrode module is in crimping connection with the power chip, the surface of one side of the first electrode of the device, which is back to the power chip, is flush with the surface of one side of the second electrode of the device, which is back to the device, or the surface of one side of the third electrode of the device, which is back to the device, of the device shell.
Optionally, the lining plate comprises an insulating layer and conductive layers positioned on two sides of the insulating layer; one of the conductive layers is directly connected with the first electrode of the device, and the other conductive layer is electrically connected with the second electrode of the chip or the third electrode of the chip.
Optionally, the second electrode of the chip is electrically connected with the conductive layer of one lining board through a bonding wire; the conducting layer electrically connected with the second electrode of the chip is positioned at one side of the insulating layer far away from the first electrode of the device; the third electrode of the chip is electrically connected with the conductive layer of the other lining board through a bonding wire; the conducting layer electrically connected with the third electrode of the chip is positioned on one side of the insulating layer far away from the first electrode of the device.
Optionally, the material of the insulating layer comprises a ceramic material.
Optionally, the ceramic material comprises: al (Al) 2 O 3 AlN or Si 3 N 4 One or more combinations thereof.
Optionally, the material of the conductive layer includes a metallic material.
Optionally, the material of the conductive layer includes Cu or Al.
Optionally, the elastic electrode includes a first connection end, a second connection end, and an elastic deformation structure connecting the first connection end and the second connection end; the elastic deformation structure is suitable for millimeter-level deformation under the action of external force and is suitable for completely recovering the shape after the external force is removed. The first connecting end is suitable for abutting against the conductive layer of one lining plate through elastic deformation of the elastic deformation structure, so that electrical contact is realized; the second connecting end is electrically contacted with the second electrode of the device or the third electrode of the device; the first connection end, the second connection end and the elastic deformation structure have conductivity.
Optionally, the elastically deformable structure comprises a disc spring or a spring.
Optionally, the material of the elastic electrode comprises oxygen-free copper.
Optionally, the deformation range of the elastic deformation structure along the direction from the second crimping electrode module to the first crimping electrode module is 1mm-5mm.
Optionally, the difference between the coefficient of thermal expansion of the first electrode of the device and the coefficient of thermal expansion of the power chip is less than 5×10 -6 /K。
Optionally, the material of the first electrode of the device comprises molybdenum, tungsten or their alloys with copper.
Optionally, the material of the electrode frame includes PPA, PPS, PBT.
Optionally, the first crimp electrode module further comprises: the packaging layer is made of insulating materials; the packaging layer is positioned in the space surrounded by the electrode frame and positioned on the surface of the first electrode of the device, which faces the power chip; the packaging layer coats the power chip and part of the elastic electrode.
Optionally, the material of the encapsulation layer comprises silicone gel or epoxy.
Optionally, the power chip includes an IGBT chip or a MOSFET chip; the power chip comprises a silicon-based chip or a silicon carbide chip; the withstand voltage class of the power chip is 6.5kV-20kV.
Optionally, the second electrode of the device is a metal electrode, and the material of the metal electrode comprises oxygen-free copper; the third electrode of the device comprises a PCB board, and the PCB board comprises a polyimide insulating layer and a copper-clad layer on the surface of the polyimide insulating layer.
The invention also provides a power semiconductor device module, which comprises a plurality of power semiconductor device sub-modules, wherein each power semiconductor device sub-module is arranged on a PCB board and is led out from a circuit on the PCB board to be connected in parallel; each power semiconductor device sub-module comprises the power semiconductor device packaging structure provided by the invention.
The invention has the beneficial effects that:
according to the power semiconductor device packaging structure, the first crimping electrode module, the power chip, the second crimping electrode module, the lining plate and the elastic electrode are arranged, so that the power chip is not subjected to crimping pressure of the elastic electrode, and the lining plate is subjected to pressure of the elastic electrode to realize crimping conduction, so that the problem that when the elastic electrode is crimped to the chip, the chip surface element is invalid or damaged due to long-term crimping or overlarge pressure is avoided, and the problem that a high-voltage power chip, particularly a SiC power chip, is difficult to package in a crimping mode is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a power semiconductor device package structure according to an embodiment of the invention;
fig. 2 is a schematic diagram showing a positional relationship of each part of a power semiconductor device package structure according to an embodiment of the present invention during crimping;
fig. 3 is a schematic top view of a power semiconductor device module according to an embodiment of the invention.
Detailed Description
As described above, the package of the high-voltage power chip, especially the SiC chip, if the chip is in a crimping manner, the chip is small, and the elastic electrode is easily crimped directly to the chip during crimping, so that the element on the surface of the chip is invalid or damaged, and the whole device is invalid.
The present invention therefore provides a power semiconductor device package structure comprising: the first crimping electrode module comprises a device first electrode and an electrode frame which is positioned around the device first electrode; the power chip is arranged on the first crimping electrode module; the first electrode of the power chip is electrically connected with the first electrode of the device; the second crimping electrode module is arranged opposite to the first crimping electrode module; the second crimping electrode module comprises a device second electrode and a device third electrode, the device second electrode is suitable for being electrically connected with the chip second electrode of the power chip, and the device third electrode is suitable for being electrically connected with the chip third electrode of the power chip; the second crimping electrode module further comprises a device shell which is arranged in a surrounding mode, and the device second electrode and the device third electrode are arranged at the bottom of the device shell; the device shell is suitable for surrounding and sleeved outside the electrode frame; the lining plate is arranged on one side surface of the first electrode, and the insulating plate and the power chip are positioned on the same side surface of the first electrode; the second electrode of the chip and the third electrode of the chip are respectively and electrically connected to different lining plates; one end of the elastic electrode is suitable for being elastically connected with one of the lining plates, and the other end of the elastic electrode is connected with the second electrode of the device or the third electrode of the device; the elastic electrode is suitable for elastically stretching along the direction of the second compression joint electrode module to the first compression joint electrode module; the first crimping electrode module and the second crimping electrode module are suitable for opposite movement by applying external force, and electric conduction with the power chip is realized through elastic deformation of the elastic electrode. The problem that the high-voltage power chip is difficult to use in compression joint packaging can be solved.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
Referring to fig. 1 and 2, the present embodiment provides a power semiconductor device package structure, including: a step of
The first crimping electrode module comprises a device first electrode 4 and an electrode frame 5 which is arranged around the device first electrode.
The power chip 1, the power chip 1 is set up in the first crimping electrode module, lie in the area surrounded by electrode frame 5, the surface of the first electrode 4 of the device. The chip first electrode 11 of the power chip 1 is electrically connected to the device first electrode 4.
The second crimping electrode module is arranged opposite to the first crimping electrode module. The second crimped electrode module comprises a device second electrode 10 and a device third electrode 9. The device second electrode 10 is adapted to be electrically connected to the chip second electrode 12 of the power chip and the device third electrode 9 is adapted to be electrically connected to the chip third electrode 13 of the power chip. The second crimped electrode module further comprises a circumferentially arranged device housing 8, the device second electrode 10 and the device third electrode 9 being arranged at the bottom of the device housing. The device housing 8 is adapted to be sleeved around the outside of the electrode frame 5.
The lining board 2 is arranged on one side surface of the device first electrode 4, the lining board 2 and the power chip 1 are positioned on the same side surface of the device first electrode 4, and the lining board 2 is surrounded by the electrode frame 5. The chip second electrode 12 and the chip third electrode 13 are electrically connected to different liners 2, respectively.
And an elastic electrode 6, wherein one end of the elastic electrode 6 is suitable for being elastically connected with one of the lining plates 2, and the other end is connected with the device second electrode 10 or the device third electrode 9. The elastic electrode 6 is adapted to elastically stretch and retract in the direction of the second crimp electrode module towards the first crimp electrode module. The first crimping electrode module and the second crimping electrode module are suitable for opposite movement by applying external force, and electric conduction with the power chip is realized through elastic deformation of the elastic electrode.
According to the power semiconductor device packaging structure provided by the embodiment, through the arrangement of the first crimping electrode module, the power chip 1, the second crimping electrode module, the lining plate 2 and the elastic electrode 6, the power chip 1 does not bear the crimping pressure of the elastic electrode 6, and the lining plate 2 bears the pressure of the elastic electrode 6 to realize crimping conduction. Therefore, when the elastic electrode is in compression joint with the chip, the failure or damage of the chip surface element caused by long-term compression joint or overlarge pressure is avoided, and the problem that the high-voltage power chip, especially the SiC power chip, is difficult to package in a compression joint mode is solved.
In the present embodiment, the height of the electrode frame 5 is less than or equal to the height of the device case 8; when the second crimping electrode module is in crimping connection with the power chip 1, the surface of the side, facing away from the power chip 1, of the first electrode 4 of the device is flush with the surface of the side, facing away from the second electrode 10 of the device or the third electrode 9 of the device, of the device shell 8.
The device housing 8 and the electrode frame 5 form a pressure equalization control system. The device housing 8 plays a role of limiting and bearing pressure in the pressure equalization control system as an immovable part. Before crimping the device, the position height of the first electrode 4 of the device is larger than the height of the device shell 8, the height deviation is 1-5 mm, and the maximum deformation of the elastic electrode 6 is smaller. After the device is pressed, the surface of the side of the device first electrode 4 facing away from the power chip 1 is flush with the surface of the side of the device shell 8 facing away from the device second electrode 10 or the device third electrode 9. In this way, even if the external pressure continues to increase, the redundant pressure is borne by the device housing 8, the pressure borne by the device first electrode 4 is relatively balanced, and the internal power chip 1 and the lining board 2 can be effectively protected.
Further, the lining plate 2 comprises an insulating layer and conductive layers on two sides of the insulating layer, that is, the conductive layers on two sides and the insulating layer in the middle form a sandwich structure, and the conductive layers on two sides are separated by the insulating layer. The conductive layers on two sides are respectively and electrically connected to the first electrode 11 and the second electrode 12/the third electrode 13 of the chip, so that the conductive layers are separated by the insulating layer in the middle, and direct electrical connection of the conductive layers is avoided; the conductive layers on both sides are directly connected to the device first electrode 4 and the other is electrically connected to the chip second electrode 12 or the chip third electrode 13.
Specifically, the second electrode 12 of the chip is electrically connected with the conductive layer of one lining plate 2 through the bonding wire 3; the conductive layer electrically connected to the second electrode 12 of the chip is located on the side of the insulating layer remote from the first electrode 4 of the device. The third electrode 13 of the chip is electrically connected with the conductive layer of the other lining board through the bonding wire 3; the conductive layer electrically connected to the third electrode 13 of the chip is located on the side 4 of the insulating layer remote from the first electrode of the device. The first chip electrode 11 may be located on the opposite side of the second chip electrode 12/third chip electrode 13 and electrically connected to the first device electrode 4 directly, or located on the same side of the second chip electrode 12/third chip electrode 13 and electrically connected to the first device electrode 4 through a bonding wire. In the power device packaging structure of the embodiment, the chip first electrode 11 of the power chip 1 is directly interconnected with the device first electrode 4, and heat dissipation can be achieved on the basis of the original side of the device second electrode 10/the device third electrode 9. Direct heat dissipation effect can be realized on one side of the first electrode 4 of the device, double-sided heat dissipation effect can be realized, thermal resistance of the device can be greatly reduced, and heat dissipation capacity of the device can be improved.
Further, the material of the insulating layer includes a ceramic material. The material of the conductive layer includes a metal material.
Specifically, the ceramic material includes: al (Al) 2 O 3 AlN or Si 3 N 4 One or more combinations thereof. Optionally, the material of the conductive layer includes Cu or Al. The thickness of the insulating layer is 0.5mm-3mm; the thickness of the conductive layer is 0.3mm-1mm. Lining plate 2 as high-voltage insulating lining plate and its manufactureThe process includes DBC (direct bond copper), AMB (active metal brazing), IMS (insulated metal liner), and the like. The lining plate 2 can play roles of high-voltage insulation, heat dissipation and electrode interconnection conduction current.
In the present embodiment, the elastic electrode 6 includes a first connection end, a second connection end, and an elastic deformation structure 61 connecting the first connection end and the second connection end. The elastically deformable structure 61 is adapted to deform in the order of millimeters under the application of an external force and to fully recover its shape after the external force is removed. The first connection end (the part above the elastic deformation structure 61 in the elastic electrode 6) is suitable for abutting against the conductive layer of one lining plate 2 through the elastic deformation of the elastic deformation structure 61, so as to realize electrical contact. The second connection terminal (the portion of the elastic electrode 6 below the elastically deformed structure 61) is in electrical contact with the device second electrode 10 or the device third electrode 9. The first connection terminal, the second connection terminal, and the elastically deforming structure 61 have conductivity.
Specifically, the elastically deformable structure includes a disc spring or a spring.
The material of the elastic electrode 6 comprises oxygen-free copper.
The deformation range (i.e., the deformation amount in which deformation can occur) of the elastic deformation structure 61 in the direction from the second crimping electrode module to the first crimping electrode module is 1mm to 5mm.
In the present embodiment, the difference between the thermal expansion coefficient of the first electrode 4 of the device and the thermal expansion coefficient of the power chip is less than 5×10 -6 and/K. This significantly reduces thermal stress due to differences in thermal expansion coefficients as the device undergoes power cycling.
In particular, the material of the first electrode 4 of the device comprises molybdenum, tungsten or their alloys with copper, respectively.
In the present embodiment, the material of the electrode frame 5 includes PPA, PPS, PBT. The electrode frame 5 and the 1 st electrode 4 of the device are interconnected through an adhesion process to form a semi-closed cavity to enclose the power chip 1 and the lining plate 2.
In this embodiment, the first crimp electrode module further includes: the packaging layer 7 is made of insulating materials; the packaging layer 7 is positioned in the space surrounded by the electrode frame 5 and positioned on the surface of the first electrode 4 of the device, which faces the power chip 1; the encapsulation layer 7 encapsulates the power chip and part of the elastic electrode 6. The power chip 1, the lining plate 2 and part of the elastic electrode 6 are coated by the packaging layer 7 formed by insulating materials, so that moisture isolation and physical protection of the power chip are realized.
Specifically, the material of the encapsulation layer includes silicone gel or epoxy resin.
In the present embodiment, the power chip 1 includes an IGBT chip or a MOSFET chip, divided by chip type. The power chip 1 comprises a silicon-based chip or a silicon carbide chip according to the chip material. The withstand voltage class of the power chip 1 is 6.5kV-20kV.
The device second electrode 10 is a metal electrode, the material of which comprises oxygen-free copper. The second electrode 10 of the device leads out the second electrode 12 of the power chip 1 to the outside of the device, so that the device is convenient to test and apply. To improve reliability. The device second electrode 10 also includes a nickel plating layer on the surface of the oxygen-free copper layer. The third electrode 9 of the device comprises a PCB board, the PCB board comprises a polyimide insulating layer and a copper-clad layer on the surface of the polyimide insulating layer, and the control signal of the power chip 1 is led out by the copper-clad layer on the surface.
Example 2
Referring to fig. 3, the present embodiment provides a power semiconductor device module, which includes a plurality of power semiconductor device sub-modules a, each power semiconductor device sub-module a is disposed on a PCB board b, and is led out from a circuit on the PCB board b in parallel; wherein each power semiconductor device sub-module a includes the power semiconductor device package structure provided in embodiment 1 above.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (20)
1. A power semiconductor device package structure, comprising:
the first crimping electrode module comprises a device first electrode and an electrode frame which is positioned around the device first electrode;
the power chip is arranged on the first crimping electrode module; the first electrode of the power chip is electrically connected with the first electrode of the device;
the second crimping electrode module is arranged opposite to the first crimping electrode module; the second crimping electrode module comprises a device second electrode and a device third electrode, the device second electrode is suitable for being electrically connected with the chip second electrode of the power chip, and the device third electrode is suitable for being electrically connected with the chip third electrode of the power chip; the second crimping electrode module further comprises a device shell which is arranged in a surrounding mode, and the second device electrode and the third device electrode are arranged at the bottom of the device shell; the device shell is suitable for surrounding and sleeved outside the electrode frame;
the lining plate is arranged on one side surface of the first electrode of the device, and the lining plate and the power chip are positioned on the same side surface of the first electrode of the device; the second electrode of the chip and the third electrode of the chip are respectively and electrically connected to different lining plates;
one end of the elastic electrode is suitable for being elastically connected with one of the lining plates, and the other end of the elastic electrode is connected with the device second electrode or the device third electrode; the elastic electrode is suitable for elastically stretching and contracting along the direction of the second crimping electrode module to the first crimping electrode module; the first crimping electrode module and the second crimping electrode module are suitable for opposite movement by applying external force, and electric conduction with the power chip is realized by elastic deformation of the elastic electrode;
before the device is crimped, the position height of the first electrode of the device is larger than the height of the device shell and smaller than the maximum deformation of the elastic electrode; after the device is pressed, the surface of the side, facing away from the power chip, of the first electrode of the device is flush with the surface of the side, facing away from the second electrode of the device or the third electrode of the device, of the device shell.
2. The power semiconductor device package of claim 1, wherein the height of the electrode frame is less than or equal to the height of the device housing;
when the second crimping electrode module is in crimping conduction with the power chip, the surface of one side of the first electrode of the device, which is opposite to the power chip, is flush with the surface of one side of the housing of the device, which is opposite to the second electrode of the device or the third electrode of the device.
3. The power semiconductor device package according to claim 1, wherein,
the lining plate comprises an insulating layer and conducting layers positioned on two sides of the insulating layer; one of the conductive layers is directly connected with the first electrode of the device, and the other conductive layer is electrically connected with the second electrode of the chip or the third electrode of the chip.
4. The power semiconductor device package according to claim 3, wherein the second electrode of the chip is electrically connected to the conductive layer of one of the pads through a bonding wire; the conducting layer electrically connected with the second electrode of the chip is positioned on one side of the insulating layer away from the first electrode of the device;
the third electrode of the chip is electrically connected with the conductive layer of the other lining plate through a bonding wire; and the conducting layer electrically connected with the third electrode of the chip is positioned on one side of the insulating layer away from the first electrode of the device.
5. A power semiconductor device package according to claim 3, wherein the material of the insulating layer comprises a ceramic material.
6. The power semiconductor device package according to claim 5, wherein the ceramic material comprises: al (Al) 2 O 3 AlN or Si 3 N 4 One or more combinations thereof.
7. The power semiconductor device package according to claim 3, wherein the material of the conductive layer comprises a metallic material.
8. A power semiconductor device package according to claim 3, wherein the material of the conductive layer comprises Cu or Al.
9. The power semiconductor device package according to claim 3, wherein,
the elastic electrode comprises a first connecting end, a second connecting end and an elastic deformation structure for connecting the first connecting end and the second connecting end; the elastic deformation structure is suitable for millimeter-level deformation under the action of external force and is suitable for completely recovering the shape after the external force is removed;
the first connecting end is suitable for abutting the conductive layer of one lining plate through elastic deformation of the elastic deformation structure to realize electrical contact;
the second connecting end is electrically contacted with the second electrode of the device or the third electrode of the device; the first connection end, the second connection end and the elastic deformation structure have conductivity.
10. The power semiconductor device package according to claim 9, wherein the elastically deformable structure comprises a disc spring or a spring.
11. The power semiconductor device package according to claim 9, wherein the material of the elastic electrode comprises oxygen-free copper.
12. The power semiconductor device package according to claim 9, wherein,
the deformation range of the elastic deformation structure along the direction from the second crimping electrode module to the first crimping electrode module is 1mm-5mm.
13. The power semiconductor device package according to claim 1, wherein,
the difference between the thermal expansion coefficient of the first electrode of the device and the thermal expansion coefficient of the power chip is less than 5×10 -6 /K。
14. The power semiconductor device package of claim 1 wherein the material of the device first electrode comprises molybdenum, tungsten, or alloys thereof with copper.
15. The power semiconductor device package according to claim 1, wherein the material of the electrode frame comprises PPA, PPS, PBT.
16. The power semiconductor device package structure of claim 1, wherein the first crimped electrode module further comprises:
the packaging layer is made of insulating materials; the packaging layer is positioned in the space surrounded by the electrode frame and positioned on the surface of the first electrode of the device, which faces the power chip; the packaging layer coats the power chip and part of the elastic electrode.
17. The power semiconductor device package of claim 16, wherein the material of the encapsulation layer comprises a silicone gel or an epoxy.
18. The power semiconductor device package according to claim 1, wherein the power chip comprises an IGBT chip or a MOSFET chip;
the power chip comprises a silicon-based chip or a silicon carbide chip; the withstand voltage class of the power chip is 6.5kV-20kV.
19. The power semiconductor device package of claim 1, wherein the device second electrode is a metal electrode, the material of the metal electrode comprising oxygen-free copper;
the third electrode of the device comprises a PCB board, and the PCB board comprises a polyimide insulating layer and a copper-clad layer on the surface of the polyimide insulating layer.
20. A power semiconductor device module is characterized in that,
the power semiconductor device comprises a plurality of power semiconductor device submodules, wherein each power semiconductor device submodule is arranged on a PCB, and the power semiconductor device submodules are led out from circuits on the PCB in parallel;
wherein each of the power semiconductor device sub-modules comprises a power semiconductor device package structure as claimed in any one of claims 1-19.
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| DE102005024900B4 (en) * | 2004-06-08 | 2012-08-16 | Fuji Electric Co., Ltd. | power module |
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| CN102768999A (en) * | 2012-07-28 | 2012-11-07 | 江阴市赛英电子有限公司 | High-power integral wafer IGBT (insulated gate bipolar transistor) packaging structure |
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