CN115587058B - Data processing system, method, equipment and medium - Google Patents
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- 238000012545 processing Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 20
- 230000005540 biological transmission Effects 0.000 claims abstract description 60
- 230000004044 response Effects 0.000 claims abstract description 29
- 230000006870 function Effects 0.000 claims abstract description 13
- 238000013500 data storage Methods 0.000 claims description 74
- 238000004458 analytical method Methods 0.000 claims description 6
- 230000005856 abnormality Effects 0.000 claims description 4
- 238000004590 computer program Methods 0.000 claims description 4
- 238000007405 data analysis Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 238000013461 design Methods 0.000 description 9
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- 230000002159 abnormal effect Effects 0.000 description 3
- 241000168254 Siro Species 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000013480 data collection Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
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- 230000011664 signaling Effects 0.000 description 2
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- 238000012938 design process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention belongs to the field of computers, and particularly relates to a data processing system, a data processing method, data processing equipment and a data processing medium. Wherein the system comprises: and the data transmission module is configured to modify the bus protocol according to preset rules and transmit a response instruction or playback data to the bus. The data identification module is configured to receive bus data from the bus, classify the received bus data according to preset rules, and send the classified bus data to the data receiving module; and the data receiving module is configured to save the bus data to a storage medium and/or send the bus data to an upper software system according to the classification of the bus data by the data identifying module. The data processing system provided by the invention shares the command channel and the instruction channel, and encapsulates the application layer protocol on the protocol through the reasonable packaging SRIO protocol to complete the recording and playback functions.
Description
Technical Field
The invention belongs to the field of computers, and particularly relates to a data processing system, a data processing method, data processing equipment and a data processing medium.
Background
In the space flight and aviation detection task, various information needs to be collected and stored for subsequent analysis application, so that the storage system has a vital role in the whole large system.
In the existing storage systems, various instructions are often used as control commands in task execution, and after receiving the instructions, each system performs corresponding tasks. Therefore, most systems have special instruction channels, such as CAN (Controller Area Network ), LVDS (Low-Voltage Differential Signaling, low voltage differential signaling), UART (Universal Asynchronous Receiver/Transmitter ), and CPU interaction. While the data channel is transmitted using other media. Thus, two sets of hardware interfaces are required to complete a completed data acquisition task. The command channel sends commands such as recording and playback, and the data channel completes the recording and playback functions of the data.
However, in the existing design, for example, the CAN, LVDS, UART instruction channel and the data channel are independent, so that the design is convenient, but the volume of the whole system can be increased, and meanwhile, the cost is increased.
Disclosure of Invention
In order to solve the above problems, the present invention provides a data processing system, including:
the data transmission module is configured to modify the bus protocol according to preset rules and transmit a response instruction or playback data to the bus;
the data identification module is configured to receive bus data from the bus, classify the received bus data according to preset rules, and send the classified bus data to the data receiving module;
and the data receiving module is configured to save the bus data to a storage medium and/or send the bus data to an upper software system according to the classification of the bus data by the data identifying module.
In some embodiments of the present invention, the data transmission module includes: the device comprises a data playback module, a playback data sending module and an instruction sending module, wherein:
the data playback module is configured to read playback data from the storage medium according to an instruction of the upper software system and transmit the playback data to the playback data transmission module or generate bus data according to a predetermined rule from the playback data to the playback data transmission module.
In some embodiments of the present invention, a data playback module includes:
the playback data configuration module is configured to receive configuration information of the upper software system and configure a data playback task of the data playback module;
and the playback data reading module is configured to read corresponding playback data from the storage medium based on the data playback task.
In some embodiments of the present invention, the playback data transmission module is configured to:
and modifying the message of the bus according to the preset rule by the playback data, and sending the playback data to the bus through the modified bus message.
In some embodiments of the present invention, the playback data transmission module includes:
the bus data transmission buffer memory is configured to buffer the playback data transmitted by the data playback module;
and the bus data transmission module is configured to generate a bus message according to a preset rule, read data with a corresponding size from the bus data transmission buffer according to the bit width of the bus, and transmit the data to the bus.
In some embodiments of the invention, the instruction sending module is configured to:
And generating a modified bus message based on the control instruction of the upper software system according to a preset rule, and sending a response command configured by the upper software system to the bus through the modified bus message.
In some embodiments of the present invention, the instruction sending module includes:
the sending instruction configuration module is configured to receive a control instruction of the upper software system and configure a sending task of the instruction sending module according to the control instruction of the upper software system;
and the bus instruction sending module is configured to generate a bus message according to a preset rule and send the sending task configured by the sending instruction configuration module to the bus based on the bus message.
In some embodiments of the present invention, the data receiving module includes a data storage module, a data parsing module, and an instruction parsing module, wherein:
the data storage module is configured to store the classified data sent by the data identification module to a storage medium.
In some embodiments of the invention, the data storage module comprises an external source data module, a bus data storage module, a data storage configuration module, wherein:
The data storage configuration module is configured to configure a data storage task of the data storage module according to a control instruction of an upper software system;
the external source data module is configured to receive the data sent by the data analysis module and send the data to the bus data storage module;
the bus data storage module is configured to store data sent by the external source data module into a storage medium.
In some embodiments of the present invention, the data storage module further comprises a data selection module, an internal source data module, wherein:
the internal source data module is configured to generate corresponding internal data according to the storage task and send the internal data to the data selection module;
the data selection module is configured to select corresponding data from the external source data module or the internal data source module based on the data storage task and send the data to the bus data storage module;
the bus data storage module is configured to store the data sent by the data selection module into a storage medium.
In some embodiments of the invention, the data parsing module is configured to:
And receiving bus data classified as data by the data identification module, analyzing the bus data, and transmitting the analyzed data to the data storage module.
In some embodiments of the present invention, the data parsing module includes a bus data receiving module:
the bus data receiving module is configured to receive the bus data sent by the data identifying module, analyze the bus data according to a preset rule based on a bus protocol, and send the analyzed data to the data storage module.
In some embodiments of the present invention, the data parsing module further includes:
the bus data receiving buffer is configured to buffer the analyzed bus data sent by the data bus data receiving module;
the bus data receiving module is further configured to send the parsed data to the bus data receiving buffer based on the sizes of the bus bit width and the internal data bit width, and send the corresponding data read from the bus data receiving buffer to the data storage module in response to the internal bit width meeting requirement.
In some embodiments of the invention, the instruction parsing module is configured to:
And receiving bus data classified as instructions by the data identification module, analyzing the bus data, and sending the analyzed instructions to an upper software system.
In some embodiments of the present invention, the instruction parsing module includes:
the instruction data receiving module is configured to receive the bus data sent by the data identification module, analyze the corresponding bus instruction from the bus data and send the bus instruction to an upper software system.
In some embodiments of the invention, the instruction parsing module further comprises:
the instruction receiving and configuring module is configured to respond to the instruction data receiving module to analyze the bus instruction, initiate an interrupt to an upper software system and receive configuration information of the upper software system to configure an instruction analysis task of the instruction analysis module through the configuration information.
In some embodiments of the invention, the system further comprises a control module configured to:
receiving bus data of the data receiving module and storing the bus data into a storage medium, or sending a bus data response result to an upper software system;
And transmitting the control instruction of the upper software system to the data transmitting module and/or transmitting the playback data in the storage medium to the data transmitting module according to the data reading request of the data transmitting module.
In some embodiments of the present invention, a link reconfiguration module is further included, the link reconfiguration module configured to:
communicating the sub-modules with the same function in a transmission loop formed by the data sending module, the data receiving module and the data identifying module through a selector;
responsive to an abnormality in each of the plurality of transmission loops, a new transmission loop is reconfigured across the transmission loops by the selector.
Another aspect of the present invention also proposes a data processing method, including:
and modifying the bus protocol according to preset rules and sending response instructions or playback data to the bus.
Receiving bus data from a bus, classifying the received bus data according to preset rules, and transmitting the classified bus data to a data receiving module;
and storing the bus data to a storage medium and/or transmitting the bus data to an upper software system according to the classification of the bus data by the data receiving module.
Yet another aspect of the present invention is directed to a computer device comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any of the above embodiments.
Yet another aspect of the invention also proposes a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.
The data processing system provided by the invention shares the command channel and the instruction channel, and encapsulates the application layer protocol on the protocol through the reasonable packaging SRIO protocol to complete the recording and playback functions. The chip area occupied by two independent ports is required to be set up in the chip design process, and the chip power consumption is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a data processing system according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a data processing method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a computer device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer readable storage medium according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a data processing system according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a portion of a data processing system according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a portion of a data processing system according to an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating a portion of a data processing system according to an embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a portion of a data processing system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
The invention aims to solve the problem of large chip area caused by the design of data collection and playback equipment block instructions and data separation in the existing aerospace equipment. In the currently used data collection and playback system, the existing data bus is used as a data transmission interface, the general implementation mode leads to the need of designing an instruction interface module and a data interface module when a chip is designed, and the transceiving of the two modules needs to design a plurality of circuits, so that the area of the chip is increased, the area of the chip is wasted, and meanwhile, the circuit design of more modules brings challenges to the power consumption and heat dissipation of the chip.
As shown in fig. 1, to solve the above-mentioned problems, the present invention proposes a data processing system, including:
a data transmission module 3, wherein the data transmission module 3 is configured to modify a bus protocol according to a preset rule and transmit a response instruction or playback data to the bus;
The data identification module 1 is configured to receive bus data from a bus, classify the received bus data according to preset rules, and send the classified bus data to the data receiving module 2;
the data receiving module 2 is configured to save the bus data to a storage medium and/or send the bus data to an upper software system according to the classification of the bus data by the data identifying module 1.
In the embodiment of the present invention, the data transmission module 3 and the data identification module 1 are set according to the bus used by the system, and in the embodiment of the present method, an SRIO (Serial Rapid Intput Output high-speed serial input output) bus is used.
In this embodiment, the data sending module 3 will modify the pre-determined bits of the header of the message according to the type of data sent to the SRIO bus. Specifically, if a response instruction is sent to the SIRO bus (sent to other modules through the SRIO bus), the format of the data packet of the response instruction is:
{srctid[63:56]，FTYPE[55:52]，TTYPE[51:48]，1，prio[46:45]，CRF[44]，SIZE[43:36]，36’d0}+CMD(256B)；
wherein, the liquid crystal display device comprises a liquid crystal display device, { srctid. &.... } denotes the header of the SRIO message, the following CMD indicates a 256 byte response command, the header of the SRIO message is 64 bits in total, the invention takes the 47 th bit as the identification bit for identifying whether the message is an instruction message or a data message, wherein the 47 th bit of the instruction message is 1, namely the value between TTYPE [51:48] and prio [46:45] is 1
The format of the data packet for transmitting data is:
{ srctid [63:56], FTYPE [55:52], TTYPE [51:48],0, prio [46:45], CRF [44], SIZE [43:36],36' d0} +DATA (256B); where { srctid.. Degree. } denotes a 64-bit header, the 47 th position of the message is 0, i.e. the value between TTYPE [51:48] and prio [46:45] is 0, followed by 256 bytes of DATA, i.e. DATA.
Therefore, the data sending module 3 modifies the 47 th bit of the report Wen Toubu as the identifier according to whether the content to be sent to the SRIO bus is data or instruction.
Similarly, the data identifying module 1 determines whether to be data or instruction, that is, classifies the message data, according to the 47 th bit value of the 64 th bit data of the header of the message data received from the SRIO bus, and transmits the classified data to the data receiving module 2.
The data receiving module 2 directly processes the classified data, if the classified data is an instruction, the instruction is sent to an upper software system, and the upper software system refers to a program system operated by a processor in a chip where the system of the present invention is located. If the data is the data, the data is stored in a memory or a disk.
In some embodiments of the present invention, the data transmission module 3 includes: a data playback module 33, a playback data transmission module 31, an instruction transmission module 32, wherein:
The data playback module 33 is configured to read playback data from a storage medium according to an instruction of an upper software system and transmit the playback data to the playback data transmission module 31 or generate bus data according to a predetermined rule from the playback data to the playback data transmission module 31.
As shown in fig. 6, the data transmission module 3 includes: the data playback module 33, the data playback module 33 is configured to move out from the playback data DDR according to a control instruction of the upper software system, and complete the grouping of the SRIOs. And transmits the data completed with the SRIO packet to the playback data transmitting module 31.
In some embodiments of the present invention, the data playback module 33 includes:
a playback data configuration module 331, where the playback data configuration module 331 is configured to receive configuration information of an upper software system and configure a data playback task of the data playback module 33;
and a playback data reading module 332, wherein the playback data reading module 332 is configured to read corresponding playback data from the storage medium based on the data playback task.
In this embodiment, as shown in fig. 7, the data playback module 33 further includes a playback data configuration module 331 and a playback data reading module 332, where the playback data configuration module 331 configures playback related registers for the data playback module 33 according to a configuration instruction of an upper software system, including playback start/stop, DMA transfer length, transfer times, reporting interrupt length, clearing interrupt, and the like, that is, configures a data playback task of the data playback module 33.
Further, in some embodiments of the present invention, the playback data module actually integrates the DMA module for reading the corresponding data from the memory, so after the playback data configuration module 331 configures the playback data task, the playback data reading module 332 starts the DMA move according to the start command of the playback task, moves the data out of the DDR, and reports an interrupt to the upper software layer whenever the configured data length is moved out.
And transmitting the message header and the message data content to the SRIO packet logic to complete the SRIO packet, namely forming a message which can be used on an SRIO bus after generating the message header and the message data content. And transmits the packetized data to the playback data transmission module 31.
In some embodiments of the present invention, the playback data transmission module 31 is configured to:
and modifying the message of the bus according to the preset rule by the playback data, and sending the playback data to the bus through the modified bus message.
In some embodiments of the present invention, the playback data transmitting module 31 includes:
a bus data transmission buffer 312, where the bus data transmission buffer 312 is configured to buffer playback data transmitted by the data playback module;
the bus data sending module 311 is configured to generate a bus message according to a preset rule, and read data with a corresponding size from the bus data sending buffer 312 according to a bit width of the bus, and send the data to the bus.
In this embodiment, the playback DATA sending module 31 is used to send the DATA sent by the DATA playback module to the SRIO bus, where the DATA playback module implements SRIO packet of the DATA content, and the playback DATA sending module 31 generates a packet header, and sends the 47 th position to be 0, and sends the SRIO packet of the DATA content to the SIRO bus as DATA after the packet header.
Further, as shown in fig. 8, the playback data sending module 31 further includes a bus data sending buffer 312, and the bus data sending buffer 312 is used for receiving the SRIO packet of the data content sent by the data playback module 33. And realizes the cross-clock domain processing of the data, and the data is read by the bus data sending module 311 and then sent to the SRIO bus.
In some embodiments of the present invention, the bus data sending module 311 may also implement SRIO packet for playback data, generate a 64-bit header, and set the 47 th bit to 0. And then reads the corresponding data part from the bus data transmission buffer 312 to complete 256-bit to 64-bit width conversion and transmit the data part to the SRIO bus.
In some embodiments of the present invention, the instruction sending module 32 is configured to:
and generating a modified bus message based on the control instruction of the upper software system according to a preset rule, and sending a response command configured by the upper software system to the bus through the modified bus message.
In this embodiment, the control instruction is an internal control instruction of the upper software system control instruction sending module 32, and the response command refers to a command that the upper software system replies to other modules on the SRIO bus through the SRIO bus, for example, after the execution of one recording flow is finished, the recording instruction at the opposite end of the SRIO bus is replied to be successfully executed, and the data is already stored in the SSD; such as playback instructions, replying to the data requested by the peer has been replied to the peer, successful execution of the instructions, and so on.
In some embodiments of the present invention, the instruction sending module 32 includes:
a transmission instruction configuration module 322, where the transmission instruction configuration module 322 is configured to receive a control instruction of the upper software system, and configure a transmission task of the instruction transmission module 32 according to the control instruction of the upper software system;
and the bus instruction sending module 321 is configured to generate a bus message according to a preset rule, and send the sending task configured by the sending instruction configuration module 322 to the bus based on the bus message.
As shown in fig. 9, in this embodiment, the sending task refers to a process of completing sending an SRIO instruction in a custom format onto the SRIO bus at a time. The instruction issue module 32 mainly includes an issue instruction configuration module 322 and a bus instruction issue module 321.
The send instruction configuration module 322 receives configuration data of the upper software system to configure the relevant registers of the instruction send module 32 to create send tasks including data write enable, command content to reply, clear interrupts, command send start, etc.
The bus command sending module 321 includes a FIFO, which is used for receiving the response content issued by the upper software system. Firstly, buffering, under the control of a command sending mark, reading out response content from the FIFO by hardware, forming an SRIO command packet format (report Wen Toubu, 47 th position 0), and after the completion of sending, reporting an interrupt to inform an upper software system that the response is sent to an opposite terminal through SRIO.
In some embodiments of the present invention, the data receiving module 2 includes a data storage module 23, a data parsing module 21, an instruction parsing module 22, wherein:
the data storage module 23 is configured to save the classification data transmitted by the data identification module 1 to a storage medium.
As shown in fig. 10, the data receiving module 2 includes a data storage module 23, a data analysis module 21, and an instruction analysis module 22, wherein the data storage module 23 stores the data classified by the data recognition module 1 into a memory inside the system.
In some embodiments of the present invention, the data storage module 23 comprises an external source data module, a bus data storage module 232, a data storage configuration module 233, wherein:
the data storage configuration module 233 is configured to configure data storage tasks of the data storage module 23 according to control instructions of an upper software system;
the external source data module is configured to receive the data sent by the data parsing module 21 and send the data to the bus data storage module 232;
the bus data storage module 232 is configured to save the data sent by the external source data module to a storage medium.
Further, as shown in fig. 11, in the present embodiment, the data storage module 23 includes an external source data module 231, a bus data storage module 232, a data storage configuration module 233,
the bus data storage module 232 is integrated with DMA control logic, and can realize data access to the storage medium. Under the configuration of the data storage configuration module 233, the DMA control logic initiates a DMA request and if the external data source module has data input, the data of the external source data module 231 is sent to the DDR.
Further, the DMA transfer length, the transfer frequency, the length of the reporting interrupt, and the like of the DMA control logic in the bus data storage module 232 are flexibly configurable, so that the upper software system can be conveniently used, and after the corresponding data is written into the DDR, the data storage configuration module 233 sends the interrupt to the upper software system, so that the upper software system can know the data amount cached in the DRR and which address is cached at the moment. And writing corresponding data from the DDR to the SSD based on the address.
The data storage configuration module 233 receives configuration data of the upper software system, and configures data storage tasks of the data storage module 23, including types of internal data sources (fixed number, random number, cumulative number), data bit widths, internal data source start generation, and the like, and configures DMA control related parameters such as DMA start move, DMA move length, move address, move times, length of reporting interrupt, and registers for clearing interrupt.
The external source DATA module is configured to receive the parsed bus DATA (i.e. DATA portion) from the DATA parsing module 21, and send the corresponding bus DATA to the bus storage module. In some embodiments of the present invention, the data storage module 23 further comprises a data selection module 235, an internal source data module 234, wherein:
the internal source data module 234 is configured to generate corresponding internal data according to the storage task, and send the internal data to the data selection module 235;
the data selecting module 235 is configured to select corresponding data from the external source data module or the internal source data module based on the data storage task to send to the bus data storage module 232;
the bus data storage module 232 is configured to save the data sent by the data selection module 235 to a storage medium.
In this embodiment, as shown in fig. 12, the data storage module 23 further includes an internal source data module 234 and a data selection module 235. Further, the data storage configuration module 233 also configures to select whether an internal data source or an external data source when configuring the storage task.
The data selection module 235 sends the data of the external source data module to the bus data storage module 232 if the external source data is selected by the configuration, and sends the data of the internal source data module to the bus data storage module 232 if the internal source data is selected.
In some embodiments of the present invention, at the beginning of system startup, the upper software system may configure the selected internal data source module of the data selection module 235 through the data storage configuration module 233, where the internal data source module generates internal test data according to a predetermined manner and sends the internal test data to the bus data storage module 232, the bus data storage module 232 writes the internal test data to the memory or the disk, and then the uploading software system may compare the internal test data according to the predetermined manner, so as to determine whether the function of the data storage module 23 is normal.
Further, in some embodiments of the present invention, the upper software system may perform periodic functional verification periodically via the data selection module 235 and the internal source data module 234.
In some embodiments of the present invention, the data parsing module 21 is configured to:
the received data identification module 1 classifies bus data as data, analyzes the bus data, and transmits the analyzed data to the data storage module 23.
In some embodiments of the present invention, the data parsing module 21 includes a bus data receiving module 211:
the bus data receiving module 211 is configured to receive the bus data sent by the data identifying module 1, parse the bus data according to a preset rule based on a bus protocol, and send the parsed data to the data storing module 23.
In some embodiments of the present invention, the data parsing module 21 further includes:
a bus data receiving buffer 212, where the bus data receiving buffer 212 is configured to buffer the parsed bus data sent by the data bus data receiving module 211;
the bus data receiving module 211 is further configured to send the parsed data to the bus data receiving buffer 212 based on the size of the bus bit width and the internal data bit width, and read the corresponding data from the bus data receiving buffer 212 to the data storage module 23 in response to meeting the internal bit width requirement.
As shown in fig. 13, in the present embodiment, the DATA parsing module 21 is configured to receive bus DATA classified as DATA from the DATA identifying module 1, and send the DATA portion of the bus message to the DATA storing module 23 according to the 47 th bit value of the header of the message.
The DATA parsing module 21 mainly includes a bus DATA receiving buffer 212 and the bus DATA receiving module 211, where the bus DATA receiving buffer 212 is used to buffer the DATA portion processed by the bus DATA receiving module 211, and the SRIO bus is 64 bits, and the internal bus is 256 bits, so that the DATA needs to be buffered to 256 bits in the bus DATA receiving buffer 212 and then sent to the DATA storage module 23.
In some embodiments of the present invention, instruction parsing module 22 is configured to:
the method comprises the steps of receiving bus data classified as instructions by a data identification module 1, analyzing the bus data, and sending the analyzed instructions to an upper software system.
In some embodiments of the present invention, instruction parsing module 22 includes:
the instruction data receiving module 221, where the instruction data receiving module 221 is configured to receive the bus data sent by the data identifying module 1, parse a corresponding bus instruction from the bus data, and send the bus instruction to an upper software system.
In some embodiments of the present invention, instruction parsing module 22 further includes:
the instruction receiving and configuring module 222 is configured to initiate an interrupt to the upper software system and receive configuration information of the upper software system to configure an instruction parsing task of the instruction parsing module 22 according to the configuration information in response to the instruction data receiving module 221 parsing the bus instruction.
In this embodiment. The instruction parsing module 22 is configured to process the bus data with bit 47 being 1 of the report Wen Toubu received from the SRIO bus, and send the command part in the bus data to the upper software system.
As shown in fig. 14, the function of the instruction parsing module 22 is completed by an internal instruction data receiving module 221 and an instruction receiving configuration module 222, where the instruction data receiving module 221 is configured to store instruction data (CMD) except for a packet header in an internal FIFO, and report an interrupt to the upper software system after the completion of the reception, and an instruction has been received. At this time, the upper software system responds by reading the instruction content from the FIFO and then judging the type of the command as a record or playback or telemetry command according to the content of 256B read, wherein the commands have own data frame format. (e.g., record instruction, record file number, length of data record, record to that SSD, etc.) information. E.g., playback instruction, record file number, length of data played back, etc. telemetry instruction, query the currently recorded file number, status of hard disk, residual capacity, etc.).
Instruction receive configuration module 222 parses the associated register configuration for instructions, such as clearing interrupts, reading FIFO enables, and receiving data registers. When the upper software system recognizes a record or playback command, it is necessary to control the associated record or playback flow.
In some embodiments of the invention, the system further comprises a control module configured to:
receiving bus data of the data receiving module 2 and storing the bus data in a storage medium, or sending a bus data response result to an upper software system;
the control instruction of the upper software system is transmitted to the data transmission module 3 and/or playback data in the storage medium is transmitted to the data transmission module 3 according to a data read request of the data transmission module 3.
As shown in fig. 5, the present embodiment further includes a control module 4, where the control module 4 is a control module for communicating the data identification module 1, the data reception module 2, and the data transmission module 3 to the upper software system. The bus data received by the data receiving module 2 is firstly stored into the memory through the control module, and the interrupt generated by each module is sent to the upper software system.
The disk management module 5 is integrated with an hsata_controller for realizing a controller for the SSD memory. The controller is used for realizing the reading and writing of the SSD, and a DMA module is contained in the controller and is used for realizing the data movement of the data in the SSD disk and the DDR. Axi_interconnect1 completes the interconnection of 4 SSD controllers to DDR bus (AXI 4).
In some embodiments of the present invention, a link reconfiguration module is further included, the link reconfiguration module configured to:
communicating the plurality of sub-modules with the same function in a transmission loop formed by the data sending module 3, the data receiving module 2 and the data identifying module 1 through a selector;
responsive to an abnormality in each of the plurality of transmission loops, a new transmission loop is reconfigured across the transmission loops by the selector.
In some embodiments of the present invention, the transmission loop refers to a loop sent by an SRIO bus receiver composed of a data sending module 3, a data receiving module 2, and a data identifying module 1 in a set of data recording system provided by the present invention. As described above, the data transmission module 3 and the data reception module 2 and the data identification module 1 have a plurality of functional modules.
When the present invention is applied, a redundant design is generally performed, that is, an interface having two or more sets of data transmission modules 3, data reception modules 2, and data identification modules 1 is developed. Therefore, in the case of a redundancy design, the present invention designs a link reconfiguration module, where there is a plurality of selectors, and there is a selector between each selector design and the module, for example, between the data identification module 1 and the data receiving module 2, and by default, in the same loop, the data sent from the data identification module 1 to the data receiving module 2 will be normally sent to the data receiving module 2. If necessary, the data of the data identification module 1 in one loop can be gated to the data receiving module 2 of the other loop through a selector by the link reconstruction module. The method can effectively avoid the reconstruction of the data link when the function of part of the modules is abnormal on the spacecraft due to some unknown reasons, and the modules which can normally run on different loops form a new transmission loop.
It should be noted that, the connection structure of the selector in the link reconfiguration module is too complex and is not shown in the figure, in the embodiment of the present invention, the inputs and outputs of the submodules with the same test speaking function are respectively connected by a plurality of selectors, and when an abnormality occurs, the selector controlling the abnormal module point avoids the abnormal module to form a new transmission link.
In some embodiments of the present invention, referring to fig. 5 to 14, the workflow of the proposed data processing system of the present invention includes:
1. command receiving flow:
the data transmitted by the SRIO interface is firstly distinguished by the data identification module 1 according to Bit [47] in the SRIO packet format, and when Bit [47] is 1, the data is transmitted to a command and then received by the command data receiving module 221. In this module, instruction data except for the packet header is stored in its internal FIFO, and after the reception is completed, an interrupt is reported to the upper software system that an instruction has been received. At this time, the upper software system responds by reading the instruction content from the FIFO and then judging the type of the command as a record or playback or telemetry command according to the content of 256B read, wherein the commands have own data frame format. (e.g., record instruction, record file number, length of data record, record to that SSD, etc.) information. E.g., playback instruction, record file number, length of data played back, etc. telemetry instruction, query the currently recorded file number, status of hard disk, residual capacity, etc.).
Instruction receive configuration module 222 configures registers associated with command receipt, such as clear interrupts, read FIFO enable, and receive data registers. When the upper software system recognizes a record or playback command, it is necessary to control the associated record or playback flow.
2. Response flow of command:
the command response is used for the upper software system to reply the execution result of a certain event, for example, after the execution of a recording flow is finished, the reply to the opposite end is successful in the execution of the note record command, and the data are stored in the SSD; such as playback instructions, replying to the data requested by the peer has been replied to the peer, successful execution of the instructions, and so on.
Mainly comprises a bus instruction sending module 321 and a sending instruction configuration module 322. Wherein the send instruction configuration module 322 upper software system configures the associated registers including data write enable, command content to reply, clear interrupt, command to start, etc.
The bus command sending module 321 includes a FIFO, which is used for receiving the response content issued by the upper software system. Firstly, caching, reading out response content from the FIFO under the control of a command sending mark, forming an SRIO command packet format, and reporting an interrupt after the sending is completed to inform an upper software system that the response is sent to an opposite terminal.
3. And (3) recording data:
after the upper software system receives the recording instruction, the upper software system controls the hardware logic of the data processing system to execute the recording flow.
The data identification module 1 is distinguished according to Bit [47] in the SRIO packet format, and when Bit [47] is 0, the data identification module indicates that valid data is transmitted. Firstly, the data is converted into bit width through the bus data receiving module 211, and is transmitted to the bus data receiving buffer 212 to complete the process of crossing clock domains, namely from the SRIO clock domain to the DDR clock domain.
And then to a data storage module 23, which is the core module for data logging control. Configuration module data store configuration module 233, external source data module 231, internal source data module 234, bus data store module 232 containing data record related registers.
Wherein the bus data storage module 232 integrates DMA control logic and DMA IP.
The data storage configuration module 233 configures the type (fixed number, random number, cumulative number) of the internal data source, the data bit width, the internal data source start generation, and the like; configuring to select an internal data source or an external data source; and configuring the related parameters of DMA control, such as DMA start moving, DMA moving length, moving address, moving times, length of reporting interrupt, clearing interrupt and other registers.
The internal source data module 234 is mainly used for generating an internal data source, and is used for the recording function of the self-test system when no external data source exists.
The external source data module 231 receives data of the bus data reception buffer 212;
the data selection module 235 selects an external data source or an internal data source under control of a selection signal;
under the control of the DMA start moving signal, the DMA control logic initiates a DMA request, and if data exists on the SRIO bus, the data arrives at the DMA data port through the bus data receiving buffer 212 module to move the data. In the DMA control logic, the DMA transfer length, the transfer times, the length of the reporting interrupt and the like are flexibly matched, and the upper software system can be conveniently used. When the DMA receives the data quantity of the length of the reporting interrupt, the data is transmitted to the DDR, the reporting interrupt is sent to the upper software system, and the upper software system can know the data quantity cached in the DRR and which address to cache. At this time, the hsata_controller at the back end can be started to complete the data moving from the DDR to the SSD. The data transmission from the front end continues during this process and is also continuously transmitted to the DDR, with the data being continuously stored in the SSD in this loop.
At this time, if the stop record is received, the DMA transfer is stopped.
In the process, the upper software system counts the related information of the file records, and maintains a table for inquiring during playback.
4. Playback flow of data:
when receiving the playback instruction, the upper software system starts the playback flow and configures the related registers.
Firstly, according to the content of a command, an upper software system searches a statistical file record table, starts a DMA (direct memory access) in an Hssata_controller to read data from a corresponding address in an SSD to the DDR. The playback flow is then started.
The core module for playback is a data playback module 33 whose main functions are to move data out of the DDR and complete the packetizing of the SRIO. The playback data reading module 332, the SRIO group packet, and the DMA IP, which are integrated with the DMA control logic, are included in the playback data configuration module 331. The playback data configuration module 331 is configured for a playback related register, and mainly includes playback start/stop, DMA transfer length, transfer times, reporting interrupt length, interrupt clearing, and the like;
the DMA control logic part starts the moving of the DMA according to the playback start command, moves the data out of the DDR, and reports the interrupt to the upper software system every time the configured data length is moved out. And transmitting the packet to the SRIO packet logic to complete the packet of the SRIO. And the data is processed across clock domains through the bus data receiving buffer 212 module, and is replayed to the opposite end through the SRIO channel through bit width conversion (replay data sending module 31).
In this process, the upper software system needs to count the amount of data to be moved, and when the data is moved to a required data length, the DMA is stopped.
As shown in fig. 2, another aspect of the present invention further proposes a data processing method, including:
and S1, modifying the bus protocol according to a preset rule and sending a response instruction or playback data to the bus.
S2, receiving bus data from a bus, classifying the received bus data according to preset rules, and sending the classified bus data to a data receiving module;
and step S3, storing the bus data to a storage medium and/or transmitting the bus data to an upper software system according to the classification of the bus data by the data receiving module.
As shown in fig. 3, a further aspect of the present invention further proposes a computer device, including:
at least one processor 2001; and
a memory 2002, said memory 2002 storing computer instructions 2003 executable on said processor 2001, said instructions 2003 implementing the steps of the method of any of the above embodiments when executed by said processor 2001.
As shown in fig. 4, a further aspect of the present invention further proposes a computer readable storage medium 401, said computer readable storage medium 401 storing a computer program 402, said computer program 402 implementing the steps of the method according to any of the above embodiments when being executed by a processor.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (21)
1. A data processing system, comprising:
the data transmission module is configured to modify the bus protocol according to preset rules and transmit a response instruction or playback data to the bus;
the data identification module is configured to receive bus data from the bus, classify the received bus data according to preset rules, and send the classified bus data to the data receiving module;
And the data receiving module is configured to save the bus data to the storage medium and send the bus data classified as the instruction to the upper software system according to the classification of the bus data by the data identification module.
2. The system of claim 1, wherein the data transmission module comprises: the device comprises a data playback module, a playback data sending module and an instruction sending module, wherein:
the data playback module is configured to read playback data from the storage medium according to an instruction of the upper software system and transmit the playback data to the playback data transmission module or generate bus data according to a predetermined rule from the playback data to the playback data transmission module.
3. The system of claim 2, wherein the data playback module comprises:
the playback data configuration module is configured to receive configuration information of the upper software system and configure a data playback task of the data playback module;
and the playback data reading module is configured to read corresponding playback data from the storage medium based on the data playback task.
4. The system of claim 2, wherein the playback data transmission module is configured to:
and modifying the message of the bus according to the preset rule by the playback data, and sending the playback data to the bus through the modified bus message.
5. The system of claim 4, wherein the playback data transmission module comprises:
the bus data transmission buffer memory is configured to buffer the playback data transmitted by the data playback module;
and the bus data transmission module is configured to generate a bus message according to a preset rule, read data with a corresponding size from the bus data transmission buffer according to the bit width of the bus, and transmit the data to the bus.
6. The system of claim 2, wherein the instruction sending module is configured to:
and generating a modified bus message based on the control instruction of the upper software system according to a preset rule, and sending a response command configured by the upper software system to the bus through the modified bus message.
7. The system of claim 6, wherein the instruction sending module comprises:
The sending instruction configuration module is configured to receive a control instruction of the upper software system and configure a sending task of the instruction sending module according to the control instruction of the upper software system;
and the bus instruction sending module is configured to generate a bus message according to a preset rule and send the sending task configured by the sending instruction configuration module to the bus based on the bus message.
8. The system of claim 1, wherein the data receiving module comprises a data storage module, a data parsing module, an instruction parsing module, wherein:
the data storage module is configured to store the classified data sent by the data identification module to a storage medium.
9. The system of claim 8, wherein the data storage module comprises an external source data module, a bus data storage module, a data storage configuration module, wherein:
the data storage configuration module is configured to configure a data storage task of the data storage module according to a control instruction of an upper software system;
the external source data module is configured to receive the data sent by the data analysis module and send the data to the bus data storage module;
The bus data storage module is configured to store data sent by the external source data module into a storage medium.
10. The system of claim 9, wherein the data storage module further comprises a data selection module, an internal source data module, wherein:
the internal source data module is configured to generate corresponding internal data according to the storage task and send the internal data to the data selection module;
the data selection module is configured to select corresponding data from the external source data module or the internal data source module based on the data storage task and send the data to the bus data storage module;
the bus data storage module is configured to store the data sent by the data selection module into a storage medium.
11. The system of claim 8, wherein the data parsing module is configured to:
and receiving bus data classified as data by the data identification module, analyzing the bus data, and transmitting the analyzed data to the data storage module.
12. The system of claim 11, wherein the data parsing module comprises a bus data receiving module:
The bus data receiving module is configured to receive the bus data sent by the data identifying module, analyze the bus data according to a preset rule based on a bus protocol, and send the analyzed data to the data storage module.
13. The system of claim 12, wherein the data parsing module further comprises:
the bus data receiving buffer is configured to buffer the analyzed bus data sent by the bus data receiving module;
the bus data receiving module is further configured to send the parsed data to the bus data receiving buffer based on the sizes of the bus bit width and the internal data bit width, and send the corresponding data read from the bus data receiving buffer to the data storage module in response to the internal bit width meeting requirement.
14. The system of claim 8, wherein the instruction parsing module is configured to:
and receiving bus data classified as instructions by the data identification module, analyzing the bus data, and sending the analyzed instructions to an upper software system.
15. The system of claim 14, wherein the instruction parsing module comprises:
The instruction data receiving module is configured to receive the bus data sent by the data identification module, analyze the corresponding bus instruction from the bus data and send the bus instruction to an upper software system.
16. The system of claim 15, wherein the instruction parsing module further comprises:
the instruction receiving and configuring module is configured to respond to the instruction data receiving module to analyze the bus instruction, initiate an interrupt to an upper software system and receive configuration information of the upper software system to configure an instruction analysis task of the instruction analysis module through the configuration information.
17. The system of claim 1, further comprising a control module configured to:
receiving bus data of the data receiving module and storing the bus data into a storage medium, or sending a bus data response result to an upper software system;
and transmitting the control instruction of the upper software system to the data transmitting module and/or transmitting the playback data in the storage medium to the data transmitting module according to the data reading request of the data transmitting module.
18. The system of claim 1, further comprising a link reconfiguration module configured to:
communicating a plurality of submodules with the same function in a transmission loop formed by the data sending module, the data receiving module and the data identifying module through a selector;
responsive to an abnormality in each of the plurality of transmission loops, a new transmission loop is reconfigured across the transmission loops by the selector.
19. A method of data processing, comprising:
modifying the bus protocol according to a preset rule and sending a response instruction or playback data to the bus;
receiving bus data from a bus, classifying the received bus data according to preset rules, and transmitting the classified bus data to a data receiving module;
and the data receiving module stores the bus data into a storage medium according to the data identification module and transmits the bus data classified as instructions to an upper software system according to the classification of the bus data by the data identification module.
20. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of claim 19.
21. A computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of claim 19.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7594002B1 (en) * | 2003-02-14 | 2009-09-22 | Istor Networks, Inc. | Hardware-accelerated high availability integrated networked storage system |
| CN105429833B (en) * | 2015-10-21 | 2019-01-04 | 中国汽车工程研究院股份有限公司 | Method and its system based on the storage of CAN bus data |
| CN106201670B (en) * | 2016-07-20 | 2019-08-02 | 北京航天发射技术研究所 | A kind of CAN bus data processing method based on Labview |
| CN110321300A (en) * | 2019-05-20 | 2019-10-11 | 中国船舶重工集团公司第七一五研究所 | A kind of implementation method of signal processing data high-speed record and playback module |
| CN209823749U (en) * | 2019-07-02 | 2019-12-20 | 深圳市综科智控科技开发有限公司 | Interface multiplexing device capable of simultaneously realizing wired communication and wireless communication |
| CN110798476A (en) * | 2019-11-06 | 2020-02-14 | 上海电气集团股份有限公司 | CAN bus data processing method and system of fuel cell system |
| CN114297124B (en) * | 2021-12-29 | 2024-03-29 | 苏州长风航空电子有限公司 | Communication system of SRIO high-speed bus based on FPGA |
| CN114356419B (en) * | 2022-03-14 | 2022-06-07 | 苏州浪潮智能科技有限公司 | Universal interface register system and rapid generation method |
| CN115189981B (en) * | 2022-06-30 | 2023-12-01 | 东风汽车集团股份有限公司 | Lin bus interface based on master-slave reusability |
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