CN104714904B

CN104714904B - Using the RapidIO controllers and its control method of window mapping mechanism

Info

Publication number: CN104714904B
Application number: CN201310688470.7A
Authority: CN
Inventors: 段小虎; 李鹏; 韩强; 邓豹; 解文涛; 魏巍; 赵小冬; 邹晨; 袁迹; 周啸; 代明清
Original assignee: AVIC No 631 Research Institute
Current assignee: AVIC No 631 Research Institute
Priority date: 2013-12-14
Filing date: 2013-12-14
Publication date: 2018-04-20
Anticipated expiration: 2033-12-14
Also published as: CN104714904A

Abstract

The present invention proposes the RapidIO controllers using window mapping mechanism, including RapidIO IP Core, the parallel local bus interacted with ppu, address decoding module, expanded configuration space, initiator's request bag generation module, initiator's response Packet analyzing module and the logging modle for initiating bus request；The piece for each address space that address decoding module is provided according to the configuration register group in expanded configuration space selects information that the read-write operation piece on parallel local bus is selected to the accessed resource for being decoded to each rear class；Initiator's request bag generation module is responsible for building request bag when needing to initiate RapidIO bus requests；Initiator responds received response bag after Packet analyzing module initiates this controller RapidIO bus requests and parses；The RapidIO bus requests that the needs that the logging modle of initiation bus request initiates controller respond bag record.The present invention is complete using the RapidIO controllers and its control method, good compatibility, function of window mapping mechanism.

Description

Using the RapidIO controllers and its control method of window mapping mechanism

Technical field

The invention belongs to embedded computing system field, more particularly to the RapidIO controllers using window mapping mechanism And its control method.

Background technology

With the continuous development of integrated avionics system, on the one hand, system is between each function module in its inside The speed and scale of data exchange and data transfer have the demand of higher, and traditional parallel bus is due to clock frequency and signal The limitation of cabling can not meet the needs of data transfer；On the other hand, since system scale is increasing, based on to system Fault-tolerance and the higher demand of grid reconstruct, common tree-shaped bus structures have been not suitable anymore for as the frame of whole system Structure pattern.Based on application demand so and development trend, avionics system needs to introduce a kind of new interconnection communication construction mode To solve the problems, such as these.

RapidIO technologies（ISO/IEC DIS18372）It is a kind of crossbar switch of the high-performance low pin count based on packet switch Interconnection technique, is first embedded system interconnection international standard.It employs high-speed serial bus technology, and bandwidth is high, delay Interconnection communication that is low, being adapted in high performance embedded system, is also admirably suitable for the tightly coupled working environment of more devices. RapidIO interconnection architectures use the internet topology based on interchanger more, the point-to-point of multiple RapidIO end equipments in system Communication link is woven in together by group of switches, and each end equipment is all the node of equity in the entire network.In this way, each end Equipment room can arbitrarily interconnect and concurrent transmission, really realizes multigroup concurrent data exchange, breaks through old " shared bandwidth " bottleneck, Bandwidth can be multiplied.It is cleverer additionally, due to the equity of each end equipments of RapidIO in the entire network, system configuration Living, scale can increase and decrease, and whole network will not be influenced when a certain end equipment breaks down, so can be System Error-tolerance Property Preferable technical support is provided with grid reconstruct.These advantages of RapidIO can be very good to solve integrated avionics Problem encountered in System Development, so building system using RapidIO technologies more and more in integrated avionic system Interior interconnection communication.

PowerPC and High Performance DSP processor chips new at present has RapidIO controllers mostly, this is also The structure of RapidIO grids and configuration management provide a convenient, but not all processor all provides this support. X86, ARM, and some old PowerPC, dsp processor chip all without RapidIO interfaces are provided, are in addition used at some FPGA is realized in the application of simple processor, is also lacked enough RapidIO and is supported, so using RapidIO as communication network System in when using these processors, it is necessary to some means allow these processors to be connected to as end equipment In RapidIO buses.A kind of feasible method is by bridge chip, such as has the bridge chip of PCIE-RapidIO.But due to bridge Chip usually only corresponds to a kind of other STD bus, it can not solve this ask to all types of processors with versatility Topic, and not all processor can search out suitable bridge chip as solution.Towards this demand, I Side designs and develops out a kind of new RapidIO controllers using window mapping mechanism based on fpga chip, can be various place Manage device extension RapidIO interfaces.

With the continuous development of FPGA technology, much the FPGA of manufacturers is each provided with multipath high-speed serial transceiver at present, It can be used for realizing Ethernet interface, the high speed serial bus interface such as PCIE or RapidIO.Based on this FPGA, many designs Programmable Analog Circuits the IP Core, conventional RapidIO IP Core that company develops RapidIO are accomplished that RapidIO The function of the physical layer of end equipment, transport layer and a part of logical layer, can carry out encoding and decoding, so as to change to high speed serialization code Operated for the parallel data signals of RapidIO bag forms.

The content of the invention

In order to solve the technical problem in the presence of background technology, the present invention proposes a kind of using window mapping mechanism RapidIO controllers and its control method, good compatibility, function are complete.

The present invention technical solution be：Using the RapidIO controllers of window mapping mechanism, it is characterised in that：Bag It is empty to include RapidIO IP Core, the parallel local bus interacted with ppu, address decoding module, expanded configuration Between, initiator's request bag generation module, initiator respond Packet analyzing module and initiate bus request logging modle；Address decoding The piece for each address space that module is provided according to the configuration register group in expanded configuration space selects information local parallel Read-write operation piece choosing in bus is decoded to the accessed resource of each rear class；Initiator's request bag generation module is responsible for needing Initiate to build request bag during RapidIO bus requests；Initiator responds Packet analyzing module and initiates RapidIO buses to this controller Received response bag is parsed after request, is obtained echo message therein and is supplied to other modules；Initiate bus request The RapidIO bus requests that the needs that logging modle initiates controller respond bag record.

Controller noted above further includes responder's request bag parsing module, responder responds bag generation module and extension is local total Line；The responder that responder's request bag parsing module monitors RapidIO IP Core asks packet interface to obtain RapidIO buses The operation requests bag that upper other equipment sends this controller, if the request bag is read-write requests, which is changed For the read-write operation on extension local bus, if the request bag is doorbell/message request, the doorbell parsed/message is believed Breath, which is sent in expanded configuration space, to be handled；Extend and the requested read-write of exterior RapidIO equipment is realized on local bus Operation, carry is both needed in the case where extending local bus by the local resource that distal end RapidIO equipment accesses；Responder responds bag generation Module is responded according to the situation structure that the relevant information and operation of request bag are completed and wraps and send, so as to complete for outside The whole response operation of RapidIO bus requests.

Controller noted above further includes data exchange double port memory, data exchange double port memory both by processor end and Row local bus accesses, and is accessed by the extension local bus of controller responder's function module.

Using the RapidIO control methods of window mapping mechanism, it is characterised in that：The described method includes controller each other simultaneously The in the following manner of row：

1）Controller initiates read-write requests process to exterior RapidIO equipment；

2）Controller initiates doorbell/message request process to exterior RapidIO equipment；

3）The read-write requests process of controller response external RapidIO equipment；

4）Doorbell/message request process of controller response external RapidIO equipment；

5）Communications and data transmission between controller and outside RapidIO equipment；

6）Error handle：6.1）Controller in the event of mistake, such as is returned to during the initiation request of exterior RapidIO equipment It should wrap and ask package informatin to mismatch, or not receive desired respond for a long time and wrap, then initiator responds Packet analyzing module Corresponding mistake can be found with the logging modle for initiating bus request, and the mistake in expanded configuration space is submitted in error message Processing unit by mistake；6.2）During the request that controller response external RapidIO equipment is sent, if request bag is wrong, respond Square request bag parsing module can parse corresponding mistake, and the error handle in expanded configuration space is submitted in error message Unit；6.3）Error handling unit in expanded configuration space records various error messages, and informs interrupt processing when necessary Unit, interrupt processing unit send interruption to processor again；After processor receives interruption, the error handle from expanded configuration space Read error information in related register, then carries out corresponding fault handling operation according to these information.

Aforesaid way 1）Specifically：

1.1）Processor is written and read by parallel local bus, some mapping window matches somebody with somebody in configuration expanded configuration space Register group is put, the ID of the address space of the window, mapping address and RapidIO target devices, read-write operation type are set；

1.2）Processor is written and read the address space of the mapping window operation, and address decoding module is by the read-write operation After progress piece translates code and address of cache selectively, initiator's request bag generation module is sent to；

1.3）After initiator's request bag generation module receives the read-write operation order of the mapping window, according to expanded configuration The configuration information for the window that space provides, builds corresponding read-write requests bag, and be sent to the initiator of RapidIOIP Core Packet interface is asked, if the request bag needs to respond bag, the information of request bag is issued to the record mould for initiating bus request at the same time Block is recorded by it and timing.It is further noted that if the data volume of this read-write operation requirement were larger, initiator Request bag generation module can also be configured to several RapidIO request bags and send out successively according to RapidIO specifications to be split Go out；

1.4）RapidIO IP Core pass through the high speed difference of physical layer after the RapidIO read-write requests bags to be initiated are received The request bag is sent in RapidIO buses by sub-signal；

1.5）Exterior RapidIO equipment carries out corresponding read-write operation after the RapidIO read-write requests bags are received, if The request needs to respond, then is also returned to this controller and respond bag；

1.6）After RapidIO IP Core receive response bag by " physical layer high-speed differential signal ", lead to after being decoded Cross initiator's response packet interface and issue initiator's response Packet analyzing module；

1.7）After initiator's response Packet analyzing module receives response bag, response package informatin is sent to the note for initiating bus request Module is recorded, allows it to record the performance of this read-write operation；Initiator responds Packet analyzing module by the response of read operation at the same time The complement mark of bag returned data or write operation is sent to initiator's request bag generation module；

1.8）Initiator's request bag generation module is in the returned data for receiving read operation or the completion mark for receiving write operation After will, this read-write operation of the mapping window is completed, and feedback is completed on address decoding module and parallel local bus step by step Corresponding read-write operation.

Aforesaid way 2）Specifically：

2.1）Processor is written and read by parallel local bus, the configuration of doorbell/message in configuration expanded configuration space Register group, sets doorbell/type of message, load data, the ID of RapidIO target devices, the mailbox number content of message transmission； After request bag related content is provided with, processor writes some command register for initiating doorbell/message request, so as to initiate This request；

2.2）Doorbell/message control unit in expanded configuration space is matched somebody with somebody after the order for initiating request is received from each The information that doorbell/message request is obtained in register is put, and is sent to initiator's request bag generation module；

2.3）Initiator's request bag generation module builds doorbell/message request according to corresponding information and is sent to RapidIO The initiator of IP Core asks packet interface, at the same the information of request bag issued initiate bus request logging modle allow its into Row record and timing；

2.4）RapidIO IP Core pass through physical layer after the RapidIO to be initiated doorbells/message request is received The request bag is sent in RapidIO buses by high-speed differential signal；

2.5）Exterior RapidIO equipment records doorbell/message after the RapidIO doorbells/message request is received, complete Into corresponding operating, then returned to this controller and respond bag；

2.6）After RapidIO IP Core receive response bag by physical layer high-speed differential signal, pass through after being decoded Initiator responds packet interface and issues initiator's response Packet analyzing module；

2.7）After initiator's response Packet analyzing module receives response bag, wherein information will both it feed back in expanded configuration space Doorbell/message control unit, be also sent to initiate bus request logging modle, allow it to record the completion feelings of this read-write operation Condition；

2.8）After doorbell/message control unit in expanded configuration space receives the response package informatin of feedback, then this is represented Secondary doorbell/message request has been completed, and complement mark is recorded in related register；If not receiving response bag for a long time, Whether see on demand will take re-transmission；Re-transmission then re-starts step 2.2）To step 2.8）.

Aforesaid way 3）Specifically：

3.1）After exterior RapidIO equipment initiates read-write requests by RapidIO buses to this controller, RapidIO IP Core receives the read-write requests bag in bus by physical layer high-speed differential signal, is connect after being decoded by responder's request bag Mouth issues responder's request bag parsing module；

3.2）After responder's request bag parsing module receives read-write requests bag, the operation class of wherein read-write operation is parsed Type, address, byte enable, the data of write-in, then go out to extend the read-write operation on local bus with these information architectures；At the same time Some information of read-write requests bag are also supplied to responder to respond bag generation module by responder's request bag parsing module；

3.3）Extension local bus is written and read the resource of its lower carry the read-write operation required by request bag, then will The returned data of read operation or the complement mark of write operation are sent to responder and respond bag generation module；

3.4）Responder responds bag generation module after the returned data or the complement mark of write operation for receiving read operation, The request package informatin provided according to responder's request bag parsing module, constructs corresponding respond and wraps, be then sent to RapidIO The responder of IP Core responds packet interface；

3.5）RapidIO IP Core pass through physical layer high-speed-differential after receiving this to be sent RapidIO and responding bag The response bag is sent in RapidIO buses by signal；

3.6）Exterior RapidIO equipment receives the response bag that this controller beams back by RapidIO buses, then completes it To this time read-write requests of this controller.

Aforesaid way 4）Specifically：

4.1）After exterior RapidIO equipment initiates doorbell/message request by RapidIO buses to this controller, RapidIO IP Core receive doorbell/message request in bus by physical layer high-speed differential signal, lead to after being decoded Crossing responder asks packet interface to issue responder's request bag parsing module；

4.2）After responder's request bag parsing module receives doorbell/message request, the information of doorbell/message is parsed And doorbell/message control unit in expanded configuration space is sent to, while it is supplied to responder to return some information of request bag Should bag generation module；

4.3）Responder responds doorbell/message request that bag generation module is provided according to responder's request bag parsing module Information, constructs the corresponding responder's response packet interface responded bag, be then sent to RapidIO IP Core；

4.4）RapidIO IP Core pass through physical layer high-speed-differential after receiving this to be sent RapidIO and responding bag The response bag is sent in RapidIO buses by signal；

4.5）Exterior RapidIO equipment receives the response bag that this controller beams back by RapidIO buses, then completes it To this time doorbell/message request of this controller；

4.6）Doorbell/message control unit in expanded configuration space is after doorbell/message request package informatin is received, by it It is placed in corresponding register and message data buffering area, then informs interrupt processing unit, interrupt processing unit is again to place Reason device sends interruption；

4.7）Processor reads from the doorbell/message related register in expanded configuration space and receives after interruption is received Doorbell/message request information, then carry out corresponding processing operation according to these information.

Aforesaid way 5）Specifically：

, both can be direct by this controller if mass data is sent to exterior RapidIO equipment from this controller Write operation is carried out to exterior RapidIO equipment, these data to be sent first can also be write into data exchange double port memory, Then these data are read from the memory by RapidIO buses by exterior RapidIO equipment；If mass data This controller is sent to from exterior RapidIO equipment, both reading behaviour directly can be carried out to exterior RapidIO equipment by this controller Make, these data can also first be write by data exchange twoport by RapidIO buses by exterior RapidIO equipment and stored Device, then native processor read these data from the memory again.

It is an advantage of the invention that：

1）Very well, its external interface respectively uses " parallel local total the compatibility of this controller for processor end Line ", for carry for the local resource of remote access " extension local bus " and RapidIO programmable logic IP Core with The interface " physical layer high-speed differential signal " of physical link.The first two bus has expansibility, the latter RapidIO IP Core has convertibility, this three determines the compatible outstanding part of this controller:

1.1）The scalability of " parallel local bus " that processor end uses, determines that this controller can be with " other The mode of bus-parallel local bus-RapidIO controllers-RapidIO buses " is by other any buses and at a high speed RapidIO buses carry out interconnection extension, and which provides a kind of new computing system framework mode.Since this controller can be Be extended in any bus, so as to can also carry out expanded application on any one processor, this just make those do not have There is use of the processor chips of integrated RapidIO controllers in RapidIO networks to become possibility.So on the one hand can be with Do not support RapidIO's using those in being to interconnect means of communication the embedded system that builds using RapidIO in a new generation The system upgrade interconnected using legacy bus, on the other hand can also be changed to the new system of RapidIO frameworks by processor System；

1.2）The scalability of " extension local bus " so that any type of local resource can easily carry exist Under responder's function module of this controller.In this way, for the different resource requirements for access of exterior RapidIO equipment, all may be used Very easily to be realized by the bus；

1.3）For different linear speeds (1.25/2.5/3.125/..Gbps) of the system to this controller and different lane numbers （1x/4x/…）Demand, RapidIO IP Core can be customized and change, and then be carried out in this controller simple Parameter setting and netlist are replaced, and can reach requirement.So different linear speeds and lane of this controller for RapidIO buses Number can be conveniently compatible；

Since this controller design has these good compatibility, so number of types of application scenario is applicable to, Face the future using can also be researched and developed according to the FPGA design, form the asic chip of fixed function；

2）This controller has used window mapping mechanism to realize the initiation of RapidIO read-write requests, has outstanding soft Part compatibility, it is flexibly easy-to-use for various application and developments.The mechanism, can be by commonly after appropriate window configuration is carried out Read-write operation be converted to the initiation of read-write requests bag in RapidIO buses and respond the parsing of bag, thus can be as visiting Ask the RapidIO equipment that common memory headroom is equally gone outside access, mode in this way is also convenient for different outsides For the different address space reflection of RapidIO equipment to local each address space, simplicity is easy-to-use, can meet that user's is various Application demand.In addition it is important that can be gone to access as accessing local memory space by window mapping mechanism Exterior RapidIO equipment, this is also the providing a convenient property of application and feasibility of DMA (direct memory access (DMA))；

3）This controller function is complete, can support to read and write, message, the various functions such as doorbell, and most of all, the control The initiation of device support maintenance read-write requests bag processed, this means that this controller can be initiated for other RapidIO equipment The read-write of configuration space, so as to the manager and guardian of the RapidIO networks as whole system.So, it is only necessary to Have this controller, it is possible to configure and safeguard whole RapidIO networks, this also present this controller function it is powerful with it is complete It is standby；

4）This controller supports burst type (burst) read-write operation, DMA transfer can be supported, so as to maximumlly Utilize the high bandwidth characteristic of RapidIO.And this controller has carried out subpackage and the work of group bag in inside, so front end is " simultaneously Burst read-write operations width on row local bus " is simultaneously not affected by the limitation for the data load length wrapped in RapidIO specifications. The maximum data load that a RapidIO bag is provided in RapidIO specifications is 256 bytes, and this controller passes through in " initiator Subpackage and group job contract inside being realized in request bag generation module " are made, and behaviour is read and write to the burst on front end " parallel local bus " Making width supports scope to be up to 4095 bytes.

Brief description of the drawings

Fig. 1 is the hardware block diagram of this controller invention；

Fig. 2 is the schematic diagram of the window mapping mechanism of this controller invention；

Fig. 3 be this controller as bus request initiator when address space distribution diagram；

Fig. 4 be this controller as bus request responder when address space distribution diagram；

Subpackage and group bag schematic diagram when Fig. 5 is the progress burst read operations of this controller；

Fig. 6 is subpackage schematic diagram when this controller carries out burst write operations；

Embodiment

This controller is to use the FPGA with high speed serialization transceiver to may be programmed as platform in conventional RapidIO Secondary development is carried out on the basis of logical ip Core to realize, the front end of controller is a parallel local bus, rear end For the HSSI High-Speed Serial Interface of RapidIO interfaces, the mechanism that is mapped using address window, realize parallel local bus operation with Mutual conversion between RapidIO bus operations.

The hardware composition of this controller is as shown in Figure 1.The controller is in conventional RapidIO programmable logic IP Carried out on Core obtained by secondary development, the square modules of 1 right side central of attached drawing are RapidIO IP Core, it is realized High speed serialization code on physical link and the mutual conversion between the parallel data signal of RapidIO bag forms.RapidIO IP Core mainly has six external interfaces, is respectively " configuration space access interface ", " physical layer high-speed differential signal ", " initiator Request packet interface ", " initiator responds packet interface ", " responder asks packet interface ", " responder responds packet interface ".Foundation RapidIO specifications, each RapidIO equipment have a configuration space, and " configuration space access interface " is to RapidIO IP The interface that the configuration space of Core accesses, can read and write 0x0 to the 0xFFFF configuration spaces address of RapidIO IP Core Section." physical layer high-speed differential signal " is the high speed serialization code on physical link, via FPGA high speed serialization transceiver with Exterior RapidIO buses are connected, and are typically connected to a RapidIO interchanger.The RapidIO end equipments of one complete function Both it can ask to initiation in bus, the request of other RapidIO end equipments in bus can also be responded.When this controller During initiator as bus request, it be by IP Core " initiator asks packet interface " to send operation in bus please Bag is sought, then monitors " initiator responds packet interface " to obtain the response bag for initiating to ask, so as to complete whole bus request behaviour Make.As responder of this controller as bus request, it monitors " responder asks packet interface " to obtain in bus other The operation requests bag that equipment sends this controller, after operation requests are completed, then by " responder respond packet interface " to this The initiator device of secondary operation requests sends corresponding respond and wraps, so as to complete whole bus response operation.Except above-described Outside primary interface, RapidIO IP Core also have some marking signals for being used to indicate current link conditions.

This controller is also broadly divided into initiator's work(of bus request around the RapidIO IP Core secondary development carried out Can module and responder function module two large divisions.Initiator's function module is the left part of attached drawing 1, by " parallel local total Line ", " address decoding module ", " expanded configuration space ", " initiator's request bag generation module ", " initiator responds Packet analyzing mould Block " and " logging modle for initiating bus request " six most of collaboration composition.Wherein, " parallel local bus " is and external treatment The interface that device interacts, ppu control whole RapidIO to control by the read-write operation to parallel local bus Device.Each address space that configuration register group in " address decoding module " basis " expanded configuration space " is provided（Respectively reflect Penetrate window access space, data exchange storage addressing space）Piece select information by " parallel local bus " read-write grasp Make the accessed resource that piece choosing is decoded to each rear class." expanded configuration space " is the expansion of this RapidIO controller configuration spaces Open up part（The 0x10000-0xFFFFFF addresses retained are realized in device configuration space by concrete application i.e. in RapidIO specifications Section）, the mapping window configuration of this controller, doorbell/Message Processing, error monitoring, interrupt processing, version are realized in the space The relevant register of various functions such as control, link state monitoring, and it is integrated with error handling unit, door around these registers Bell/message control unit and interrupt processing unit etc.." initiator's request bag generation module " is responsible for needing initiation RapidIO total Line builds request bag when asking, and request bag is broadly divided into two big type of read-write requests and doorbell/message request.Read-write requests are logical Cross window mapping mechanism to realize, by " expanded configuration space ", " address decoding module ", " initiator's request bag generation module " " initiator responds Packet analyzing module " is common to complete, complex, later " workflow of each function of the present invention " and " tool It is described in detail again in body embodiment " chapters and sections.Doorbell/message request is more relatively easy, is according in " expanded configuration space " The content of related register, constructs the relevant information of request bag by doorbell/message control unit and is supplied to " initiator's request Bag generation module ".Received respond is wrapped after " initiator responds Packet analyzing module " initiates this controller RapidIO bus requests Parsed, obtain echo message therein and be supplied to other modules.The main work of " logging modle for initiating bus request " Work is that the RapidIO bus requests that the needs that this controller is initiated are responded with bag record, and one side, which checks, to be responded bag and ask Ask whether bag matches and report relevant error, on the other hand timing is carried out to the bus request that need to be responded, if not receiving for a long time Bag is responded to desired, then reports that bus request time-out does not respond mistake.

Responder's function module of this controller is the lower right-most portion of attached drawing 1, comprising " responder's request bag parsing module ", " responder responds bag generation module " and " extension local bus " three components." responder's request bag parsing module " is monitored " responder asks packet interface " of RapidIO IP Core sends this controller to obtain other equipment in RapidIO buses Operation requests bag, if the request bag is read-write requests, which is converted into the read-write on " extension local bus " Operation, if the request bag is doorbell/message request, the doorbell/information parsed is sent in " expanded configuration space " In handled.The requested read-write operation of exterior RapidIO equipment is realized on " extension local bus ", can be by distal end The local resource that RapidIO equipment accesses is both needed to carry under " extension local bus ".After the operation of external request is completed, The situation structure that " responder responds bag generation module " then completes according to the relevant information of request bag and operation, which is responded, to be wrapped and sends, So as to complete the whole response operation for exterior RapidIO bus requests.

1 lower left corner of attached drawing is one " data exchange double port memory ", which both can be by the " parallel of processor end Local bus " accesses, and can be accessed by " the extension local bus " of controller responder's function module（So as to exterior RapidIO equipment accesses）.So data can be carried out by the memory between native processor and outside RapidIO equipment Exchange.The memory can be realized inside FPGA, if it is desired to which extended storage capacity, can also use storage core outside FPGA Piece is realized.

Above-mentioned RapidIO programmable logic IP Core, initiator's function module, responder's function module and data are handed over Double port memory combination is changed, is cooperated, together form the hardware components of this RapidIO controllers invention.Respectively Coordinated relation between comprising modules, reference can be made to " workflow of each function of the present invention " and " embodiment " hereinafter Related content in chapters and sections.

The workflow of each function of the present invention is：

This RapidIO controllers can initiate bus request to exterior RapidIO equipment, also respond other RapidIO and set Standby bus request, can be by being communicated and data transfer between RapidIO buses and external equipment.Bus request is divided into Read-write requests and doorbell/message request two types.The workflow of the several major functions of this controller is as follows：

1）Controller initiates read-write requests process to exterior RapidIO equipment：1.1）Processor passes through parallel local bus It is written and read, the configuration register group of some mapping window, sets the address space of the window, reflect in configuration expanded configuration space Penetrate the ID of address and RapidIO target devices, read-write operation type；

1.3）After initiator's request bag generation module receives the read-write operation order of the mapping window, according to expanded configuration The configuration information for the window that space provides, builds corresponding read-write requests bag, and be sent to the initiator of RapidIO IP Core Packet interface is asked, if the request bag needs to respond bag, the information of request bag is issued to the record mould for initiating bus request at the same time Block is recorded by it and timing.It is further noted that if the data volume of this read-write operation requirement were larger, initiator Request bag generation module can also be configured to several RapidIO request bags and send out successively according to RapidIO specifications to be split Go out；

2）Controller initiates doorbell/message request process to exterior RapidIO equipment：

3）The read-write requests process of controller response external RapidIO equipment：

4）Doorbell/message request process of controller response external RapidIO equipment：

5）Communications and data transmission between controller and outside RapidIO equipment；If mass data from this control Device processed is sent to exterior RapidIO equipment, and portion's RapidIO equipment can have both been directed out by this controller and has carried out write operation, These data to be sent first can be write into data exchange double port memory, then be passed through by exterior RapidIO equipment RapidIO buses from the memory read these data；If mass data is sent to this control from exterior RapidIO equipment Device processed, both directly can carry out read operation to exterior RapidIO equipment by this controller, can also be set by exterior RapidIO Standby that these data are first write data exchange double port memory by RapidIO buses, then native processor is deposited from this again Reservoir reads these data.

6）Error handle：Controller in the event of mistake, such as responds bag to during the initiation request of exterior RapidIO equipment Mismatched with request package informatin, or do not receive for a long time it is desired respond bag, then " initiator respond Packet analyzing module " and " logging modle for initiating bus request " can find corresponding mistake, and error message is submitted in " expanded configuration space " Error handling unit.During the request that controller response external RapidIO equipment is sent, if request bag is wrong, " responder Request bag parsing module " can parse corresponding mistake, and error message be submitted at the mistake in " expanded configuration space " Manage unit.Error handling unit in " expanded configuration space " records various error messages, and informs interrupt processing when necessary Unit, interrupt processing unit send interruption to processor again.After processor receives interruption, at the mistake in " expanded configuration space " Read error information in related register is managed, then carries out corresponding fault handling operation according to these information.

The present invention is described in further details below.

Since the design comparison is complicated, so needing to illustrate the hardware design of the present invention in terms of two：The A part illustrates the implementation strategy of some complex mechanisms of this controller from overall angle, and Part II introduces each hardware respectively The respective implementation of comprising modules.

1）The overall implementation strategy of some complex mechanisms

1.1）Window mapping mechanism

The realization mechanism of window mapping mechanism is：For each exterior RapidIO equipment to be accessed certain sector address this A sector address space is opened up on ground, this section of home address space is referred to as to map window, then by the read and write access to mapping window The initiation to the read-write requests bag of exterior RapidIO equipment and the corresponding parsing for responding bag are converted into, so as to reach to outside The read and write access of RapidIO equipment.Mode in this way, will map every attribute of window（Plot, space size, mesh Marking device ID, mapping address, read and write access type, priority etc.）After configuration is good, it is possible to as accessing local storage space Equally go to access exterior RapidIO equipment, it is corresponding use for, it is simple, flexible, conveniently, it is transparent, and DMA can be supported to pass It is defeated, maximumlly utilize the high bandwidth characteristic of RapidIO.

The realization principle of window mapping mechanism is as shown in Figure 2.The configuration information of each mapping window, can pass through read-write Related register group in " expanded configuration space " is set, and then " expanded configuration space " puies forward the information of each mapping window Supply " address decoding module " and " initiator's request bag generation module ".The window plot for mapping window 2 is arranged in attached drawing 2 0x1300_0000, window size 0x10_0000, mapping plot are 0x8000_0000, this represents the local of mapping window 2 Address realm is 0x1300_0000 to 0x130F_FFFF, and the 0x8000_0000 of correspondence mappings to exterior RapidIO equipment is arrived 0x800F_FFFF address realms.In this way, when address 0x1300_8C40 is being read at processor end, " address decoding module " is through ground After the decoding of location, it is found that it has hit mapping window 2, just the read operation of Front Side Bus is changed the reading behaviour for penetrating window 2 for mapping Make, and be 0x8000_8C40 by address of cache." initiator's request bag generation module " is receiving the address to mapping window 2 After the read access of 0x8000_8C40, according to the other information of the mapping window（Purpose equipment ID, read-write type, priority etc.）, State machine is generated by internal request bag to construct a read request packet and be sent to RapidIO IP Core, the read request Every terms of information after bag generation is as shown in Figure 2.Mode in this way, this controller is just one to local 0x1300_ The read access of 8C40 addresses, change in order to one to ID into the 0x8000_8C40 addresses of the exterior RapidIO equipment of 0x1 NREAD request bags.

After the exterior RapidIO equipment that ID is 0x1 responds received read request packet and returns to response bag, RapidIO IP Core receive response bag, it are issued " initiator responds Packet analyzing module ".The every terms of information for responding bag is for example attached Shown in Fig. 2, returned data therein is 0x55AA_55AA." initiator responds Packet analyzing module " parses the data for responding bag After going out, " initiator request bag generation module " and " address decoding module " are fed back to step by step, and eventually as to 0x1300_8C40 Read operation returned data.This completes whole read operation process.

As described above, after mapping window is configured, the read access for the address 0x1300_8C40 in window 2, Be eventually converted into ID be 0x1 exterior RapidIO equipment 0x8000_8C40 addresses NREAD request bags structure with The corresponding parsing for responding bag, and the reading data 0x55AA_55AA returned, here it is window mapping mechanism.Pass through this side Formula, can go to access the different address space of the distinct device in RapidIO buses, band as accessing local storage space Convenience and the transparency to user's maximum.

It is also noted that be a bit, due to safeguarding read-write requests bag（Maintenance read/write）With other classes The read-write requests bag of type has more difference in form, information and inter-process mode, so the mapping inside this controller Window has been divided into two types：To safeguard read-write mapping window, the read and write access to such mapping window can only be converted to one kind Safeguard read-write（Maintenance read/write）Request bag；Another kind maps window for common read-write, to such map pane The read and write access of mouth can be converted to common read-write（NREAD/NWRITE/NWRITE_R/SWRITE）Request bag or atom are read Write（ATOMIC inc/dec/……）Request bag, common read-write map configuration of the specific translation type of window according to the window The content of the related register of read-write operation type determines.1 is provided with this controller altogether and safeguards read-write mapping window With 16 common read-write mapping windows.In RapidIO specifications, what common read-write requests bag and atom read-write requests bag accessed is The bus space of RapidIO equipment, safeguard the access of read-write requests bag is the configuration space of RapidIO equipment.So work as needs When accessing the configuration space of other RapidIO equipment（Such as when carrying out the configuration and maintenance of RapidIO exchange networks）, should use The maintenance read-write mapping window of this controller；When needing to access the bus space of other RapidIO equipment（Such as RapidIO When data exchange between equipment and communication）, the common read-write of this controller should be used to map window.

1.2）Address space distributes

This controller both can be as the initiator asked in RapidIO buses, can also be square in response, so its ground The distribution in location space is also corresponding with such two kinds of situations.

As initiator of this controller as RapidIO bus requests, it is typically carry on the ground of a processor Location is accessed by it under space, and the method for salary distribution of its address space is shown in attached drawing 3.Processor is whole RapidIO controllers distribution one Sector address space, when processor accesses the address that the address space bias internal amount is 0x0 to 0xFFFF, access is this 0x0 to the 0xFFFF address fields of the configuration space of RapidIO controllers, are when processor accesses the address space bias internal amount During the address of 0x10000 to 0xFFFFFF, access be the RapidIO controllers as shown in Figure 1 " expanded configuration is empty Between ", i.e., each mapping window configuration, doorbell/message controls, error handle, interrupt processing, the deposit of Version Control etc. function Device.By the configuration to mapping window related register, each address space for mapping window can be further specified that（See attached drawing 3 dotted portion）.In addition, processor is also to pass through corresponding registers to the access address space of data exchange double port memory The mode of configuration is come definite.Finally, each mapping window further according to its configuration register content map to each specifying RapidIO device ids and its address field.

As responder of this controller as RapidIO bus requests, it has two parts address space.Such as the institute of attached drawing 4 Show, when exterior RapidIO equipment carries out maintenance read-write to this controller（Maintenance read/write）, can be with during request Have access to 0x0 to the 0xFFFF address fields of this controller configuration space；When carrying out common read-write requests, access is this control " the extension local bus " of responder's function module of device.The resource of carry is deposited for data exchange twoport under " extension local bus " Reservoir and each local resource accessed for exterior RapidIO equipment.

1.3）Initiator's request bag is with responding checking for bag

As initiator of this controller as RapidIO bus requests, request bag is initiated to exterior RapidIO equipment, According to the difference of request Packet type, certain form of request bag needs counterpart device to return to corresponding response bag.It is total in order to ensure The correctness and reliability of line request operation, controller need to match initiator's request bag and response bag correspondingly Check.

In RapidIO specifications, request bag and its it is corresponding respond in bag, have that some customizing messages are consistent and one is a pair of Answer, this controller makes requests on bag and respond checking for bag according to these customizing messages.For read-write requests and door Bell is asked, and is made requests on bag with the Transaction ID in bag and is responded the correspondence of bag；For message request, with message Letter, mbox and msgseg/xmbox make requests on bag and respond the correspondence of bag jointly.Herein, by RapidIO request bags It is referred to as " match index " with these the specific corresponding informances for responding bag.

When " initiator's request bag generation module " is built and sends a RapidIO request bag, if the request bag needs Bag is responded accordingly, then the information of the request bag is submitted to " logging modle for initiating bus request "." initiate bus request Logging modle " information of request bag is deposited into an internal storage with " match index " for address, and each please Bag is asked to safeguard that an internal counter carries out timing.This controller is provided with 32 such internal counters, so initiator Function module at most can have 32 request bags to be responded at the same time.

When " initiator responds Packet analyzing module ", which receives a RapidIO, responds bag, the information of the response bag is submitted To " logging modle for initiating bus request "." logging modle for initiating bus request " is with " match index " information in response bag For address, the related data in inquiry request package informatin memory, obtains asking package informatin accordingly, then will ask package informatin Compared and analyzed with responding package informatin, check whether matching, by the request bag in request bag information-storing device if matching Erasing of information, and its corresponding internal counter is closed, report mistake if mismatching.

By above mechanism, it on the one hand can check whether response bag can correctly match with request bag, if mismatching Report mistake, if not receiving response bag after on the other hand certain request bag is initiated for a long time, foregoing count internal can be passed through Device is monitored, if counter is overtime, reports time-out error.The timeouts of the counter are can to pass through configuration space Corresponding registers configured.

1.4）Realization and subpackage and the group of initiator's burst type (burst) read-write are wrapped

In order to maximally utilize the high bandwidth characteristic of RapidIO high-speed serial bus, this controller realizes burst type (burst) read and write, burst read-writes will transmit more beat of data in a read-write operation.Due to the number of RapidIO read-write requests bags It is as defined in RapidIO specifications according to loaded length, and the data volume of burst read-write is determined by processor and its bus , so there is the problem of being fitted to each other between both.When the number that the burst of " parallel local bus " is read and write at processor end According to the data load length of read-write requests bag as defined in length and RapidIO specifications it is inconsistent when, this controller " initiator please Seek bag generation module " subpackage and the processing of group bag have been carried out, to use multiple RapidIO request bags to complete a burst read-write behaviour Make.

For read request packet, provided in RapidIO specifications its length can be 1-8,16,32,64,96,128,160, 192nd, 224,256 byte.When the data length of front end burst read operations is not these length, with regard to carrying out subpackage operation.When It is 300 words that " initiator's request bag generation module ", which is received to the burst length of some mapping window 0x8000_0000 mapping address, During the read operation of section, the flow of its subpackage and group bag is as shown in Figure 5.The state machine of structure initiator's request bag is built simultaneously first The read request packet that the read request length that first address is 0x8000_0000 is 256 bytes is sent, treats that its data response bag receives And then the read request length that second address of structure is 0x8000_0100 is the read request packet of 32 bytes and sends, class successively The read request packet of the read request packet and the 4th 4 bytes that continue the 3rd 8 bytes of transmission is pushed away, is finally completed the reading behaviour of 300 bytes Make.In this process, the data of each data response bag return to Front Side Bus successively, complete whole burst read operations.

For write request bag, it can be the byte of 1-8,16,32,64,128,256 that its length is provided in RapidIO specifications.When When the data length of front end burst write operations is not these length, with regard to carrying out subpackage operation.When " initiator's request bag generates mould Block " receive to some mapping window 0x8000_0000 mapping address burst length be 300 bytes write operation when, its subpackage Flow is as shown in Figure 6.The state machine of structure initiator's request bag builds and sends four write request bags successively, and " data are grown for it Degree/address " is followed successively by 256/0x8000_0000,32/0x8000_0100,8/0x8000_0120,4/0x8000_0128, each There is the write operation write data load, be finally completed 300 bytes of corresponding length in write request bag.

2）The specific implementation of each comprising modules

2.1）Expanded configuration space

0x10000 to the 0xFFFFFF addresses of the configuration space of RapidIO controllers are realized in " expanded configuration space " Section and the read-write capability to this partial address.The configuration register of each function of controller realized in this section, including Map window configuration register, doorbell/messaging control register, error handle register, interrupt processing register, data exchange Double port memory configuration register, version management register, link state control register etc..In addition " expanded configuration space " Integrate some functions relevant with each register to realize, such as the information for mapping window configuration register is supplied to other moulds Block, the processing of doorbell/message, error message record, interrupt enabled and shielding, data exchange double port memory access address Configuration etc..The several larger word function modules integrated in " expanded configuration space " have：

2.1.1）Doorbell/message control unit

" doorbell/message control unit " is on the one hand responsible for this controller and initiates doorbell/message request to external equipment, On the other hand doorbell/the message that sent to external equipment is handled.

When initiating doorbell/message, information of the control unit in corresponding configuration register and data buffer zone, door The information of bell/message request is sent to " initiator's request bag generation module " and allows it to build respective request bag and send.Then control Unit processed starts waiting for the response bag of the request bag, and time-out error occurs or have received back if not receiving response bag for a long time It should wrap but respond bag and represent this time request operation when being not successfully completed, control unit re-initiates this doorbell/message request, Until request successfully completes or has reached the sending times limited.If reach the sending times upper limit not complete still but This time doorbell/message request, then recording-related information send interruption to corresponding registers and to " interrupt processing unit " to notify Processor carries out subsequent treatment.

When receiving doorbell/message that external equipment is sent, control unit is stored in the information of these doorbell/message In corresponding register and data buffer zone, then to " interrupt processing unit " send interruption come notifier processes device from register and Read the information content of doorbell and message in data buffer zone.Further, since the message of RapidIO is mailbox, each RapidIO equipment can have multiple mailboxes, so to safeguard a message data buffering area for each mailbox number of this control Domain.

2.1.2）Error handling unit

" error handling unit ", which classifies the error message occurred in whole RapidIO controllers functions module, to be remembered Record and be stored in register and buffering area, refer to the error handle portion in the chapters and sections for introducing this controller workflow above Point.Then " error handling unit " is according to the danger classes and number that mistake occurs, to determine whether needs pass through the side interrupted Formula carrys out notifier processes device.Interrupted if necessary to produce, then send interruption to " interrupt processing unit " and carry out notifier processes device from deposit Read current error message record in device and buffering area.

2.1.3）Interrupt processing unit

" interrupt processing unit " summarizes the various interrupt events for needing processor to be responded, such as this controller occurs Mistake, physical link are reached the standard grade and offline, transmission doorbell/message failure, receive exterior doorbell/message etc.." interrupt processing list Member " can be enabled and shielded to these interrupt events according to the setting for interrupting related register, if certain does not shield There occurs then interrupt signal is set to by " interrupt processing unit " effectively carrys out notifier processes device and is accordingly grasped the interrupt event covered Make.After processor receives interruption, can read represent Current interrupt state register come judge be there occurs which kind of interrupt thing Part, and be further processed.

2.2）Address decoding module

" address decoding module " obtains each mapping window from " expanded configuration space " and data exchange double port memory Access address segment information, is used as the foundation of address decoding.

When processor end is written and read access to " parallel local bus ", the address that " address decoding module " accesses carries out Address decoding：The access of 0x0 to 0xFFFF is decoded as the access of the configuration space to RapidIO IP Core；By 0x10000 Access to 0xFFFFFF is decoded as access to each register in " expanded configuration space "；Will be to data exchange double port memory The access of access address section is decoded as the read-write to the memory；By row address mapping of going forward side by side to the access decoding of each mapping window After be transmitted to " initiator's request bag generation module ".

2.3）Initiator's request bag generation module

" initiator's request bag generation module " use state machine makes requests on the structure of bag.Some is mapped when receiving When the read and write access of window or the initiation of doorbell/message request, starting state machine, then state machine is according to the ground of read and write access Location, data, map the configuration information of window and the solicited message of doorbell/message to build request bag, and are sent to RapidIO " initiator asks packet interface " of IP Core.If the request bag sent needs to respond bag, it is also necessary to by the information of the request bag Presenting " logging modle for initiating bus request " allows its record to be checked in case carrying out response bag.

When the read and write access to mapping window accesses for burst type (burst), " initiator's request bag generation module " can It can also need to carry out subpackage and group job contract is made, " the realization of initiator's burst type (burst) read-write above of this part operational detail And subpackage and group are wrapped " chapters and sections have been described in detail, have repeated no more.

2.4）Initiator responds Packet analyzing module

" initiator responds Packet analyzing module " parses received response bag after initiating bus request.If doorbell/ The response bag of message, need to issue echo message the doorbell/message elements in " expanded configuration space " to allow it to be handled, if The band data response bag that read request returns, need to issue the data parsed " initiator's request module " to allow it to complete map pane The read operation of mouth.

When being parsed to responding bag, if it find that having the mistake such as form, it is necessary to which error message is reported to " extension is matched somebody with somebody Between emptying " error handling unit." initiated in addition, " initiator responds Packet analyzing module " also needs a response package informatin to be transmitted to The logging modle of bus request " allows it to carry out response bag and checks.

2.5）Initiate the logging modle of bus request

A request bag information-storing device and 32 internal counters are realized in " logging modle for initiating bus request ", And request bag is carried out using these memories and counter and has responded checking for bag.Request bag information-storing device is used to deposit The information of the request bag for the bag that awaits a response is stored up, is checked according to it after responding bag and returning, internal counter is used to treat The request bag of response carries out timing, to judge whether that there occurs the mistake that bus request time-out does not receive response.If it find that Mistake error message, it is necessary to report the error handling unit to " expanded configuration space ".The realization of these functions " is sent out above Square request bag is played with responding checking of wrapping " chapters and sections have been described in detail, have repeated no more.

2.6）Responder's request bag parsing module

" responder's request bag parsing module " after the request bag of exterior RapidIO equipment is received, to the content of request bag Parsed, different operations is done according to different request Packet types.If doorbell/message request, then by letter therein Breath parses and is sent to the doorbell/message control unit in " expanded configuration space " and is further processed.If read-write requests Bag, then enable address therein, data, byte, accesses the information such as data length (burst length) and parses, then builds Go out corresponding read and write access operation and be sent to the rear class resource that " extension local bus " goes to allow it to access its carry.

When being parsed to request bag, if it find that having the mistake such as form, it is necessary to which error message is reported to " extension is matched somebody with somebody Between emptying " error handling unit.In addition, " responder's request bag parsing module " also needs to that the request bag for responding bag will be needed to believe Breath forwarding is toward " responder responds bag generation module ", to allow its structure to respond bag.

2.7）Responder responds bag generation module

After the request bag that exterior RapidIO equipment is sent, if the request bag needs to respond bag, " responder responds Bag generation module " is responded to wrap and be sent to RapidIO IP Core accordingly according to the information architecture of request bag allows it to send.

For the response bag without data load, it is only necessary to can build response bag according to the information of request bag；For band The response bag of data load, in addition to the information of request bag, it is also necessary to use the returned data of read operation on " extension local bus " Bag is responded to build.

2.8）Data exchange double port memory

" data exchange double port memory " includes two access ports, both can be by " the parallel local bus " at processor end Access, can also be accessed by " the extension local bus " at responder's function module end, so reach native processor and outside The data exchange of RapidIO equipment.In the chapters and sections for introducing this controller workflow above, to reaching data using the memory The access mode of communication is described.

" data exchange double port memory " can be realized inside FPGA, but memory capacity can limit, if desired The capacity of bigger, can also be realized outside FPGA using dedicated memory chip.

2.9）Parallel local bus and extension local bus

This controller includes Liang Ge local bus interfaces, is respectively " the parallel local bus " and responder's work(at processor end " the extension local bus " of energy module end." parallel local bus " is to access this controller by processor, and " extension is local total Line " is this controller to access the rear class resource of other carries, both access direction difference.

Two sets of parallel bus are in addition to conventional clock, reset, piece choosing, reading and writing, address, data, byte enable, also Burst access flags are increased newly, burst access widths, read response of shaking hands, write the signals such as response of shaking hands, and come using these signals Complete burst read-write operations.

Claims

1. using the RapidIO control methods of window mapping mechanism, it is characterised in that：It is alongside one another the described method includes controller In the following manner：

1) controller initiates read-write requests process to exterior RapidIO equipment；

2) controller initiates doorbell/message request process to exterior RapidIO equipment；

3) the read-write requests process of controller response external RapidIO equipment；

4) doorbell of controller response external RapidIO equipment/message request process；

5) the communications and data transmission between controller and outside RapidIO equipment；

6) error handle：6.1) controller, in the event of mistake, is responded bag and is asked to during the initiation request of exterior RapidIO equipment Ask package informatin to mismatch, or do not receive desired respond for a long time and wrap, then initiator responds Packet analyzing module and initiates total The logging modle of line request can find corresponding mistake, and error message be submitted to the error handle list in expanded configuration space Member；6.2) during the request that controller response external RapidIO equipment is sent, if request bag is wrong, responder's request bag Parsing module can parse corresponding mistake, and the error handling unit in expanded configuration space is submitted in error message； 6.3) error handling unit in expanded configuration space records various error messages, and informs interrupt processing unit, interrupt processing Unit sends interruption to processor again；After processor receives interruption, read from the error handling unit in expanded configuration space Error message, then carries out corresponding fault handling operation according to these error messages；

The mode 1) be specifically：

1.1) processor is written and read by parallel local bus, and the configuration for configuring some mapping window in expanded configuration space is posted Storage group, sets the ID of the address space of the mapping window, mapping address and RapidIO target devices, read-write operation type；

1.2) processor is written and read the address space of the mapping window operation, and address decoding module carries out the read-write operation After piece translates code and address of cache selectively, initiator's request bag generation module is sent to；

1.3) after initiator's request bag generation module receives the read-write operation order of the mapping window, according to expanded configuration space The configuration information of the window provided, builds corresponding read-write requests bag, and is sent to initiator's request of RapidIO IP Core The information of request bag, if the read-write requests bag needs to respond bag, is issued the record mould for initiating bus request by packet interface at the same time Block is recorded by it and timing；If the data volume of read-write operation requirement is big, initiator's request bag generation module can also root Split according to RapidIO specifications and be configured to several RapidIO request bags and send successively；

1.4) RapidIO IP Core are believed after the RapidIO read-write requests bags to be initiated are received by physical layer high-speed-differential Number the request bag is sent in RapidIO buses；

1.5) exterior RapidIO equipment carries out corresponding read-write operation, if the reading after the RapidIO read-write requests bags are received Write request needs to respond, then is also returned to this controller and respond bag；

1.6) after RapidIO IP Core receive response bag by " physical layer high-speed differential signal ", hair is passed through after being decoded Play side's response packet interface and issue initiator's response Packet analyzing module；

1.7) after initiator's response Packet analyzing module receives response bag, response package informatin is sent to the record mould for initiating bus request Block, allows it to record the performance of this read-write operation；Initiator responds Packet analyzing module and returns the response bag of read operation at the same time The complement mark for returning data or write operation is sent to initiator's request bag generation module；

1.8) initiator's request bag generation module is after receiving the returned data of read operation or receiving the complement mark of write operation, This read-write operation of the mapping window is completed, and it is corresponding in feedback completion address decoding module and parallel local bus step by step Read-write operation.

2. the RapidIO control methods according to claim 1 using window mapping mechanism, it is characterised in that：The side Formula 2) be specifically：

2.1) processor is written and read by parallel local bus, the configuration deposit of doorbell/message in configuration expanded configuration space Device group, sets doorbell/type of message, load data, the ID of RapidIO target devices, the mailbox number content of message transmission；Treating please After asking bag related content to be provided with, processor writes some command register for initiating doorbell/message request, so as to initiate the door Bell/message request；

2.2) doorbell/message control unit in expanded configuration space is posted after the order for initiating request is received from each configuration The information of doorbell/message request is obtained in storage, and is sent to initiator's request bag generation module；

2.3) initiator's request bag generation module builds doorbell/message request according to corresponding information and is sent to RapidIO IP The initiator of Core asks packet interface, while the information of request bag issued and initiates the logging modle of bus request and allows it to be remembered Record and timing；

2.4) RapidIO IP Core are after the RapidIO to be initiated doorbells/message request is received, by physical layer at a high speed The request bag is sent in RapidIO buses by differential signal；

2.5) exterior RapidIO equipment records doorbell/message after the RapidIO doorbells/message request is received, and completes phase It should operate, then be returned to this controller and respond bag；

2.6) after RapidIO IP Core receive response bag by physical layer high-speed differential signal, initiation is passed through after being decoded Fang Huiying packet interfaces issue initiator and respond Packet analyzing module；

2.7) after initiator's response Packet analyzing module receives response bag, wherein information the door in expanded configuration space had both been fed back into Bell/message control unit, is also sent to the logging modle for initiating bus request, allows it to record the performance of this read-write operation；

2.8) after doorbell/message control unit in expanded configuration space receives the response package informatin of feedback, then this door is represented Bell/message request has been completed, and complement mark is recorded in related register；If not receiving response bag for a long time, confirm Whether re-transmission is taken；Re-transmission then re-starts step 2.2) and arrives step 2.8).

3. the RapidIO control methods according to claim 1 using window mapping mechanism, it is characterised in that：The side Formula 3) be specifically：

3.1) after exterior RapidIO equipment initiates read-write requests by RapidIO buses to this controller, RapidIO IP Core receives the read-write requests bag in bus by physical layer high-speed differential signal, is connect after being decoded by responder's request bag Mouth issues responder's request bag parsing module；

3.2) after responder's request bag parsing module receives read-write requests bag, the action type of wherein read-write operation is parsed, Address, byte enable, the data of write-in, then go out to extend the read-write operation on local bus with these information architectures；Ring at the same time Square request bag parsing module is answered also to be supplied to responder to respond bag generation module some information of read-write requests bag；

3.3) read-write operation that local bus is written and read the resource of its lower carry required by request bag is extended, then will read to grasp The returned data of work or the complement mark of write operation are sent to responder and respond bag generation module；

3.4) responder responds bag generation module after the returned data or the complement mark of write operation for receiving read operation, according to The request package informatin that responder's request bag parsing module provides, constructs corresponding respond and wraps, be then sent to RapidIO IP The responder of Core responds packet interface；

3.5) RapidIO IP Core, will by physical layer high-speed differential signal after receiving the RapidIO to be sent and responding bag RapidIO responds bag and is sent in RapidIO buses；

3.6) exterior RapidIO equipment receives the response bag that this controller beams back by RapidIO buses, then completes it to this This time read-write requests of controller.

4. the RapidIO control methods according to claim 1 using window mapping mechanism, it is characterised in that：The side Formula 4) be specifically：

4.1) after exterior RapidIO equipment initiates doorbell/message request by RapidIO buses to this controller, RapidIO IP Core receive doorbell/message request in bus by physical layer high-speed differential signal, pass through responder after being decoded Request packet interface issues responder's request bag parsing module；

4.2) after responder's request bag parsing module receives doorbell/message request, the information for parsing doorbell/message is concurrent It is supplied to responder to respond bag generation toward doorbell/message control unit in expanded configuration space, while by the information of request bag Module；

4.3) responder responds doorbell/message request letter that bag generation module is provided according to responder's request bag parsing module Breath, constructs the corresponding responder's response packet interface responded bag, be then sent to RapidIO IP Core；

4.4) RapidIO IP Core, will by physical layer high-speed differential signal after receiving the RapidIO to be sent and responding bag RapidIO responds bag and is sent in RapidIO buses；

4.5) exterior RapidIO equipment receives the response bag that this controller beams back by RapidIO buses, then completes it to this This time doorbell/message request of controller；

4.6) doorbell/message control unit in expanded configuration space is put into after doorbell/message request package informatin is received Into corresponding register and message data buffering area, interrupt processing unit is then informed, interrupt processing unit is again to processor Send interruption；

4.7) processor reads received door after interruption is received from the doorbell/message related register in expanded configuration space Bell/message request information, then carries out corresponding processing operation according to these information.

5. the RapidIO control methods according to claim 1 using window mapping mechanism, it is characterised in that：The side Formula 5) be specifically：If mass data is sent to exterior RapidIO equipment from this controller, directed out by this controller Portion's RapidIO equipment carries out write operation, or these data to be sent first are write data exchange double port memory, Ran Houyou Exterior RapidIO equipment reads these data by RapidIO buses from the memory；If mass data from outside RapidIO equipment is sent to this controller, and directly read operation is carried out to exterior RapidIO equipment by this controller, or by outer These data are first write data exchange double port memory by portion's RapidIO equipment by RapidIO buses, then processing locality Device reads these data from the memory again.