CN115221070B

CN115221070B - NVMe disk-based system-on-chip diagnosis method

Info

Publication number: CN115221070B
Application number: CN202210923792.4A
Authority: CN
Inventors: 田建军; 刁永翔; 宫晓渊; 宋晓宁; 王欢
Original assignee: Wuxi Zhongxing Microsystem Technology Co ltd
Current assignee: Wuxi Zhongxing Microsystem Technology Co ltd
Priority date: 2022-08-02
Filing date: 2022-08-02
Publication date: 2023-06-20
Anticipated expiration: 2042-08-02
Also published as: CN115221070A

Abstract

The invention provides a system-on-chip diagnosis method based on an NVMe disk, which comprises the following steps: when receiving Trace data of a system on chip transmitted by a CoreSimight Trace network, writing the received Trace data into the DDR, and constructing an NVMe write disc command; issuing an NVMe write disc command to a PCIe control unit, and informing the NVMe disc to extract the write disc command, wherein the write disc command is used for moving Trace data in the DDR to the NVMe disc; after the NVMe disc extracts and executes the disc writing command, the command execution state is fed back to the system on chip. The method can meet the requirements of larger data bandwidth and higher transmission data rate when the CoreSimight Trace network is used for coping with complex systems such as CPU multiple cores, high frequency and the like and system problem diagnosis analysis scenes with multiple Trace data sources, ensure the integrity of on-chip data tracking, save on-chip memory resources, improve the capability of system analysis and diagnosis problems and save chip debugging cost.

Description

NVMe disk-based system-on-chip diagnosis method

Technical Field

The invention belongs to the field of chip debugging, and particularly relates to a system-on-chip diagnosis method based on an NVMe disk.

Background

In the chip debugging link, tracking of on-chip data and instructions is critical to the diagnosis of the system on chip. However, as the complexity of the chip system is higher and higher, it is difficult for the off-chip instrument to measure the on-chip data stream and the instruction stream during the processor debugging process, and a system problem that cannot be analyzed easily occurs. Therefore, the real-time tracking and observing problem of the running state of the processor needs to be solved at the cost of silicon area. More and more processor manufacturers are beginning to provide Trace-on-chip functions. The on-chip Trace system is designed through special hardware, information such as a program execution path, data reading and writing and the like is recorded in real time in a non-invasive mode, then effective information is compressed into Trace data streams, the Trace data streams are transmitted to a debugging host through a special data channel, and finally decompressed Trace data streams are received through an external receiving tool, and program running information is recovered to carry out system debugging and performance analysis.

Currently, the industry leading multi-core on-chip Trace solutions include CoreSight of ARM. CoreSight is an open architecture that SoC designers can add debug and trace functionality of other IP cores to CoreSight infrastructure. CoreSight includes various trace macro-units, system and software measurements of ARM processors and a complete set of IP blocks to debug and trace various complex multi-core socs. Trace paths are typically included in CoreFlight networks. The Trace path is used to output internal information of the CPU core, i.e., the processor core, to the outside. The Trace path of the CoreSight network can realize the data tracking function of the CPU core.

The Trace path of a typical CPU (4 cores) CoreSight network is shown in fig. 1. ETM (Embedded Trace Macrocell) is responsible for tracking the processor's information, packaging the information and sending it over the ATB Bus (AMBA Trace Bus) onto the Trace Bus. ATB data is sent to CoreSight ETB (Embedded Trace Buffer) and TPIU components (Trace Port Interface) by configuring CoreSight fuel and replier components on the Trace bus, and finally output off-chip. Each core of the CPU monitors it during operation by the respective ETM and outputs corresponding trace information in ATB format. The CoreSight fuel component outputs the received 4-way ATB data as 1-way ATB data by configuration and then sends the data to the CoreSight replicator component. CoreSight replicator component copies the received 1-way ATB data into 2-way data, which are sent to CoreSimight TPIU and CoreSimight ETB components, respectively. The CoreSight TPIU component transmits the received ATB data from the chip pin to the off-chip in a serial manner after internal processing. Wherein trace_out_clk is the output clock for sampling by an external tool; trace_ctrl and Trace_data are data to be sampled, and an external tool uses Trace_out_clk to perform double-edge sampling on the data to realize data receiving. And the CoreSight ETB component caches the received ATB data into its internal RAM for data reading by an external debug tool. The Trace path of the traditional CoreSight network can solve the problem of a more complex system by tracking the data of the internal CPU operation and outputting the data to the outside of the chip for system analysis.

However, as the level of chip manufacturing technology increases, CPUs are running at higher operating frequencies. To improve chip performance, more and more systems also require CPU multi-core parallel co-operation. The improvement of chip performance depends on the design of a system with high-frequency multi-core cooperative operation, and therefore, the complexity of the system is increased. In addition, many IP vendors other than CPUs support Trace output for enhancing their own debug functions. This results in the need to deal with more complex systems and more Trace data sources when designing Trace paths using CoreSight networks, since the CPU multiple cores are all running at high frequencies and other IPs, in addition to the CPU, generate Trace data. The Trace path of a conventional CoreSight network, when faced with such a scenario, typically suffers from the following drawbacks and deficiencies:

1) Insufficient data bandwidth

For the scenario that the Trace is performed by multiple cores of the CPU at the same time, because Trace data may be generated in each clock cycle of each core during the running period, and the Trace path is to merge and collect all Trace data sources into one path of data and output the path of data to the outside of the chip, a back pressure of a part of data links may occur due to insufficient bandwidth. If the ETM corresponding to a certain core is subjected to back pressure, the running information of the core cannot be captured and monitored normally and timely, so that a blind area exists in the data tracking process, and the system diagnosis and analysis are affected.

For Trace scenes with large data volume, trace data can only be output to the outside of the chip through the PAD by using the traditional CoreSimight architecture, and then the data is sampled, stored and analyzed by an external chip receiving tool. However, due to PAD clock frequency limitations and external receiving tool sampling frequency limitations using clock double-edge sampling, the Trace bandwidth on chip cannot be designed to be too large. The maximum Trace bandwidth in a conventional CoreSight network is 19.2Gbps.

According to the standard provided by ARM, if the CPU single core operating frequency is 1GHz, the Trace bandwidth needs to meet 4Gbps. If the CPU 4cores operates at a frequency of 1GHz, the trace bandwidth needs to meet 21Gbps. It can be seen that the Trace bandwidth requirement of 4cores operating frequency 1GHz cannot be met by the method of outputting Trace data through TPIU according to the above-described conventional CoreSight architecture.

2) On-chip data storage space is insufficient

CoreSight also supports temporary storage of Trace data in on-chip ETB RAM for reading by the debug tool. According to ARM, recommended standards are provided, and for a plurality of CPU cores, the ETB RAM is recommended to be correspondingly increased. For example, 8KB ETB for 2 CPU cores or 16KB for 4 CPU cores. However, since the ETB implementation uses a ring RAM, it can only be read by an external debug tool after Trace has stopped. Therefore, if Trace start time is long, the phenomenon that new data is covered by old data after the RAM is full exists, so that Trace data is lost. Especially for more complex system analysis, there is a scene that needs to be continuously tracked, and the generated data volume is more likely to be increased sharply due to the overlong system running time. The amount of Trace data may reach the GB order, resulting in loss of Trace data.

In addition, while the RAM provided by the ETB may be used to store the generated Trace data, the available space is determined by the memory size of the actual chip design. However, in the face of massive Trace data on the order of GB, it is not preferable to rely on a method of satisfying Trace data storage by increasing the memory size inside the chip, and the drastic increase in chip area and manufacturing cost is not acceptable.

3) Low data transmission rate

The Trace path of the traditional CoreSight network adopts a method of carrying out data capture and Trace data re-writing on the hard disk through an external receiving tool, is limited by the transmission rate of TPIU, is related to the type of the hard disk and has the maximum rate of 6Gbps if a SATA hard disk (gen 3) is used. If a SAS hard disk (gen 3) is used, the maximum rate is 12Gbps.

Taking the Trace bandwidth reaching the peak value of 19.2Gbps in the above design as an example, when multi-core complex system analysis is performed, the Trace data generation rate inside the whole chip may be fast, and the data writing rate into the hard disk is relatively slow, so that the external receiving tool cannot write into the hard disk space in time after receiving and capturing the Trace data of the chip, thereby causing the loss of the Trace data.

4) External reception tool use limitations

After the chip is produced, pins for debugging are not reserved in packaging in order to save packaging cost and consider system safety. Therefore, when the system problem diagnosis and analysis are needed after the chip is produced by adopting the Trace path method of the traditional CoreSimht network, the Trace data in the chip cannot be output outwards through the TPIU pins, so that the on-chip Trace data cannot be received by the method before the chip is produced, and the difficulty of the system problem diagnosis and analysis is increased.

5) External receiving tools are costly

In the chip debugging and testing stage, a plurality of debugging tools are generally required to be configured, so that the parallel development of chip debugging and testing is ensured, and the project delivery schedule is accelerated. Therefore, the external debugging tool supporting CoreFlight Trace data receiving is adopted as the debugging and testing tool of the chip, so that the input cost of chip debugging and testing can be obviously increased.

Disclosure of Invention

The invention aims to provide a system-on-chip diagnosis method based on an NVMe disk, which aims to solve the limitations of the system diagnosis method for outputting CPU internal information to the outside of a chip aiming at the traditional CoreSim Trace network and the defects of receiving and storing Trace data through an external receiving tool.

The NVMe disk-based system-on-chip diagnosis method comprises the following steps:

when receiving Trace data of a system on chip transmitted by a CoreSimight Trace network, writing the received Trace data into the DDR, and constructing an NVMe write disc command;

issuing the NVMe write disc command to a PCIe control unit, and informing an NVMe disc to extract the write disc command, wherein the write disc command is used for moving system-on-chip Trace data in the DDR to the NVMe disc;

after the NVMe disc extracts and executes the write disc command, a command execution state is fed back to the system on chip.

Preferably, the writing the received Trace data to the DDR further includes:

and receiving Trace data transmitted by the CoreSight replicator component through an NVMe Trace ctrl unit, and then controlling the received Trace data to be written into a DDR corresponding space by the NVMe Trace ctrl unit for caching.

Preferably, trace data transmitted by the CoreSight replicator component is program executed by an on-chip CPU and generated by configuring the ETM.

Preferably, the NVMe Trace ctrl unit is connected with an NVMe dispatch unit, the NVMe dispatch unit includes a commit queue SQ and a completion queue CQ, and the constructing an NVMe write disk command further includes:

and constructing the NVMe write disk command by utilizing the NVMe Trace ctrl unit, delivering the NVMe write disk command to a commit queue SQ of the NVMe dispatch unit, and recording the issued command ID.

Preferably, the NVMe dispatch unit and the DDR are respectively connected with a PCIe control unit through an AXI bus, and the PCIe control unit is connected with the NVMe disk through a PCIe link.

Preferably, the issuing the NVMe write disc command to the PCIe control unit informs the NVMe disc to extract the write disc command, and further includes:

and issuing command frame contents to the PCIe control unit through the NVMe dispatch unit, and communicating with the NVMe disk side controller through a PCIe link to inform the NVMe disk side controller to extract related commands from the SQ.

Preferably, the NVMe disc extracts and executes the write disc command, further comprising:

and the NVMe disk reads Trace data cached in the DDR through a PCIe control unit according to the write disk command, and then writes the Trace data into a corresponding space of the NVMe disk.

Preferably, the feeding back the command execution status to the system on chip further includes:

the NVMe disk writes the completion state of command execution into a completion queue CQ of the NVMe dispatch unit, and then notifies a chip to check the completion state of the command by sending interrupt information;

and returning a command execution result to the NVMe Trace ctrl unit through the NVMe dispatch unit, and carrying out corresponding processing operation by the NVMe Trace ctrl unit.

Preferably, the processing operation is command ID reclamation, event statistics, error logging or information reporting.

Preferably, the NVMe disc is an NVMe gen4 hard disc.

Compared with the prior art, the invention has the following advantages:

the method of the invention realizes the function of writing Trace data on a chip into an NVMe hard disk to perform system problem diagnosis analysis by adding NVMe Trace ctrl, NVMe dispatch, DDR and PCIe control units to the traditional CoreSim network and by controlling Trace data stream construction by hardware automation and dispatching NVMe commands and processing command execution return results, and provides a solution of the system on chip diagnosis method based on the NVMe disk. The method effectively solves the problems of insufficient Trace data bandwidth, insufficient on-chip data storage space, low data transmission rate, use limitation of external receiving tools and high cost of the external receiving tools in the traditional CoreSimight Trace network system diagnosis method, achieves the purpose of receiving and storing Trace data on chip at high speed, remarkably improves the capability of analyzing and diagnosing the problems of the system and saves the chip debugging cost.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will briefly explain the drawings required for the embodiments or the prior art description, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a Trace path schematic of a typical CoreSight network according to the prior art.

Fig. 2 shows a schematic diagram of an implementation architecture of a system-on-chip diagnostic method based on NVMe disk according to the present invention.

Fig. 3 shows a flow chart of an implementation of the NVMe disk-based system-on-chip diagnostic method according to the present invention.

Fig. 4 shows a control flow diagram of an NVMe disk-based system on chip diagnostic process according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In order to solve the problems in the background technology, the invention provides a system-on-chip diagnosis method based on an NVMe disk. On the basis of the traditional Coreweight network infrastructure, an NVMe track ctrl unit and an NVMe dispatch unit are added, on-chip tracking data is controlled to be written into the DDR cache and an NVMe move data command is automatically delivered, and finally, the purpose that massive on-chip tracking data are directly stored into an NVMe disk at high speed is achieved by using an NVMe PCIe link, so that the analysis capability of a system is enhanced.

NVMe (Non-Volatile Memory express) is a high performance, nonvolatile storage, memory access optimized, highly scalable storage protocol for interfacing hosts and storage subsystems. NVMe is specially designed for nonvolatile storage such as NAND, flash memory, etc., and can meet the requirements of high-speed storage media. An advantage of NVMe is that it can utilize parallel data paths, providing better performance in terms of acceleration. It enables existing applications and new applications to work more efficiently. NVMe improves read-write performance by approximately 6 times compared with AHCI (Advanced Host Controller Interface, an advanced host controller interface)/SATA, and improves read-write performance by 2-3 times compared with AHCI/PCIe SSD. In addition, the advantages of NVMe include low latency, low power consumption and high compatibility.

Fig. 2 shows a schematic diagram of an implementation architecture of a system-on-chip diagnostic method based on NVMe disk according to the present invention. The CoreSight network architecture of the present invention is composed of an invention unit and a standard IP unit, wherein the invention unit includes an NVMe Trace ctrl unit (NVMe Trace Data control unit) and an NVMe dispatch unit (NVMe command dispatch unit), and the standard IP unit includes a DDR (Double Data Rate) and a PCIe control unit. The NVMe Trace ctrl unit is connected to the output of the CoreSight replicator component. The NVMe Trace ctrl unit is further connected with the NVMe dispatch unit and the DDR through the AXI bus respectively. The NVMe dispatch unit further includes a commit queue SQ (Submission Queue) and a completion queue CQ (Completion Queue) for buffering write disk commands to be distributed and completed write disk commands, respectively. And the NVMe dispatch unit and the DDR are further connected with the PCIe control unit through the AXI bus respectively. The output of the PCIe control unit is connected to the NVMe disk through a PCIe link. In a preferred embodiment, the NVMe disc may employ an NVMe gen4 hard disk.

Unlike traditional structure with Coreweight ETB assembly, the invention receives Trace data in standard ATB format in Coreweight network through NVMe Trace ctrl unit, uses AXI bus to write the Trace data into DDR for buffering after processing, then delivers data moving command to NVMe dispatch unit, finally completes moving Trace data on chip to NVMe hard disk through PCIe link, thus realizing design structure of moving massive Trace data on chip of more complex system network to NVMe disk directly and high speed without using external receiving tool.

By adding NVMe Trace ctrl, NVMe dispatch, DDR and PCIe control units to the traditional CoreFlight Trace network, and executing the return results through hardware automation control Trace data stream construction, dispatch NVMe commands and processing commands as described below, a solution is achieved to write on-chip Trace data to an NVMe hard disk for system problem diagnostic analysis. The method of the invention can realize the purposes of unlimited size of Trace data on a receiving storage chip, no back pressure generated on source data in a high-speed transmission process and no blind area for tracing the data on the chip, improves the capability of system analysis and diagnosis and saves the chip debugging cost, thereby effectively overcoming various defects and shortages of data bandwidth, data storage space on the chip, data transmission rate and external receiving tool in the traditional CoreSimight Trace network system diagnosis method.

Fig. 3 shows a general flow chart of a system-on-chip diagnostic method based on NVMe disk according to the present invention. Based on the system-on-chip network architecture of fig. 2, the specific diagnostic flow of the system-on-chip of the present invention is as follows:

step 101: when receiving the system-on-chip Trace data transmitted by the CoreSimight Trace network, writing the received Trace data into the DDR, and constructing an NVMe write disc command.

In the control flow diagram of the NVMe disk-based system on chip diagnosis method described in connection with fig. 4 from the event point of view, in event T1, the CPU executes a program, generates corresponding Trace data by configuring the ETM, and transmits the data to the NVMe Trace ctrl unit using the CoreSight Trace network. Next, in event T2, the NVMe Trace ctrl unit writes the received Trace data control into the DDR corresponding space for caching. Meanwhile, in event T3, the NVMe track ctrl unit constructs an NVMe write disc command, delivers the write disc command to the SQ of the NVMe dispatch unit, and records the issued command ID. The process can continuously deliver a plurality of commands so as to exert the parallel processing capacity of the NVMe multi-queue and improve the transmission performance of the link.

Step 102: and issuing the NVMe write disc command to a PCIe control unit, and informing the NVMe disc to extract the write disc command, wherein the write disc command is used for moving the system-on-chip Trace data in the DDR to the NVMe disc.

Referring to fig. 4, in event T4, the NVMe dispatch unit performs SQ queue management and issues command frame contents to the PCIe control unit. Preferably, the PCIe control unit may select PCIe gen4. In event T5, the NVMe dispatch unit communicates with the NVMe disk side Controller (Controller) via the PCIe link, including issuing an SQ Tail DOorbell (to inform the NVMe disk side Controller to extract commands) and transferring data with the chip during command execution. And the method also comprises the step of issuing CQ Head Doppler of the updated NVMe disk side Controller so as to inform the NVMe disk side of processing Completion information. In event T6, after receiving the related message, the NVMe disk side Controller extracts the command from the SQ of the NVMe dispatch unit through the PCIe link and executes the command, and during executing the command, data transfer is performed with the chip. In event T7, the NVMe disk side reads Trace data of the DDR cache through the PCIe control unit, and then writes the Trace data into a corresponding space of the NVMe hard disk.

Step 103: after the NVMe disc extracts and executes the write disc command, a command execution state is fed back to the system on chip.

Referring to fig. 4, after the NVMe disk completes the reception of the command and data, in event T8, the NVMe disk side writes the completion status of the command execution to the CQ of the NVMe dispatch unit and then notifies the chip of checking the completion status of the command by transmitting interrupt information. Further, the NVMe dispatch unit returns a command execution result to the NVMe Trace ctrl unit, and the NVMe Trace ctrl unit carries out corresponding processing, including command ID recovery, event statistics, error recording and information reporting.

Those skilled in the art will appreciate that the components of the method steps and apparatus described in the above embodiments are by way of example only. Those skilled in the art can combine, add or delete or sequentially adjust the steps of the above-mentioned system-on-chip diagnosis method flow based on NVMe disk, or easily conceivable adjust the CoreSight Trace network architecture, as required. And the inventive concept should not be limited to the specific structures and flows of the examples described above.

The system-on-chip diagnosis method based on the NVMe disk can solve the defects of the traditional CoreFlight Trace network in dealing with more complex systems such as multiple cores, high frequencies and the like and system problem diagnosis analysis scenes with multiple Trace data sources, and is concretely as follows:

1) In terms of data bandwidth, the method of the present invention is adopted, since Trace data is directly written into the NVMe hard disk without using an external receiving tool. Therefore, the frequency of trace data in the chip is 1GHz, the data bit width is 32 bits, and the trace bandwidth can reach 32Gbps without being limited by the receiving capability of an external receiving tool. The output interface PCIe (gen 4) can reach 32Gbps by adopting a dual-channel physical speed. Therefore, the situation can be met, namely, the working frequency of the CPU 4cores is 1GHz, the Trace bandwidth needs to meet 21Gbps, the problem that the CPU ETM output is subjected to high probability back pressure due to insufficient Trace channel bandwidth is solved, and the effect of no blind area in CPU monitoring and tracking is achieved.

2) In the aspect of on-chip data storage space, the method of the invention does not use ETB components, but stores Trace data into an external NVMe hard disk after caching the Trace data through DDR, so that special on-chip memory is not needed to cache the Trace data, thereby saving on-chip memory resources. The external NVMe hard disk can generally accommodate hundreds of GB or even TB levels, so that the method can also normally receive and store the scene of processing massive Trace data. The method of the invention not only can support the receiving and storage of massive Trace data, but also saves the on-chip storage space resource and reduces the chip design and manufacturing cost.

3) In terms of data transmission rate, when the continuous output of the chip Trace is dealt with, the method adopts the NVMe gen4 hard disk, the transmission rate can reach 32Gbps, and the maximum transmission rate 21Gbps of Trace data with the CPU 4cores working frequency of 1GHz is met. The on-chip Trace data can be written into the corresponding hard disk space in time, so that the problem of low data transmission rate of the traditional CoreSimight Trace network is solved.

4) In the aspect of the application range of an external receiving tool, trace data is output to an external NVMe hard disk outside the chip through the original on-chip high-speed data channel interface by adopting the method of the invention, and a traditional debugging pin is not used any more, so that the influence of the pin for debugging is not reserved when the chip is packaged after being produced, and the application limitation caused by the fact that the traditional CoreSim Trace network needs to rely on the pin for debugging and the external receiving tool is solved.

5) In the aspect of the cost of an external receiving tool, the method of the invention does not depend on an external debugging tool supporting CoreSimight Trace data receiving any more, but only needs a common debugging tool with lower purchase cost, thereby greatly saving the input cost of chip debugging and testing tools.

Therefore, the method can effectively solve the requirements of larger data bandwidth and higher transmission data rate existing in the traditional CoreSimight Trace network when dealing with the diagnosis and analysis scene of the complex systems such as CPU multicore, high frequency and the like and the system problems with multiple Trace data sources. When dealing with a massive Trace data scene, the aim of timely receiving and storing data is achieved by means of a large-capacity storage space of an external NVMe hard disk, and the integrity of on-chip data tracking is guaranteed. Because the method of the invention does not use CoreFlight ETB assembly any more, the on-chip memory resource is saved, and the design and manufacturing cost is reduced. Because the external receiving tool is not relied on any more, the traditional Trace output pins of the chip can be saved, and the pin resources are saved. Because an external debugging tool supporting CoreSimight Trace data receiving with higher purchase cost is not needed, the cost of the chip debugging and testing tool is reduced. The method of the invention achieves the purposes of unlimited size of Trace data on the receiving storage chip, no back pressure generated on source data in the high-speed transmission process and no blind area for tracking the data on the chip, obviously improves the capability of system analysis and diagnosis problems and saves the chip debugging cost.

While the invention has been described in detail with reference to the foregoing embodiments, it will be appreciated by those skilled in the art that variations may be made in the techniques described in the foregoing embodiments, or equivalents may be substituted for elements thereof; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system-on-chip diagnostic method based on NVMe disk, comprising:

when receiving Trace data of a system on chip transmitted by a CoreSimghtTrace network, writing the received Trace data into the DDR, and constructing an NVMe write disc command;

issuing the NVMe write disc command to a PCIe control unit of the CoreSimight Trace network, informing an NVMe disc to extract the write disc command, wherein the write disc command is used for moving system on chip Trace data in the DDR to the NVMe disc through an on-chip data channel;

after the NVMe disk extracts and executes the disk writing command, feeding back a command execution state to a system on chip;

the writing the received Trace data into the DDR further comprises:

receiving Trace data transmitted by a CoreSight replicator component through an NVMe Trace ctrl unit, and then controlling the received Trace data to be written into a DDR corresponding space by the NVMe Trace ctrl unit for caching;

the NVMe Trace ctrl unit is connected with an NVMe dispatch unit, the NVMe dispatch unit comprises a commit queue SQ and a completion queue CQ, and the construction of the NVMe write disk command further comprises:

constructing the NVMe write disk command by utilizing the NVMe Trace ctrl unit, delivering the NVMe write disk command to a commit queue SQ of the NVMe dispatch unit, and recording the issued command ID;

an SQ Tail Doorbell message is issued to inform an NVMe disk side controller of extracting the command and carrying out data transfer with the chip during the command execution;

issuing a CQ Head Doorbell message to update the NVMe disk side controller to inform the NVMe disk side of completing the Completion of the processing;

the feedback of the command execution status to the system on chip further comprises:

2. The NVMe disk-based system on chip diagnostic method of claim 1, wherein Trace data transmitted by the coresight reflector component is generated by a CPU on chip executing a program and by configuring ETM.

3. The NVMe disk-based system on chip diagnostic method of claim 2, wherein the NVMe dispatch unit and DDR are respectively connected to a PCIe control unit through an AXI bus, and the PCIe control unit is connected to the NVMe disk through a PCIe link.

4. The NVMe disk-based system on a chip diagnostic method of claim 3, wherein issuing an NVMe write disk command to a PCIe control unit, informing an NVMe disk to extract the write disk command, further comprises:

5. The NVMe disk-based system on chip diagnostic method of claim 1, wherein the NVMe disk extracts and executes the write disk command, further comprising:

6. The NVMe disk-based system on chip diagnostic method of claim 4, wherein the processing operation is command ID reclamation, event statistics, error logging, or information reporting.

7. The NVMe disk-based system on chip diagnostic method of claim 1, wherein the NVMe disk is an NVMe gen4 hard disk.