CN115576258A - Vehicle chip system control method, system-on-chip and vehicle - Google Patents
Vehicle chip system control method, system-on-chip and vehicle Download PDFInfo
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Abstract
The present disclosure relates to a vehicle chip system control method, a system-on-chip and a vehicle, the method is applied to the system-on-chip, the system-on-chip includes a first core and a second core which are heterogeneous, a processing performance of the first core is greater than a processing performance of the second core, the method includes: the second core responds to the system level chip to be switched from the running state to the dormant state and informs the first core of first state switching information; the first core responds to the first state switching information and controls the application program to sleep; storing the calibration data and a sleep state identifier to a memory, wherein the sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on; the second core controls the power-off of the first core and controls the power supply module to supply power to the memory, and then the power-off of the second core is controlled, so that the system-on-chip is switched from the running state to the dormant state. The starting time of the heterogeneous system-on-chip can be effectively reduced.
Description
Technical Field
The present disclosure relates to the field of vehicle chips, and in particular, to a vehicle chip system control method, a system on chip, and a vehicle.
Background
In the related art, the overall starting process of the vehicle system-on-chip is long, and after each shutdown, the system-on-chip is restarted. The whole process is repeated once again, and at least 5-10 seconds are needed from the whole starting to the completion of the loading and running of the application program, so that the starting time of the existing automobile is longer, and the starting experience of the intelligent automobile is influenced.
Disclosure of Invention
In order to overcome the problems in the related art, the present disclosure provides a vehicle chip system control method, a system on chip and a vehicle.
According to a first aspect of the embodiments of the present disclosure, a vehicle chip system control method is provided, which is applied to a system-on-chip, where the system-on-chip includes a first core and a second core that are heterogeneous, and a processing performance of the first core is greater than a processing performance of the second core, and the method includes:
the second core responds to the system-on-chip to be switched from a running state to a dormant state and informs the first core of first state switching information;
the first core responds to the first state switching information and controls the application program to sleep; storing calibration data and a sleep state identifier to a memory, wherein the sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on;
and the second core controls the power-off of the second core after controlling the power-off of the first core and controlling the power module to supply power to the memory, so that the system-level chip is switched from the running state to the dormant state.
Optionally, the method comprises:
the second core responds to the system-level chip to be switched from a sleep state to a wake-up state, and controls the first core to be powered on;
the first core responds to power-on and detects whether the dormant state identification exists in the memory;
the first core, in response to determining that the sleep state identifier exists in the memory, performing a fast wake-up procedure based on the calibration data;
and the first core responds to the completion of awakening and informs the second core of successful awakening, so that the second core switches the dormant state to the running state.
Optionally, before the second core controls itself to power down, the method further comprises:
the second core configures a wake source, the wake source being one or more of: a real-time clock, an external device; the wake-up source is used for controlling the power module to supply power to the second core, so that the second core obtains data from a starting storage and completes initialization.
Optionally, the first core is a core of a Cortex-a hardware platform, in which an operating system is deployed; the second core is the core of the Cortex-M hardware platform, and the AutoSar component is deployed in the second core.
Optionally, the AutoSar component includes a power management master, the first core includes a power management slave, and the power management master is configured to manage a power state of the system-on-chip;
the second core notifying the first core of first state switching information in response to the system-on-chip switching from an operating state to a sleep state, comprising:
the second core responds to second state switching information sent by external equipment received by the AutoSar component, and determines that the system-level chip is switched from a running state to a dormant state;
the power management master of the second core notifies the power management slave to control the first state switching information.
Optionally, the controlling, by the first core, application program hibernation in response to the first state switching information includes:
the first core executes a program killing operation on the application program so as to end the process corresponding to the application program;
alternatively, before the first core responds to the first state switching information, the method includes:
the first core initiates an auto-sleep service;
the first core controls application program dormancy in response to the first state switching information, including:
and the first core responds to the first state switching information and starts a target sleep mechanism of the kernel of the operating system through the automatic sleep service so as to suspend the application program to a memory.
Optionally, the first core performs a fast wake-up procedure, including:
and skipping a data loading stage and an initialization stage by the first core, and skipping to a data pointer corresponding to the calibration data in the memory to realize quick awakening.
Optionally, the system-on-chip includes a register and a sleep memory, and the system-on-chip is further in communication with the main memory chip;
the storing calibration data and the sleep state identification to the memory comprises:
storing the calibration data to any one of: registers, sleep memory or main memory chips;
storing the sleep state identification to the sleep memory;
the control power module supplies power to the memory, and comprises:
controlling the power module to supply power to the main memory chip, the hibernation memory, and the register storing the calibration data, the hibernation memory, or the main memory chip.
According to a second aspect of the embodiments of the present disclosure, there is provided a system-on-chip, the system-on-chip including a first core and a second core that are heterogeneous, a processing performance of the first core being greater than a processing performance of the second core, the method including:
the second core responds to the system-on-chip to be switched from a running state to a dormant state and informs the first core of first state switching information;
the first core responds to the first state switching information and controls the dormancy of the application program; storing calibration data and a sleep state identifier to a memory, wherein the sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on;
and the second core controls the second core to power down after controlling the first core to power down and controlling a power supply module to supply power to the memory, so that the system-level chip is switched from a running state to a dormant state.
According to a third aspect of embodiments of the present disclosure, there is provided a vehicle comprising the system on chip of the second aspect of the present disclosure.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects: the system-on-chip power-off control method has the advantages that the second core informs the first core to store the calibration data and the dormant state identification in the memory when the system-on-chip is switched to the dormant state, then the first core is controlled to power off and keeps the power of the memory to be powered off, and then the system-on-chip can be switched to the dormant state from the running state, so that the power consumption of the system-on-chip can be reduced, the system-on-chip can be enabled to be awakened quickly, the starting time of the heterogeneous system-on-chip is effectively shortened, the automobile starting speed is increased, and the driving experience of a user is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a flow chart illustrating a vehicle system-on-chip control method according to one exemplary embodiment.
FIG. 2 is a schematic diagram of a system-on-chip shown in accordance with an example embodiment.
FIG. 3 is a schematic diagram of a system-on-chip shown in accordance with an example embodiment.
FIG. 4 is a block diagram of a vehicle shown in an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the disclosure, as detailed in the appended claims.
It should be noted that all actions of acquiring signals, information or data in the present application are performed under the premise of complying with the corresponding data protection regulation policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
In order to make those skilled in the art understand the improvement of the technical solution provided by the present disclosure, the present disclosure first introduces a multi-core heterogeneous chip start-up procedure and a power supply situation in the related art.
In the related art, an SOC (System on Chip, or System on Chip) is started from reset, and then a general loader, such as Bootloader, loads code from a Chip that is powered off and can store content, such as Flash, to an SRAM (memory Chip in SOC, speed block, but small capacity). Then, two types of processors on the SOC chip are started (M core: M core, which has weaker performance but low power consumption and generally runs an embedded real-time operating system, A core: A core, which has stronger performance but high power consumption and generally runs a large operating system such as Linux).
The SOC may include three power managed state machines, running (running), waking (standby), and shutdown (shutdown). The M core may control the power state of the entire chip by managing the power management state machine, for example, in response to the power management state machine switching to the wake state, the a core may be controlled to start. During the starting process of the core a, an ATF (ARM Trusted Firmware) starting process, a core loading process, an application program initialization process, and a memory operation process may be sequentially included. Wherein, the ATF is an underlying open source firmware code given for the ARM chip.
In the related art, the overall starting process of the vehicle system-on-chip is long, and the system-on-chip is restarted after each shutdown. The whole process is repeated once again, and about 5-10 seconds are needed from the whole starting to the completion of the loading and running of the application program, so that the starting time of the existing automobile is longer, and the starting experience of the intelligent automobile is influenced.
In order to solve the problems in the related art, the present disclosure provides a vehicle chip system control method, a chip, and a vehicle.
Fig. 1 is a diagram illustrating a vehicle Chip System control method applied to a System On Chip (SOC), which may also be referred to as a System On Chip (SOC), according to an exemplary embodiment, where the SOC includes a first core and a second core, and a processing performance of the first core is greater than a processing performance of the second core, as shown in fig. 1, and the method includes:
s101, the second core responds to the fact that the system-on-chip is switched from the running state to the dormant state, and the first core is informed of first state switching information.
It should be noted that the system-on-chip may include a plurality of first cores of the same hardware platform and a plurality of second cores of the same hardware platform, and the first cores and the second cores referred to in the embodiments of the present disclosure may be any one of the plurality of first cores and the plurality of second cores, or the plurality of first cores and the plurality of second cores may be collectively referred to as the first cores and the second cores.
It should be noted that, before the step S101 is executed, the sleep state (suspend) may be configured in advance in addition to the running (running), waking (standby), and stopping (shutdown) of the power management state machines, so that the second core can execute the subsequent steps based on the power management state machine corresponding to the sleep state. For example, the first state switching information may be the power management state machine, and for example, when the power management state machine is characterized as a sleep state, the first state switching information may be used to inform the first core that the system on chip is to be switched from a running state to the sleep state.
The system-on-chip may determine to switch from the operating state to the sleep state in response to other external devices or other program instructions, which is not limited in this disclosure. Furthermore, the first core and the second core may be information interaction through inter-core communication, such as: an Inter-Platform Communication Framework (IPCF) can support application programs located on the same chip or different chips, run on multiple isomorphic or heterogeneous processing cores, and communicate through various transmission interfaces such as a shared memory and other modes; alternatively, the Inter-Process Communication (IPC) may be a Communication bus between CPU (central processing unit) cores, and may enable information exchange between different processors.
S102, the first core responds to the first state switching information and controls the application program to sleep; and storing the calibration data and the sleep state identifier into the memory.
The sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on.
In some possible embodiments, the first core performs a fast wake-up procedure, including: and skipping a data loading stage and an initialization stage by the first core, and skipping to a data pointer corresponding to the calibration data in the memory to realize quick awakening.
In the method, jumping to a Memory, for example, a Data pointer corresponding to calibration Data in a DDR (Double Data Rate Dynamic Random Access Memory, DDRSRAM, double-Rate Synchronous Dynamic Random Access Memory), may enable the first core to directly obtain Data from a location corresponding to the Data pointer, without searching for Data from an external Memory, thereby enabling fast wake-up.
And S103, after controlling the first core to power off and controlling the power supply module to supply power to the memory, the second core controls the second core to power off so as to switch the system-level chip from the running state to the dormant state.
The Power module may be a Power Management Integrated Circuit (PMIC) that the system on chip is connected to, the Power Management integrated circuit may be respectively connected to the first core, the second core, and each of the memory units, and the Power Management integrated circuit may at least receive a control instruction sent by the second core to start or stop supplying Power to each of the units in the system on chip.
In some optional embodiments, the system-on-chip comprises a register and a hibernate memory (StandbyRAM), the system-on-chip further in communication with a main memory chip (DDR);
the storing calibration data and the sleep state identification to the memory comprises:
storing the calibration data to any one of: a register, a sleep memory, or a main memory chip;
storing the sleep state identification to the sleep memory;
the control power module supplies power to the memory, and comprises:
controlling the power module to supply power to the main memory chip, the hibernation memory, and the register storing the calibration data, the hibernation memory, or the main memory chip.
That is, controlling the power module to supply power to the memory may refer to maintaining power to the memory storing the sleep state identification, the memory storing the calibration data, and the main memory chip, so that these devices can self-refresh to maintain the data stored therein.
Where the hibernate memory may be a dynamic random access memory identified as StandbyRAM. The system-on-chip may further include a Static Random Access Memory (SRAM), and may also communicate with an external nonvolatile memory such as an EMMC (Embedded Multi Media Card), a boot memory such as Norflash, and the like, respectively. Upon determining that the system-on-chip will sleep, the static random access memory, such as SRAM, may be powered down directly.
In one possible embodiment, calibration data may be stored in the hibernation memory along with the hibernation-state identification; in another possible embodiment, the calibration data may be stored in the main memory chip, and the hibernation status flag may be stored in the hibernation memory, which is not limited in this disclosure.
It can be understood that after the power of the memory is cut off, the data stored on the memory is deleted, and the power supply of the memory is maintained to ensure the self-refresh of the memory, so that the data required by the quick wake-up process is reserved.
In the embodiment of the disclosure, after the second core notifies the first core to store the calibration data and the dormant state identifier to the memory when the system-on-chip is switched to the dormant state, the first core is controlled to be powered off and the power of the memory is kept powered off, so that the system-on-chip is switched from the running state to the dormant state.
In some optional embodiments, the method comprises:
the second core controls the first core to be powered on in response to the system-on-chip switching from a sleep state to a wake state; the first core responds to power-on and detects whether the dormant state identification exists in the memory; the first core, in response to determining that the sleep state identifier exists in the memory, performs a fast wake-up procedure based on the calibration data; and the first core responds to the completion of the awakening and informs the second core of the successful awakening, so that the second core is switched from the dormant state to the running state.
It will be appreciated that the above steps may be performed after the second core is powered up and full initialization is complete, and whether the second core is powered up may be controlled by a real time clock and/or signals sent by external devices.
In one embodiment, the second core may be a system on chip, and when determining to switch from the sleep state to the wake state in response to other external devices or other program instructions, such as a real-time clock, the other external devices or other program instructions control the power module to power on the second core.
In another embodiment, after controlling the first core to power on, the second core may further notify the first core of a power management state machine maintained by the second core, so that the first core detects whether a sleep state identifier exists in the memory and executes the subsequent steps when the power management state machine is characterized as an awake state. In addition, the first core detects whether the sleep status flag exists in the memory, which may be executed when the ATF boot procedure is executed.
By adopting the scheme, the first core is controlled to be powered on when the system-level chip is switched to the awakening state through the second core, the first core executes the quick awakening process based on the calibration data in the memory and the dormancy state identification, and the second core is informed after the awakening is completed, so that the system-level chip can be switched to the running state from the dormancy state, the system-level chip can be ensured to be awakened quickly, the starting time of the heterogeneous system-level chip is effectively shortened, the automobile starting speed is improved, and the driving experience of a user is improved.
In some optional embodiments, the first core is a core of a Cortex-A hardware platform, in which an operating system is deployed; the second core is the core of the Cortex-M hardware platform, wherein the AutoSar component is deployed.
The operating system may be a Linux system or a Unix, the AutoSar component may be an AutoSar AP component or an AutoSar CP component, and the disclosure does not specifically limit this.
In other possible embodiments, the first core and the second core may be cores of other hardware platforms, for example, cores of x86 hardware platforms.
Optionally, the AutoSar component includes a power management master (powermanagermatter), the first core includes a power management slave (powermanageslave), and the power management master is configured to manage a power state of the system-on-chip;
the second core notifying the first core of first state switching information in response to the system-on-chip switching from an operating state to a sleep state, comprising: the second core responds to second state switching information sent by external equipment received by the AutoSar component, and determines that the system-level chip is switched from a running state to a dormant state; the power management master of the second core notifies the power management slave of the first state switching information.
It is understood that the power states include at least an active state, a wake state, and a sleep state. In some possible embodiments, a shutdown state may also be included.
The second state switching information sent by the external device and received by the AutoSar component may be the second state switching information received by the service provided by the AutoSar component to another chip or another device through the vehicle-mounted ethernet, and the second state switching information may be received in the form of a service parameter.
In addition, the power management master and the power management slave may be processes running in corresponding cores, respectively, and may perform information interaction through inter-core communication, and may be configured to maintain the power management state machine. Further, the power management slave may be a process corresponding to an application program executed by the first core.
For example, the power management master notifies the power management slave of the first state switching information, which may be a power management state machine that the power management master notifies the power management slave of its management through inter-core communication.
By adopting the scheme, the power management slave control and the power management master control are respectively arranged on the first core and the second core, and the synchronization of the power management states between the first core and the second core is realized by utilizing the communication of the power management slave control and the power management master control, so that the first core can be reliably controlled by the second core, the system-level chip is switched from the running state to the dormant state, the starting time of the heterogeneous system-level chip is reliably reduced, and the starting time of the automobile is prolonged.
The first core control application program hibernation in step S102 can be implemented in the following two alternative embodiments.
In an optional embodiment, the first core controls application program hibernation in response to the first state switching information, including: and the first core executes a process killing operation on the application program so as to end the process corresponding to the application program.
It will be appreciated that the application described above may include a plurality of applications. The execution of the process killing operation may be implemented by a preset mechanism of a system kernel in the first core, or may be implemented by an application program, a process corresponding to the application program may be referred to as an executor, and the executor may execute self-closing after executing the process killing operation to close all other processes, thereby terminating processes corresponding to all application programs run by the first core.
By adopting the mode, all processes can be restarted when the first core is awakened, redundant data of the processes can be cleared, and system resources can be saved.
In another optional embodiment, before the first core responds to the first state switching information, the method comprises: the first core initiates an auto-sleep service;
the first core controls application program dormancy in response to the first state switching information, including:
and the first core responds to the first state switching information and starts a target sleep mechanism of the kernel of the operating system through the automatic sleep service so as to suspend the application program to a memory.
That is, the auto-hibernate service may be configured to initiate a target hibernate mechanism of the operating system kernel to suspend the application to memory in response to the first core receiving the first state transition information.
In a possible implementation manner, after the first core receives the first state switching information, if the automatic sleep service does not monitor voting information sent by other threads within a preset time period, it may be determined that a target sleep mechanism of the operating system kernel is started to suspend the application program to the memory.
The suspending the application program to the memory may specifically mean storing data of the application program in the main memory chip.
For example, the target hibernation mechanism may be a WakeUP Count mechanism of a Linux kernel, or may be any other system kernel mechanism capable of implementing retention of application data, which is not limited by the present disclosure.
By adopting the mode, compared with the mode of killing the program, the time required by the first core to wake up can be further reduced by reserving the application program in the memory, and the speed of switching the system level chip from the dormant state to the wake-up state is improved.
In some optional embodiments, before the second core controls itself to power down, the method further comprises:
the second core configures a wake source, the wake source being one or more of: a real-time clock, an external device; the wake-up source is used for controlling the power module to supply power to the second core, so that the second core obtains data from a starting storage and completes initialization.
For example, when the real-time clock determines that the system-on-chip is woken up at the current moment, the real-time clock may send a target signal to the PMIC, and the PMIC responds to the target signal and supplies power to the second core, so that the second core obtains data required by the start-up of the second core from a start-up memory such as Norflash, completes initialization of the AutoSar component, further causes the second core to inform the first core, and causes the first core to start up.
In another possible implementation, the second core may move the configured wake source from the AutoSar device driver to the bootloader, and the system on chip may control the second core to power up in response to the signal of the wake source, so that the second core determines that the system on chip will switch from the sleep state to the wake state.
By adopting the scheme, the second core is configured with the awakening source before powering off, so that the second core can acquire data from the boot storage based on the awakening source and complete initialization to ensure the stability of AutoSar, the first core is further started, the awakening of a system level chip can be reliably realized, and the interference of signals of other non-awakening sources is avoided.
Based on the same inventive concept, the present disclosure also provides a schematic diagram of a system-on-chip 200 as shown in fig. 2, where the system-on-chip 200 includes a first core 210 and a second core 220 that are heterogeneous, a processing performance of the first core 210 is greater than a processing performance of the second core 220,
the second core 220 is configured to notify the first core 210 of first state switching information in response to the system on chip 200 being switched from an operating state to a sleep state;
the first core 210 is configured to control an application to sleep in response to the first state switching information; storing calibration data and a sleep state flag to a memory, wherein the sleep state flag is used for instructing the first core 210 to execute a fast wake-up process based on the calibration data when the first core is powered on;
the second core 220 is configured to control the power down of the second core after controlling the power down of the first core 210 and controlling the power module to supply power to the memory, so as to complete the switching of the system on chip 200 from the operating state to the sleep state.
Optionally, the second core 220 is configured to control the first core 210 to power up in response to the system on chip 200 switching from a sleep state to a wake state;
the first core 210 is configured to detect whether the dormant state flag exists in the memory in response to power-up;
the first core 210 is configured to perform a fast wake-up procedure based on the calibration data in response to determining that the sleep state flag exists in the memory;
the first core 210 is configured to notify the second core 220 that the wake-up is successful in response to the wake-up completion, so that the second core 220 switches the sleep state to the running state.
Optionally, the first core 210 is a core of a Cortex-a hardware platform, in which an operating system is deployed; the second core 220 is the core of the Cortex-M hardware platform, in which the AutoSar component is deployed.
Optionally, the AutoSar component includes a power management master, and the first core 210 includes a power management slave, where the power management master is configured to manage a power state of the system-on-chip 200;
the second core 220 is configured to notify the first core 210 of first state switching information in response to the system on chip 200 switching from the operating state to the sleep state, including:
the second core 220 is configured to determine that the system on chip 200 is to be switched from the operating state to the sleep state in response to the AutoSar component receiving second state switching information sent by an external device;
the power management master of the second core 220 is configured to notify the power management slave of the first state switching information.
Optionally, the first core 210 is configured to perform a process killing operation on the application program, so as to end a process corresponding to the application program;
alternatively, the first core 210 is configured to start an auto-sleep service;
the first core 210 is configured to, in response to the first state switching information, start a target hibernation mechanism of the operating system kernel through the auto-hibernation service to suspend the application program to the memory.
Optionally, the second core 220 is configured to configure a wake source, the wake source being one or more of: a real-time clock, an external device; the wake-up source is used for controlling the power module to supply power to the second core, so that the second core obtains data from a starting storage and completes initialization.
Optionally, the first core 210 is configured to skip a data loading stage and an initialization stage, and jump to a data pointer in the memory corresponding to the calibration data to implement fast wake-up.
Optionally, the system on chip 200 includes a register, a dynamic random access memory, and a static random access memory, and the system on chip 200 further communicates with the main memory chip; the memory comprises the main memory chip and/or any one of the following: the register, the dynamic random access memory and the static random access memory.
In order to make the technical solution provided by the present disclosure more understandable to those skilled in the art, the present disclosure also provides a schematic diagram of a system-level chip as shown in fig. 3.
As shown in fig. 3, the SOC includes an a core, an M core, an SRAM, and a StandbyRAM, wherein the a core is a core of the Cortex-a hardware platform, the M core is a core of the Cortex-M hardware platform, the a core, the M core, the SRAM, and the StandbyRAM are all powered by PMICs, the M core is further connected to the PMICs through an I2C (Inter-Integrated Circuit) bus, and the PMICs are further respectively powered by DDR, EMMC, and Norflash. It is to be understood that, for convenience of viewing, partial connection relationships are not shown in fig. 3, for example, the a core and the M core may also have connection relationships with respective storage media, communication connection relationships of inter-core communication between the a core and the M core, and the like. In some optional embodiments, the system on chip SOC may further include a register.
The core A can be deployed with a Linux system, the core M can be deployed with an AutoSar AP component, the AutoSar AP component can comprise a power management master control, the core A can run with a power management slave control, the power management master control can carry out inter-core communication with the power management slave control, and then the core M can inform the core A of a power management state machine managed by the power management master control based on the inter-core communication, so that the core A can carry out a sleeping or awakening process. For example, when the M-core receives a power management state machine switching command sent by an external device through the AutoSar AP component, the M-core may change the power management state machine, and notify the a-core of the changed power management state machine through inter-core communication.
The power management state machine may be configured to manage 4 power management states of the system-on-chip, which are an operating state, a wake-up state, a sleep state, and a shutdown state. The wake-up state may be switched to an operational state, which may be switched to a sleep state or a shutdown state, which may be switched to a shutdown state or a wake-up state.
If the core A determines that the power management state machine notified by the core M is switched from the running state to the dormant state, the calibration data and the dormant state identifier can be stored in the StandbyRAM, and the core M can determine to reserve the power supply of the DDR and the StandbyRAM, configure a wake-up source and control all other elements in the system-level chip to be powered down including the power-down source after determining that the storage is completed.
The wake-up source can send a target signal to the PMIC when the system-on-chip is determined to need to be woken up, so that the PMIC supplies power to the M core, and after the M core is powered on, the M core acquires data required by initialization from the Norflash and completes initialization.
After the initialization of the M core is completed, and the fact that the system level chip is switched from the sleep state to the wake-up state is determined, the A core can be controlled to be powered on, so that the A core can check whether a sleep state identifier exists in the query StandbyRAM, and when the sleep state identifier exists, calibration data is obtained, corresponding data in the DDR is obtained according to the calibration data to achieve fast wake-up, and after the wake-up is successful, the M core is informed through inter-core communication to enable the M core to switch the wake-up state of the power management state machine to the running state.
In the embodiment of the disclosure, the AutoSar service of the M core is started quickly, so that the normal power down and complete restart can be performed, and thus the stability of the AutoSar can be greatly ensured. The part A of the core has large data volume and long loading time, so that the dormancy and the quick awakening can be realized through the scheme, the repeated loading is effectively avoided, the starting time of the heterogeneous system-level chip is effectively reduced, the automobile starting speed is improved, and the driving experience of a user is improved.
FIG. 4 is a block diagram illustrating a vehicle 400 according to an exemplary embodiment. For example, the vehicle 400 may be a hybrid vehicle, a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other type of vehicle. Vehicle 400 may be an autonomous vehicle, a semi-autonomous vehicle, or a non-autonomous vehicle.
Referring to fig. 4, a vehicle 400 may include various subsystems, such as an infotainment system 410, a perception system 420, a decision control system 430, a drive system 440, and a system-on-chip 200. The vehicle 400 may also include more or fewer subsystems, and each subsystem may include multiple components, among others. In addition, the interconnection between each subsystem and each component of the vehicle 400 may be achieved by wire or wirelessly.
In some embodiments, infotainment system 410 may include a communication system, an entertainment system, a navigation system, and the like.
The sensing system 420 may include several sensors for sensing information about the environment surrounding the vehicle 400. For example, the sensing system 420 may include a global positioning system (the global positioning system may be a GPS system, a beidou system, or other positioning system), an Inertial Measurement Unit (IMU), a laser radar, a millimeter-wave radar, an ultrasonic radar, and a camera.
The decision control system 430 may include a computing system, a vehicle control unit, a steering system, a throttle, and a braking system.
The drive system 440 may include components that provide powered motion to the vehicle 400. In one embodiment, the drive system 440 may include an engine, an energy source, a transmission system, and wheels. The engine may be one or a combination of more of an internal combustion engine, an electric motor, and an air compression engine. The engine is capable of converting energy provided by the energy source into mechanical energy.
Some or all of the functions of the vehicle 400 are controlled by the system-on-chip 200. The system-on-chip 200 may include at least one first core 210 and a second core 220, and in the embodiment of the present disclosure, the first core 210 and the second core 220 may be configured to execute prestored executable instructions to complete all or part of the steps of the above-described vehicle chip system control method.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A vehicle chip system control method is applied to a system-on-chip (SOC), wherein the SOC comprises a first core and a second core which are heterogeneous, and the processing performance of the first core is greater than that of the second core, and the method comprises the following steps:
the second core responds to the system-on-chip to be switched from a running state to a dormant state and informs the first core of first state switching information;
the first core responds to the first state switching information and controls the application program to sleep; storing calibration data and a sleep state identifier to a memory, wherein the sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on;
and the second core controls the power-off of the second core after controlling the power-off of the first core and controlling the power module to supply power to the memory, so that the system-level chip is switched from the running state to the dormant state.
2. The method according to claim 1, characterized in that it comprises:
the second core controls the first core to be powered on in response to the system-on-chip switching from a sleep state to a wake state;
the first core responds to power-on and detects whether the dormant state identifier exists in the memory;
the first core, in response to determining that the sleep state identifier exists in the memory, performs a fast wake-up procedure based on the calibration data;
and the first core responds to the completion of the awakening and informs the second core of the successful awakening, so that the second core is switched from the dormant state to the running state.
3. The method according to claim 1 or 2, wherein before the second core controls itself to power down, the method further comprises:
the second core configures a wake source, the wake source being one or more of: real-time clock, external device; the wake-up source is used for controlling the power module to supply power to the second core, so that the second core obtains data from a starting storage and completes initialization.
4. The method of claim 1 or 2, wherein the first core is a core of a Cortex-a hardware platform, in which an operating system is deployed; the second core is the core of the Cortex-M hardware platform, and the AutoSar component is deployed in the second core.
5. The method of claim 4, wherein the AutoSar component comprises a power management master, the first core comprises a power management slave, and the power management master is configured to manage a power state of the system-on-chip;
the second core responds to the system-on-chip to switch from the running state to the dormant state, and informs the first core of first state switching information, wherein the first state switching information comprises:
the second core responds to second state switching information sent by external equipment received by the AutoSar component, and determines that the system-level chip is switched from a running state to a dormant state;
the power management master of the second core notifies the power management slave of the first state switching information.
6. The method of claim 4, wherein the first core controls application dormancy in response to the first state switch information, comprising:
the first core executes a process killing operation on the application program so as to end the process corresponding to the application program;
alternatively, before the first core responds to the first state switching information, the method includes:
the first core initiates an auto-sleep service;
the first core responds to the first state switching information and controls the application program to sleep, and the method comprises the following steps:
and the first core responds to the first state switching information and starts a target sleep mechanism of the kernel of the operating system through the automatic sleep service so as to suspend the application program to a memory.
7. The method of claim 1 or 2, wherein the first core performs a fast wake-up procedure comprising:
and skipping a data loading stage and an initialization stage by the first core, and skipping to a data pointer corresponding to the calibration data in the memory to realize quick awakening.
8. The method according to claim 1 or 2, wherein the system-on-chip comprises registers and a sleep memory, the system-on-chip further communicating with a main memory chip;
the first core stores calibration data and a sleep state flag to a memory, including:
the first core stores the calibration data to any one of: a register, a sleep memory, or a main memory chip; and the number of the first and second antennas is increased,
storing the sleep state identification to the sleep memory;
the second core control power supply module supplies power to the memory, and comprises:
the second core controls the power module to supply power to the main memory chip, the sleep memory, and the register storing the calibration data, the sleep memory, or the main memory chip.
9. A system-on-chip comprising a first core and a second core that are heterogeneous, the processing performance of the first core being greater than the processing performance of the second core;
the second core is used for responding to the system-on-chip to be switched from the running state to the dormant state and informing the first core of first state switching information;
the first core is used for responding to the first state switching information and controlling an application program to sleep; storing calibration data and a sleep state identifier to a memory, wherein the sleep state identifier is used for indicating the first core to execute a quick wake-up process based on the calibration data when the first core is powered on;
the second core is used for controlling the power-off of the first core and controlling the power supply module to supply power to the memory, and then the power-off of the second core is controlled so as to switch the system-level chip from the running state to the dormant state.
10. A vehicle, characterized in that the vehicle comprises a system-on-chip according to claim 9.
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