CN114090498B - Method for realizing multi-core starting and service mutual decoupling of embedded SOC (system on chip) system - Google Patents
Method for realizing multi-core starting and service mutual decoupling of embedded SOC (system on chip) system Download PDFInfo
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Abstract
The application discloses a method for realizing the mutual decoupling of multi-core starting and service of an embedded SOC (system on chip) system, which realizes the independent starting among a plurality of cores and the mutual independence of service configuration by adopting a multi-core processor on an intelligent sensing terminal and adopting an AMP (application program) architecture, so that the mutual decoupling among the multi-core systems is realized, and the stability and the reliability of the intelligent sensing terminal are improved; the multi-core is started relatively independently, the real-time core operates on the main core, and when the management core operates abnormally, the service logic of the real-time core is not affected, so that the reliability of the intelligent perception terminal is improved.
Description
Technical Field
The application relates to the field of embedded technology, in particular to a method for realizing the mutual decoupling of multi-core starting and services by an embedded System On Chip (SOC).
Background
With the continuous development of modern embedded technology, the intelligent perception terminal based on the multi-core processor can realize high-speed processing and data calculation by one or more real-time cores, and one management core is responsible for managing data and files. The main architecture of the multi-core CPU at present comprises three operation modes of SMP, AMP and BMP, wherein the symmetrical multi-processing SMP architecture is used for managing each core equally through an operating system; whereas a hybrid multiprocessing BMP architecture is similar to an SMP architecture, a developer may specify that a certain task be executed only on a certain specified kernel; the asymmetric multiprocessing AMP architecture runs different tasks through a plurality of cores relatively independently, each core can be respectively loaded with and run different operating systems or bare core programs, but one core is needed to be used as a main core to control the whole system and other cores, and the cores are orderly started and are not interfered with each other, so that the asymmetric multiprocessing AMP architecture has higher energy efficiency.
However, the starting modes of the processors adopted by the multi-core architecture are all modes of guiding the slave cores by the master core, the slave cores can be awakened to be started after the master core is started, so that the coupling between the multi-core processors is higher, meanwhile, due to the fact that certain coupling relation exists between service data of the intelligent sensing terminal, the service data are required to be kept consistent, once the management cores are halted, abnormally reset and the like, the real-time cores cannot be loaded or abnormally restarted, normal protection logic is greatly influenced, and the problems of refusal of operation and misoperation and the like are caused.
Disclosure of Invention
The application provides a method for realizing the mutual decoupling of multi-core starting and business by an embedded SOC system, which aims to solve the problem of unreasonable distribution caused by personnel selection depending on subjective intention of people in the prior art.
The application provides a method for realizing the mutual decoupling of multi-core starting and service of an embedded SOC (system on a chip) system, which is applied to an AMP (analog-to-digital) framework formed by a service module, a real-time core module, a management core module and a shared memory module, wherein the real-time core module comprises a plurality of real-time cores and comprises the following steps:
building a multi-core system corresponding to an AMP architecture;
in a multi-core system, dividing a shared memory into ARM cores corresponding to each real-time core according to a plurality of real-time cores; the ARM core comprises a main core ARM core0 and slave cores ARM cores 1-N;
dividing a main partition of a system external memory into core 0-N programs for each ARM core to execute;
loading an FSBL program to an internal RAM area of the ARM core0 of the main core according to Bootrom, and jumping to an FSBL execution address;
initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses;
writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby;
the main core executes starting operation according to the SEV instruction;
writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby;
the slave core executes a starting operation according to the SEV instruction;
the management core starts to boot and load the operating system, initializes the operating system kernel, executes task scheduling and related service parameter initialization, and manages service data and files of each real-time core.
In some embodiments, the step of the master core performing a boot operation according to an SEV instruction includes:
jumping to the written address execution program;
initializing resources;
setting a stack pointer;
main ()'s running core 0;
initializing a platform;
initializing service parameters;
core0 service logic is entered.
In some embodiments, the step of the slave core performing a boot operation according to an SEV instruction includes:
detecting whether the fixed address value is 0;
if not, jumping to the written address execution program;
initializing resources;
setting a stack pointer;
run core1, 2..n-1 or main of N ();
initializing a platform;
initializing service parameters;
core1, 2,..n-1 or N business logic.
In some embodiments, if the fixed address value is 0, the step of detecting whether the fixed address value is 0 is performed again.
In some embodiments, after building the multi-core system corresponding to the AMP architecture, the method further includes:
and designating a stack memory corresponding to each real-time core.
In some embodiments, the method further comprises:
and the service modules complete data interaction through corresponding ARM cores in the shared memory.
In some embodiments, when the management core performs data updates according to the update configuration information, the self configuration updates are synchronized to the respective real-time cores.
In some embodiments, the multi-core system includes a master verification time system, a slave core embedded real-time system, and a bare core system; wherein the master verification time system is configured to perform the steps of:
initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses;
writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby;
the main core executes starting operation according to the SEV instruction;
the slave core embedded real-time system is configured to perform the steps of:
writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby;
the slave core executes a starting operation according to the SEV instruction;
the bare core system is configured to run a boot operating step without an operating system program directly on the ARM.
In some embodiments, the step of building the multi-core system corresponding to the AMP architecture further includes device-driven migration and resource allocation.
The invention provides a method for realizing the mutual decoupling of multi-core starting and business by an embedded SOC system, which comprises the following steps: building a multi-core system corresponding to an AMP architecture; in a multi-core system, dividing a shared memory into ARM cores corresponding to each real-time core according to a plurality of real-time cores; dividing a main partition of a system external memory into core 0-N programs for each ARM core to execute; loading an FSBL program to an internal RAM area of the ARM core0 of the main core according to Bootrom, and jumping to an FSBL execution address; initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses; writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby; the main core executes starting operation according to the SEV instruction; writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby; the slave core executes a starting operation according to the SEV instruction; the management core starts to boot and load the operating system, initializes the operating system kernel, executes task scheduling and related service parameter initialization, and manages service data and files of each real-time core. According to the intelligent perception terminal, the multi-core processor is adopted, the AMP architecture is adopted to realize independent starting among a plurality of cores and mutual independence of service configuration, so that the multi-core systems are mutually decoupled, and the stability and reliability of the intelligent perception terminal are improved; the multi-core is started relatively independently, the real-time core operates on the main core, and when the management core operates abnormally, the service logic of the real-time core is not affected, so that the reliability of the intelligent perception terminal is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of an AMP architecture on which the present application is based;
FIG. 2 is a flow chart of a method for implementing the mutual decoupling of multi-core startup and service in an embedded SOC system;
fig. 3 is a schematic diagram illustrating the operation of the method provided in the present application.
Detailed Description
As shown in fig. 1, the method of the present application is applied to an AMP architecture formed by a service module, a real-time core module, a management core module and a shared memory module, unlike in the prior art, in this embodiment, the real-time core module includes a plurality of real-time cores, and a new execution method based on the AMP architecture is designed in the present application.
Referring to fig. 2, a flowchart of a method for implementing mutual decoupling between multi-core startup and service in an embedded SOC system of the present application is shown; referring to FIG. 3, a schematic diagram of the operation of the method is provided herein;
the method of the present application is described below in conjunction with fig. 2 and 3, the method comprising:
s100: firstly, building a multi-core system corresponding to an AMP architecture; the AMP architecture is illustrated from a hardware perspective, where the architecture representing the hardware, such as a business module, may be generally considered a peripheral interface, a shared memory module, may be generally considered a memory storage, etc., while a real-time core module and a management core module may be generally considered multiple cores of a system that assume different functions; the multi-core system realizes specific functions from the software perspective, and can be specifically expressed as software parts including a bootstrap program, a kernel mirror image, a service program and the like.
In step S100, the meaning of the establishment of the multi-core system includes the migration of the device driver, that is, the preparation and the raising of the various device drivers, and the allocation of system resources.
Depending on the functionality, in some embodiments, the multi-core system may be further divided into a master verification-time system, a slave-core embedded real-time system, and a bare-core system. The function of these three systems will be described in the following description.
S200: in a multi-core system, dividing a shared memory into ARM cores corresponding to each real-time core according to a plurality of real-time cores; the ARM cores comprise a master ARM core0 and slave ARM cores 1-N, each ARM core can independently execute a certain task and does not have harmful influence on each other, and the arrangement accords with the theme thought of an AMP architecture. After being divided into a plurality of ARM cores, the ARM cores need to initialize the required resources respectively at the time of starting, so that the system is ensured to be restored to the original state.
The process may occur in synchronization with step S200, S300: dividing a main partition of a system external memory into core 0-N programs for each ARM core to execute; the step is to allocate the divided shared memory to each core, so that each real-time core can independently execute a corresponding program in one ARM core, and for different core programs, the execution of each core program is not affected, and the next program is not required to be executed after one program is completely started, so that the steps S200 and S300 are fundamental technical features for solving the technical problems of the application.
S400: when the multi-core is electrified, executing Bootrom to boot and load the FSBL program to an internal RAM area of the ARM core0 of the main core, and jumping to an FSBL execution address;
BootROM function: after power-on reset, the PS end starts configuration. Without the use of JTAG, ARM would begin executing code in BootROM on-chip. The code in BootROM initializes the basic peripheral controllers for NAND, NOR, quad-SPI, SD and PCAP so that the ARM core can access and use these peripherals.
While other peripherals such as DDR will initialize at stage 1 or later. The code in BootROM is also responsible for loading the boot image of phase 1. The start-up source of PS is selected by the high and low levels of the external mode pins, that is to say BootROM will load the start-up image of phase 1 from different external memories according to the setting of the external configuration pins, which of course also supports direct operation on linear Flash. It should be noted that the configuration of the PL is not done in BootROM, which is only ready for configuring the PL.
FSBL (first stage boot loader) is a boot program that starts after BootROM. Loaded to the OCM by BootROM or run directly on linear Flash. FSBL mainly completes the following work:
1) And according to the configuration in XPS, finishing the initialization of the PS end.
2) The PL is configured using a bitstream file.
3) A second stage boot program (SSBL) or a bare running program (running no operating system program directly on ARM) is loaded into the memory space.
4) Jumps execute SSBL or nude running program (based on nude system). Note that: FSBL does not enable MMU before jumping to SSBL or nude running program. This is because many operating systems, such as linux, assume that the MMU is disabled at boot-up.
S500: the main core is initialized (clock, reset, interrupt and the like), the main partition of the external memory is read, and the execution programs of core 0-N are loaded to the corresponding running starting addresses in sequence;
in this step, only the execution program of core0 to N is loaded to the corresponding operation start address, instead of directly running the execution program as in the prior art, so that other slave cores do not need to wait for starting after the master core is started, so that the overall starting efficiency can be greatly increased, and since each of the steps S200 and S300 implements that each of the ARM cores executes a starting program, the starting programs of the cores are not affected by each other, thereby embodying the decoupling performance of the method of the present application.
S600: writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby;
s700: the main core executes starting operation according to the SEV instruction;
s800: writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby;
s900: the slave core executes a starting operation according to the SEV instruction;
steps S600-S900 describe the execution procedure of all cores, and it should be noted that, when other real-time cores are powered on, the state of waiting for a loop should be entered, waiting for wakeup, and when the distributed loading execution writes the starting address, the other real-time cores jump to the execution address, and start each real-time core in turn, and finally complete the related operation.
S1000: when the execution is carried out to the management core, the management core starts to boot and load the operating system, initializes the operating system core, starts to execute task scheduling and the initialization of related service parameters, and uniformly manages the service data and files of each real-time core.
Further, in the above steps S700 and S800, the step of performing the start operation specifically includes:
the master core (through the master verification time system) performs:
jumping to the written address execution program;
initializing resources;
setting a stack pointer;
main ()'s running core 0;
initializing a platform;
initializing service parameters;
core0 service logic is entered.
The slave core (via the slave core embedded real-time system) performs:
detecting whether the fixed address value is 0;
if not, jumping to the written address execution program;
initializing resources;
setting a stack pointer;
run core1, 2..n-1 or main of N ();
initializing a platform;
initializing service parameters;
core1, 2,..n-1 or N business logic.
In the above two execution methods, if the fixed address value is 0, the step of detecting whether the fixed address value is 0 is executed again until the fixed address value is not 0, and then the subsequent steps are executed again.
Further, after building the multi-core system corresponding to the AMP architecture, the method further includes:
and designating a stack memory corresponding to each real-time core.
Further, after step S1000, the method further includes:
the plurality of service modules complete data interaction through corresponding ARM cores in the shared memory, and the shared memory is divided, so that the data interaction among different services is easy to process, and the plurality of data interactions can be processed by different ARM cores without influence and can be synchronously performed.
Further, when the management core performs data update according to the update configuration information, the management core synchronizes the self-configuration update to each real-time core, thereby maintaining the consistency of the data.
As can be seen from the above technical solution, the method for implementing mutual decoupling between multi-core start and service in an embedded SOC system provided by the present invention includes: building a multi-core system corresponding to an AMP architecture; in a multi-core system, dividing a shared memory into ARM cores corresponding to each real-time core according to a plurality of real-time cores; the ARM core comprises a main core ARM core0 and slave cores ARM cores 1-N; dividing a main partition of a system external memory into core 0-N programs for each ARM core to execute; loading an FSBL program to an internal RAM area of the ARM core0 of the main core according to Bootrom, and jumping to an FSBL execution address; initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses; writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby; the main core executes starting operation according to the SEV instruction; writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby; the slave core executes a starting operation according to the SEV instruction; the management core starts to boot and load the operating system, initializes the operating system kernel, executes task scheduling and related service parameter initialization, and manages service data and files of each real-time core. According to the intelligent perception terminal, the multi-core processor is adopted, the AMP architecture is adopted to realize independent starting among a plurality of cores and mutual independence of service configuration, so that the multi-core systems are mutually decoupled, and the stability and reliability of the intelligent perception terminal are improved; the multi-core is started relatively independently, the real-time core operates on the main core, and when the management core operates abnormally, the service logic of the real-time core is not affected, so that the reliability of the intelligent perception terminal is improved.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (9)
1. The method for realizing the mutual decoupling of the multi-core starting and the service of the embedded SOC system is applied to an AMP architecture formed by a service module, a real-time core module, a management core module and a shared memory module, wherein the real-time core module comprises a plurality of real-time cores, and is characterized in that the method comprises the following steps:
building a multi-core system corresponding to an AMP architecture;
in a multi-core system, dividing a shared memory into ARM cores corresponding to each real-time core according to a plurality of real-time cores; the ARM core comprises a main core ARM core0 and slave cores ARM cores 1-N;
dividing a main partition of a system external memory into core 0-N programs for each ARM core to execute;
loading an FSBL program to an internal RAM area of the ARM core0 of the main core according to Bootrom, and jumping to an FSBL execution address;
initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses;
writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby;
the main core executes starting operation according to the SEV instruction;
writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby;
the slave core executes a starting operation according to the SEV instruction;
the management core starts to boot and load the operating system, initializes the operating system kernel, executes task scheduling and related service parameter initialization, and manages service data and files of each real-time core.
2. The method for implementing mutual decoupling between multi-core startup and service in an embedded SOC system as claimed in claim 1, wherein the step of executing the startup operation by the master core according to the SEV instruction includes:
jumping to the written address execution program;
initializing resources;
setting a stack pointer;
main ()'s running core 0;
initializing a platform;
initializing service parameters;
core0 service logic is entered.
3. The method for implementing mutual decoupling between multi-core initiation and service in an embedded SOC system as claimed in claim 1, wherein the step of executing the initiation operation by the slave core according to the SEV instruction includes:
detecting whether the fixed address value is 0;
if not, jumping to the written address execution program;
initializing resources;
setting a stack pointer;
run core1, 2..n-1 or main of N ();
initializing a platform;
initializing service parameters;
core1, 2,..n-1 or N business logic.
4. The method for implementing mutual decoupling between multi-core initiation and service in an embedded SOC system as claimed in claim 3, wherein the step of detecting whether the fixed address value is 0 is performed again if the fixed address value is 0.
5. The method for implementing mutual decoupling between multi-core initiation and service by an embedded SOC system as claimed in claim 1, wherein after building the multi-core system corresponding to the AMP architecture, the method further comprises:
and designating a stack memory corresponding to each real-time core.
6. The method for implementing mutual decoupling between multi-core initiation and service in an embedded SOC system as claimed in claim 1, further comprising:
and the service modules complete data interaction through corresponding ARM cores in the shared memory.
7. The method for implementing the mutual decoupling of multi-core startup and service by the embedded SOC system according to claim 1, wherein the method comprises the steps of,
when the management core executes data updating according to the updating configuration information, the self-configuration updating is synchronized to each real-time core.
8. The method for implementing the mutual decoupling of the multi-core start and the service by the embedded SOC according to claim 1, wherein the multi-core system comprises a master verification time system, a slave core embedded real-time system and a bare core system; wherein the master verification time system is configured to perform the steps of:
initializing a main core, reading a main partition of an external memory, and sequentially loading execution programs of core 0-N to corresponding operation starting addresses;
writing the initial address of the core0 execution program of the main core into the CPU execution address, and executing the SEV instruction to start and load the execution program of the core0 after the execution is completed by standby;
the main core executes starting operation according to the SEV instruction;
the slave core embedded real-time system is configured to perform the steps of:
writing initial addresses of the core 1-N execution programs into CPU execution addresses in sequence, and executing the SEV instruction to start and record the execution programs of the core 1-N after the execution is completed by standby;
the slave core executes a starting operation according to the SEV instruction;
the bare core system is configured to run a boot operating step without an operating system program directly on the ARM.
9. The method for implementing the mutual decoupling between the multi-core initiation and the service by the embedded SOC system as claimed in claim 1, wherein the step of building the multi-core system corresponding to the AMP architecture further includes device-driven migration and resource allocation.
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| CN115081033B (en) * | 2022-07-20 | 2022-11-11 | 南方电网数字电网研究院有限公司 | Service safety isolation method for edge computing device of digital power distribution network |
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