CN115565492A

CN115565492A - Display panel and display device

Info

Publication number: CN115565492A
Application number: CN202211351391.2A
Authority: CN
Inventors: 熊娜娜
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2023-01-03

Abstract

The invention discloses a display panel and a display device. The display panel includes a pixel circuit and a light emitting element; the pixel circuit comprises a driving transistor, a double-gate transistor, a data writing module and a clamping module; the grid electrode of the driving transistor and the first electrode of the double-grid transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node; the double-gate transistor comprises a first sub transistor and a second sub transistor, and a connection node between the first sub transistor and the second sub transistor is a third node; the working process of the pixel circuit comprises a non-light-emitting stage, wherein the non-light-emitting stage comprises a first sub-stage; the clamping module is used for clamping the potential of the second node to the potential of the third node in at least partial time period of the first sub-stage. In the invention, the voltage difference between the first node and the second node in different working stages of the pixel circuit can be reduced by the clamping module, so that the flicker phenomenon of the display panel is improved, and the display effect is improved.

Description

Display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.

Background

Organic Light-Emitting diodes (OLEDs) have the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed, and become one of the research hotspots in the display field at present. The electronic display product can display in different application scenes by adopting different refresh rates, for example, a driving mode with a higher refresh rate is adopted to drive and display a dynamic picture so as to ensure the fluency of the displayed picture; and a driving mode with a lower refresh rate is adopted to drive and display the static picture so as to reduce the power consumption.

In the prior art, when a low frequency is set, the refresh rate of the light-emitting control signal is generally maintained, and the refresh rate of the reset control signal or the data write control signal is reduced, which causes the difference of the rising speed of the brightness of the light-emitting elements in different display stages, and causes the screen to flicker.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device to improve the flicker phenomenon of the display panel and improve the display effect of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit and a light emitting element;

the pixel circuit comprises a driving transistor, a double-gate transistor, a data writing module and a clamping module;

the driving transistor is used for providing driving current for the light-emitting element;

the data writing module is used for providing data signals for the driving transistor;

the grid electrode of the driving transistor and the first electrode of the double-grid transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node;

the double-gate transistor comprises a first sub transistor and a second sub transistor, and a connection node between the first sub transistor and the second sub transistor is a third node;

the working process of the pixel circuit comprises a non-light-emitting stage, wherein the non-light-emitting stage comprises a first sub-stage; in the first sub-phase, the first sub-transistor and the second sub-transistor are both turned off;

the clamping module is respectively connected with the second node and the third node, and is used for clamping the potential of the second node to the potential of the third node in at least partial time period of the first sub-stage.

In a second aspect, an embodiment of the present invention further provides a display device, including the display panel according to the first aspect of the present invention.

In an embodiment of the present invention, a display panel includes a pixel circuit and a light emitting element; the pixel circuit comprises a driving transistor, a double-gate transistor, a data writing module and a clamping module; the driving transistor is used for providing a driving current for the light-emitting element; the data writing module is used for providing a data signal for the driving transistor; the grid electrode of the driving transistor and the first electrode of the double-grid transistor are connected to a first node, and the data writing module and the first electrode of the driving transistor are connected to a second node; the double-gate transistor comprises a first sub transistor and a second sub transistor, and a connection node between the first sub transistor and the second sub transistor is a third node; the working process of the pixel circuit comprises a non-light-emitting stage, wherein the non-light-emitting stage comprises a first sub-stage; in the first sub-stage, the first sub-transistor and the second sub-transistor are both turned off; the clamping module is respectively connected with the second node and the third node, and is used for clamping the potential of the second node to the potential of the third node in at least partial time period of the first sub-stage. According to the invention, the voltage difference between the first node and the second node is closer before and after the signal is written in by the clamping module, so that the flicker phenomenon of the display panel is better improved, and the display effect of the display panel is improved.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

FIG. 2 is a graph illustrating luminance variation of a display panel according to the related art in different display frames according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a pixel circuit and a light emitting element in a display panel according to an embodiment of the invention;

fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a pixel circuit and a light emitting element in another display panel according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 7 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;

fig. 8 is a schematic structural diagram of a pixel circuit and a light emitting element in another display panel according to an embodiment of the invention;

FIG. 9 is a driving timing diagram of the pixel circuit shown in FIG. 8;

fig. 10 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a pixel circuit in a display panel according to the related art, and fig. 2 is a graph showing luminance variation of the display panel according to the related art, where the luminance variation is generated in different display frames, and as shown in fig. 1 and fig. 2, a first node N1 of a pixel circuit 1' is respectively connected to a gate of a driving transistor T3 and one end of a first double-gate transistor T1. The pixel circuit 1' may include a reset stage, a data writing stage, and a light emitting stage, wherein in the reset stage, the first double-gate transistor T1 is turned on according to a reset control signal, and the reset signal Vref is transmitted to the first node N1 to reset the first node N1, i.e., the gate of the driving transistor; in a data writing phase, writing a data signal Vdata into the first node N1 by the second double-gate transistor T2 while compensating the threshold voltage of the driving transistor T3 to the potential of the first node N1, wherein the potential stored in the first node N1 at the end of the data writing phase is Vdata- | Vth |, and Vth is the threshold voltage of the driving transistor T3; in the light emitting stage, the light emitting control signal controls the light emitting control transistor T4 to be turned on, the driving transistor T3 is turned on, the first power voltage signal PVDD is inputted to the source of the driving transistor T3, and the driving transistor T3 generates the driving current and drives the light emitting element 2' to emit light based on the first power voltage signal PVDD at the source and the threshold-compensated data signal Vdata- | Vth | stored in the first node N1.

In the related art, the refresh rate of the data write control signal is reduced while the refresh rate of the light emission control signal is maintained in the low frequency display of the display panel. For example, when the refresh rate of the light emission control signal is maintained at 60Hz and the refresh rate of the data write control signal is reduced to 15Hz, the display panel drives the display at 15 Hz. In this way, a frame of display image of the display panel may include a write frame A1 and a hold frame A2, the compensated data signal is normally written into the first node N1 in the write frame A1, and then the light emitting element 2' is driven by the voltage written into the first node N1 in the write frame A1 in the hold frame A2, and no data is written into the hold frame A2. The average light emitting brightness of the display panel can be adjusted by adjusting the duration of the active level of each light emitting control signal (also called dimming length) in the holding frame A2.

The inventors have studied and found that, in a non-emission phase, such as a reset phase, in which the frame A1 is written, the potential VN1 of the first node N1 is Vref, the second node N2 maintains the potential (close to the first power supply voltage signal PVDD) at the time of emission of the previous frame, and the gate-source voltage difference Vgs1' = VN1-VN2 ≈ Vref-PVDD of the driving transistor T3. Typically, the reset signal Vref is about-3V, the first power supply voltage signal PVDD is about 3V, and Vgs1' is about-6V. In the non-emission stage of the sustain frame A2, since data writing is no longer performed, the potential VN1 of the first node N1 is Vdata- | Vth |, and the second node N2 holds the potential (close to the first power voltage signal PVDD) when the previous frame emits light, at this time, the gate-source voltage difference Vgs2' = VN1-VN2 ≈ Vdata- | Vth | -PVDD of the driving transistor T3. For example, vdata- | Vth | is around 3V, vgs1' is around-1V. Therefore, | VGS1'| > | VGS2' |, that is, the difference between the gate-source voltage difference VGS of the driving transistor T3 in the non-light-emitting period of writing the frame A1 and maintaining the frame A2 is relatively large, and because the gate-source voltage difference VGS2 'in maintaining the frame A2 is relatively small, the light-emitting luminance of the light-emitting element 2' is increased rapidly in the light-emitting period of maintaining the frame A2; the gate-source voltage difference VGS1 'in the writing frame A1 is large, and the light emitting brightness of the light emitting element 2' is increased slowly (as shown in fig. 2) during the light emitting period of the writing frame A1, thereby causing the problem of flicker of the display panel and affecting the display effect of the display panel.

In view of the above-mentioned drawbacks of the prior art, the inventors propose a technical solution in the present application, and in particular, a display panel including a pixel circuit and a light emitting element;

the data writing module is used for providing a data signal for the driving transistor;

the working process of the pixel circuit comprises a non-light-emitting stage, wherein the non-light-emitting stage comprises a first sub-stage; in the first sub-stage, the first sub-transistor and the second sub-transistor are both turned off;

In the invention, the existence of the clamping module increases the voltage difference (the gate-source voltage difference of the driving transistor) between the first node and the second node in the first sub-stage, and the voltage difference is closer to the gate-source voltage difference of the driving transistor after data writing, thereby reducing the voltage difference between the first node and the second node in different working stages of the pixel circuit, further improving the flicker phenomenon of the display panel and improving the display effect of the display panel.

The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 3 is a schematic structural diagram of a pixel circuit and a light emitting element in a display panel according to an embodiment of the present invention, and referring to fig. 3, the display panel includes a pixel circuit 1 and a light emitting element 2; the pixel circuit 1 comprises a driving transistor T3, a double-gate transistor 3, a data writing module 8 and a clamping module 4; the driving transistor T3 is used to supply a driving current to the light emitting element 2; the data writing module 8 is used for providing a data signal Vdata for the driving transistor T3; the grid electrode of the driving transistor T3 and the first electrode of the double-grid transistor 3 are connected to a first node N1, and the data writing module 8 and the first electrode of the driving transistor T3 are connected to a second node N2; the double-gate transistor 3 includes a first sub-transistor 31 and a second sub-transistor 32, and a connection node between the first sub-transistor 31 and the second sub-transistor 32 is a third node N3; the working process of the pixel circuit 1 comprises a non-light-emitting stage, wherein the non-light-emitting stage comprises a first sub-stage; in the first sub-phase, both the first sub-transistor 31 and the second sub-transistor 32 are turned off; the clamping module 4 is respectively connected to the second node N2 and the third node N3, and the clamping module 4 is configured to clamp the potential of the second node N2 to the potential of the third node N3 in at least a part of the time period of the first sub-stage.

Specifically, as shown in fig. 3, in the present application, the display panel includes a pixel circuit 1 and a light emitting element 2, and the pixel circuit 1 is configured to drive the light emitting element 2 to emit light, thereby completing the display of the display panel. The pixel circuits 1 may be arranged in an array in the display panel, and the pixel circuits 1 are provided with a driving transistor T3, a double-gate transistor 3, a data writing module 8, and a clamping module 4. The first pole of the driving transistor is connected with the data writing module 8, and the connection point of the driving transistor and the data writing module 8 is a second node. In the data writing stage, the data writing control signal controls the data writing module 8 to be turned on, the data signal Vdata is transmitted to the gate of the driving transistor T3, i.e., the first node N1, through the data writing module 8, and then the driving transistor T3 supplies a driving current to the light emitting element 2 according to the data signal Vdata in the light emitting stage.

With continued reference to fig. 3, the first node N1 is also connected to a first gate of the double gate transistor 3. The double-gate transistor 3 is composed of a first sub-transistor 31 and a second sub-transistor 32, the first sub-transistor 31 and the first sub-transistor 31 are connected through a third node N3, and gates of the first sub-transistor 31 and the second sub-transistor 32 are connected to the same scanning signal line and controlled by the same scanning signal. The clamping module 4 is used for connecting the second node N2 and the third node N3.

As known to those skilled in the art, in addition to the driving transistor T3, a reset module 5, a compensation module 6, a light-emitting control module 7, and the like are generally disposed in the pixel circuit 1, the reset module 5 is turned on or off under the control of a reset control signal S1, and in a reset phase, the reset module 5 transmits a reset signal Vref1 to the first node N1. The reset phase typically precedes the data write phase. The compensation module 6 is turned on or off under the control of the data write control signal S2, and in the threshold compensation stage, the compensation module 6 is turned on to detect and self-compensate the deviation of the threshold voltage of the driving transistor T3, and after the threshold compensation, the potential of the first node N1 is Vdata- | Vth |. In the time dimension, the threshold compensation phase may overlap with the data writing phase. The light emission control module 7 is turned on or off under the control of the light emission control signal EM, and when the light emission control module EM is turned on, the driving transistor T3 generates a driving current to drive the light emitting element 2 to emit light.

Fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the invention, referring to fig. 4, in the present application, the working process of the pixel circuit 1 can be divided into a light-emitting phase B1 and a non-light-emitting phase B2, where the light-emitting phase B1 is turned on, the driving current drives the light-emitting element 2 to emit light, and the non-light-emitting phase B2 is an arbitrary time period except the light-emitting phase B1, such as a reset phase ta and a data writing phase (threshold compensation phase) tb. The non-emitting phase B2 further includes a first sub-phase B3, and in the first sub-phase B3, the first sub-transistor 31 and the second sub-transistor 32 are both in an off state. The first sub-transistor 31 and the second sub-transistor 32 may be P-type transistors, and the scan signal for controlling the first sub-transistor 31 and the second sub-transistor 32 to be turned off is at a high level. In this application, the clamping module 4 can clamp the potential of the second node N2 to the potential of the third node N3 in at least a part of the time period of the first sub-stage B3, that is, the potential of the third node N3 is charged into the second node N2. Since the third node N3 between the first sub-transistor 31 and the second sub-transistor 32 is pulled high by the high-level scan signal, the clamp block 4 can charge a higher potential into the second node N2.

The first sub-stage B3 may be a part of the time period in the hold frame A2 in the related art. According to the above description of the related art, if the clamp block 4 is not present, the difference between the gate-source voltages of the driving transistors in the retention frame A2 and the write frame A1 is large, and the rising speeds of the light emitting brightness of the light emitting elements in the respective light emitting phases are different. In the application, in the first sub-stage B3, the potential of the third node N3 can be charged into the second node N2 through the clamping module 4, so that the potential of the second node N2 is raised, and after the potential of the second node N2 is raised, the voltage difference (the gate-source voltage difference of the driving transistor) between the first node N1 and the second node N2 is increased, and is closer to the gate-source voltage difference of the driving transistor in the write-in frame A1, so that the flicker phenomenon of the display panel is better improved, and the display effect of the display panel is improved.

The embodiment of the present invention does not limit the specific location of the double-gate transistor, and those skilled in the art can set the double-gate transistor according to the actual requirement, and fig. 3 exemplarily shows that the compensation module 6 is set as the double-gate transistor 3. The actual arrangement is not limited thereto.

The compensation module 6 including the dual-gate transistor 3 is used as an example to explain the technical principle of the present invention. In the first sub-phase B3, the first and second sub-transistors 31 and 32 are turned off, and the data signal Vdata is not written to the first node N1. In general, the scan signal for controlling the first and second sub-transistors 31 and 32 to be turned off is a high level signal VGH, and the potential of the third node N3 is pulled high. Under the action of the clamping module 4, the potential VN2 of the second node N2 becomes close to the voltage value of the high-level signal VGH, the potential VN1 of the first node N1 is still Vdata- | Vth |, and the value of VGH is generally about 8V. At this time, the gate-source voltage difference Vgs2 of the driving transistor T3 is approximately equal to Vdata- | Vth | -VGH approximately equal to-5V. Except for the first sub-stage B3, when the data signal Vdata is written into the first node N1 in the non-light-emitting stage B2, the gate-source voltage difference Vgs1 of the driving transistor T3 is the same as Vgs1' in the related art and is about-6V, and Vgs1 is close to Vgs2, so that the problem that the rising speed of the light-emitting brightness of the light-emitting element 2 is different in different light-emitting stages in the related art can be solved, the phenomenon of flicker is avoided to a large extent, and the display effect of the display panel is effectively improved.

Optionally, the embodiment of the present invention does not limit the specific arrangement manner of the clamping module 4, and a person skilled in the art can perform the arrangement according to actual requirements, and any specific design scheme for realizing the function of the clamping module 4 is within the technical scheme protected by the present invention.

In the invention, the existence of the clamping module increases the voltage difference between the first node and the second node (the gate-source voltage difference of the driving transistor) in the first sub-stage, and the voltage difference before and after the signal is written into the first node is closer, namely, the voltage difference between the first node and the second node when the signal is written into the first node is closer to the voltage difference between the first node and the second node when the signal is not written into the first node, so that the voltage difference between the first node and the second node in different working stages of the pixel circuit is reduced, the flicker phenomenon of the display panel is improved, and the display effect of the display panel is improved.

Optionally, with continuing reference to fig. 4, the non-light emitting period further includes a second sub-period B4, and in the second sub-period B4, both the first sub-transistor 31 and the second sub-transistor 32 are turned on; the pixel circuit 1 further comprises a reset module 5, the reset module 5 is configured to provide a reset signal Vref1 to the first node N1 in the second sub-stage B4, and the reset module 5 comprises a dual-gate transistor 3; alternatively, the pixel circuit 1 further comprises a compensation module 6, the compensation module 6 being configured to detect and self-compensate for a deviation of the threshold voltage of the driving transistor T3 in the second sub-phase B4, the compensation module 6 comprising the dual gate transistor 3.

Optionally, the non-emitting period B2 may include a first sub-period B3 and a second sub-period B4, where the second sub-period B4 is a period for writing the reset signal Vref1 or the data signal Vdata into the first node N1 in the above embodiment, that is, a partial period for writing into the frame A1 in the related art. In the embodiment shown in fig. 3, the compensation module 6 is used as the dual-gate transistor 3 for description, when the compensation module 6 is the dual-gate transistor 3, the second sub-phase B4 corresponds to the threshold compensation phase (data writing phase) tb, and in the second sub-phase B4, the potential VN1 of the first node N1 is Vdata- | Vth |.

Fig. 5 is a schematic structural diagram of a pixel circuit and a light emitting element in another display panel according to an embodiment of the present invention. In the embodiment shown in fig. 5, the reset module 5 may further include the dual-gate transistor 3, when the reset module 5 is the dual-gate transistor 3, the second sub-phase B4 may correspond to the reset phase ta, and in the second sub-phase B4, the potential VN1 of the first node N1 is Vref-PVDD. When the reset module 5 is a dual-gate transistor 3, the operation principle of the clamp module 4 is the same as that in the above-mentioned embodiment, and will not be described too much here.

With continued reference to fig. 3 to 5, the clamping module 4 may include a first transistor 41, two ends of the first transistor 41 are respectively connected to the second node N2 and the third node N3, and a control end of the first transistor 41 receives the clamping control signal S-RST; the first transistor 41 is arranged to be turned on during at least part of the time period of the first sub-phase B3 under control of the clamp control signal S-RST.

As a possible embodiment, the function of the clamping module 4 can be implemented with transistors. Specifically, a first transistor 41 may be disposed in the clamping module 4, a first terminal of the first transistor 41 is connected to the second node N2, a second terminal of the first transistor 41 is connected to the third node N3, and a control terminal of the first transistor 41 is configured to receive the clamping control signal S-RST. The clamp control signal S-RST controls the first transistor 41 to be in a conducting state for at least part of the time during the first sub-phase B3. The first transistor 41 is shown as a P-type transistor, but the actual arrangement is not limited thereto. When the first transistor 41 is a P-type transistor, the clamp control signal S-RST is at a low level during at least a portion of the first sub-phase B3 to control the first transistor 41 to be turned on. The pixel circuits 1 and the first transistors 41 may be in a one-to-one correspondence relationship, that is, each pixel circuit 1 is provided with a first transistor 41, and the first transistor 41 can charge the potential of the third node N3 of the pixel circuit 1 to the second node N2 of the pixel circuit 1.

In addition, optionally, in the embodiment of the present invention, when the reset module 5 includes the dual-gate transistor 3, the first transistor 41 is further configured to be turned off in the second sub-phase B4 under the control of the clamp control signal S-RST; when the compensation block 6 comprises the dual gate transistor 3, the first transistor 41 is further adapted to be switched off in the second sub-phase B4 under control of the clamping control signal S-RST.

Specifically, when the reset module 5 is the dual-gate transistor 3 (shown in fig. 5), in the second sub-phase B4, i.e., the reset phase ta, the clamp control signal S-RST controls the first transistor 41 to turn off, so as to prevent the first transistor 41 from charging the potential of the third node N3 into the second node N2, thereby ensuring the reset effect of the reset module 5 on the potential of the first node N1.

When the compensation module 6 is the dual-gate transistor 3 (shown in fig. 3), in the second sub-stage B4, i.e., the threshold compensation stage tb, the clamp control signal S-RST controls the first transistor 41 to turn off, so as to prevent the first transistor 41 from charging the potential of the third node N3 into the second node N2, and ensure the compensation effect of the compensation module 6 on the potential of the first node N1. Illustratively, when the first transistor 41 is a P-type transistor, the clamp control signal S-RST should be high during the reset stage ta or the threshold compensation stage tb to control the first transistor 41 to turn off.

Next, the driving timing of the pixel circuit in this embodiment will be described in its entirety with reference to fig. 3 and 4. The second sub-phase B4 can be a threshold compensation phase tb (data writing phase). In the non-emission phase B2, the emission control signal EM is at a high level, and the emission control module 7 is turned off, and in the emission phase B1, the emission control signal EM is at a low level, and the emission control module 7 is turned on. As shown in fig. 4, the first sub-phase B3 and the second sub-phase B4 are both in the high level period of the emission control signal EM, first, the data writing control signal S2 becomes active level (low level), the data writing module 8 and the compensation module 6 are turned on, the compensated data signal is written into the first node N1, after the data signal is written, the data writing control signal S2 jumps to high level, the dual-gate transistor 3 is turned off, and the third node N3 between the first sub-transistor 31 and the second sub-transistor 32 is pulled to high level. In the above process, the clamp control signal S-RST is always at an inactive level (high level). After the threshold compensation stage tb is finished, the clamp control signal S-RST jumps to an active level (low level), the first transistor 41 is turned on, and the high potential of the third node N3 is charged into the second node N2. The on period of the first transistor 41 is the first sub-phase B3. The first sub-phase B3 is located after the second sub-phase B4.

Optionally, referring to fig. 3 to 5, the pixel circuit 1 may further include a data storage module 10; the reset module 5 is connected between a reset signal end Vref1 and a first node N1, a control end of the reset module 5 receives a reset control signal S1, and the reset module 5 is used for providing the reset signal Vref1 for the first node N1 under the control of the reset control signal S1; the data writing module 8 is connected to the data signal end Vdata and the first pole of the driving transistor T3, and the control end of the data writing module 8 receives the data writing control signal S2; the compensation module 6 is connected between the second pole of the driving transistor T3 and the first node N1; the data storage module 10 is connected between the first power voltage terminal PVDD and the first node N1; the data writing module 8 is configured to write a data signal Vdata to the first node N1 sequentially through the driving transistor T3 and the compensation module 6 under the control of the data writing control signal S2, and the data storage module 10 is configured to store the data signal written into the first node N1.

In the above embodiments, the data writing module 8, the resetting module 5, and the compensating module 6 are mentioned, two ends of the resetting module 5 may be specifically located between the resetting signal terminal Vref1 and the first node N1, and the control terminal of the resetting module 5 receives the resetting control signal S1, so as to reset the first node N1. The data writing module 8 may be specifically located between the data signal terminal Vdata and the first terminal of the driving transistor T3, and a control terminal of the data writing module 8 is configured to receive the data writing control signal S2; the compensation module 6 may be specifically located between the second pole of the driving transistor T3 and the first node N1, and a control terminal of the compensation module 6 may receive the same data writing control signal S2 as the data writing module 8. In the data writing phase tb, the data signal Vdata is written into the first node N1 through the driving transistor T3 and the compensation module 6. For the specific working principle of each stage, reference may be made to the above embodiments, which are not described herein again.

In addition, the pixel circuit 1 is further provided with a data storage module 10, the data storage module 10 is located between the first power voltage terminal PVDD and the first node N1, and the data signal Vdata written in the data writing stage tb can be stored in the data storage module 10.

The reset module 5 may be a reset transistor, the data write module 8 may be a data write transistor, the compensation module 6 may be a compensation transistor, the light-emitting control module 7 may be a first light-emitting control transistor 71 and a second light-emitting control transistor 72, and the data storage module 10 may be a storage capacitor, which may be P-type transistors, but is not limited thereto.

Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 3 and fig. 6, in a possible embodiment, the display panel may include N rows of pixel circuits 1 and M cascaded first shift registers 11, where N and M are positive integers greater than or equal to 1, and N < M; the first shift register 11 is configured to provide a first scanning signal to the pixel circuit 1, and the first scanning signals provided by the first shift registers 11 at different stages are sequentially shifted by the same distance in time sequence; in the pixel circuit 1 in the nth row, the nth stage first shift register 11 provides the control terminal of the reset module 5 with the first scan signal as the reset control signal S1, and the (n + 1) th stage first shift register 11 provides the control terminal of the data write module 8 with the first scan signal as the data write control signal S2; wherein N is a positive integer greater than or equal to 1 and less than or equal to N.

Specifically, as shown in fig. 6, N rows of pixel circuits 1 in the display panel, and M first shift registers 11 for supplying the first scan signal S1 to the pixel circuits 1, the M first shift registers 11 are arranged in cascade, that is, M cascaded first shift registers 11 can be arranged in the row direction in which the pixel circuits 1 are located, and the specific meaning of the cascade arrangement is known to those skilled in the art and will not be described in detail herein.

Where M and N should each be a positive integer greater than or equal to 1, and the number of first shift registers 11 is greater than the number of rows of pixel circuits 1. First scan signals required for the respective devices in the pixel circuits 1 are supplied to the N pixel circuits 1 from the M first shift registers 11. The direction from top to bottom in the figure is the first direction X, and along the first direction X, the first scan signals provided by the first shift registers 11 at each stage are sequentially delayed for the same time in time sequence, that is, after the first scan signal is sent out by the first shift register 11 at the nth (N is a positive integer, and N is greater than or equal to 1 and less than or equal to N), the first shift register 11 at the N +1 th stage delays for a preset time to send out the first scan signal.

In this embodiment, for a certain row of pixel circuits 1, for example, the nth row of pixel circuits 1, the nth stage first shift register 11 provides the first scan signal to the reset module 5 of the nth row of pixel circuits 1 as the reset control signal S1 for controlling the on or off of the reset module 5; and, the first scan signal provided by the n +1 th stage first shift register 11 to its data writing block 8 is used as a data writing control signal S2 for controlling the data writing block 8 to turn on or off. Meanwhile, the first scan signal provided by the (n + 1) th stage first shift register 11 is also used as the reset control signal S1 of the reset module 5 in the (n + 1) th row of pixel circuits 1. In short, the data write control signal S2 received by the pixel circuit 1 in the current row may also be understood as the reset control signal S1 for the pixel circuit 1 in the next row.

Fig. 7 is a timing diagram of another driving method for a pixel circuit according to an embodiment of the present invention, and the driving process is described with reference to fig. 7. Referring to fig. 7, when n =1, the 1 st stage first shift register 11 outputs the first scan signal serving as the reset control signal S1-1 to the 1 st row of pixel circuits 1, the 2 nd stage first shift register 11 outputs the first scan signal serving as both the data write control signal S2-1 for the 1 st row of pixel circuits 1 and the reset control signal S1-2 for the 2 nd row of pixel circuits 1 after a delay of a preset time Δ t, and so on, and the n +1 th stage first shift register 11 outputs the first scan signal serving as both the reset control signal S1- (n + 1) for the n-1 th row of pixel circuits 1 and the data write control signal S2-n for the n-1 th row of pixel circuits 1. It can be understood that the first scan signal output by the first shift register 11 of the 1 st stage is also used as a start signal to control the first shift registers 11 of the respective stages to be sequentially delayed by a preset time to turn on and transmit the first scan signal.

Optionally, referring still to fig. 6, the display panel further includes N cascaded second shift registers 12; the second shift register 12 is used for providing a second scanning signal to the pixel circuit, and the second scanning signals provided by the second shift registers 12 at different stages are sequentially shifted by the same distance in time sequence; the nth stage second shift register 12 supplies the second scan signal as a clamp control signal to the first transistors in the pixel circuits of the nth row.

As shown in fig. 6, N cascaded second shift registers 12 are further disposed in the display panel, the number of the second shift registers 12 is the same as the number of rows of the pixel circuits 1, and each stage of the second shift registers 12 provides a second scanning signal to the pixel circuits 1 in the corresponding row, where the second scanning signal can be used as a clamping control signal S-RST received by the first transistor 41 in each row of the pixel circuits. For example, the 1 st stage second shift register 12 transmits the clamp control signal S-RST to the 1 st row of pixel circuits. In the first direction X, the second scan signals provided by the second shift registers 12 of each stage are sequentially delayed by the same time, that is, after the nth shift register sends out the second scan signal, the (n + 1) th shift register 11 delays for a preset time to send out the second scan signal.

The second shift register 12 is separately arranged, and the second shift register 12 provides the clamping control signals S-RST for the pixel circuits 1 in the corresponding row, so that the accuracy of transmission of the clamping control signals S-RST can be improved, and the clamping module 4 can be guaranteed to normally complete clamping work.

With continued reference to fig. 6, the display panel includes a display area AA, and the first shift register 11 and the second shift register 12 are respectively located on both sides of the display area 11 in the row direction.

It is understood that the pixel circuit 1 is disposed in the display area AA of the display panel, and the shift register is disposed in the non-display area NA on both sides of the display area AA. In this embodiment, the first shift register 11 and the second shift register 12 may be respectively disposed in the non-display area NA on both sides of the display area AA. In this arrangement, the first shift register 11 and the second shift register 12 can be driven by a single side, so that the occupied size of the shift register in the non-display area NA is not increased, and the frame of the display panel can be ensured to be narrow.

The first shift register 11 and the second shift register 12 are only exemplarily shown in fig. 6, and any shift register known to those skilled in the art, such as the light emission control shift register 13, may be further provided in the display panel, but is not limited thereto.

Fig. 8 is a schematic structural diagram of a pixel circuit and a light emitting element in a display panel according to another embodiment of the present invention, fig. 9 is a driving timing diagram of the pixel circuit shown in fig. 8, as shown in fig. 8 and fig. 9, the operation process of the pixel circuit 1 further includes a dual-gate-off period B5, and in the dual-gate-off period B5, both the first sub-transistor 31 and the second sub-transistor 32 are turned off; the first sub-phase B3 is located within the double-gate-off phase B5; the clamp module 4 includes a potential capture unit 42 and a potential write-in unit 43, the potential capture unit 42 is configured to capture and store a potential of the third node N3 in a capture period t 1; the potential writing unit 43 is configured to write the potential of the third node N3 onto the second node N2 in the writing period t2; in the time dimension, the capture period t1 and the write period t2 are both located in the dual-gate-off stage B5, the write period t2 is located in the first sub-stage B3, and the write period t2 is located after the capture period t 1.

In the present embodiment, in the time dimension, the period of time when the first sub-transistor 31 and the second sub-transistor 32 are turned off simultaneously is the dual-gate-off period B5, and the first sub-period B3 is located in the dual-gate-off period B5. In this embodiment, the clamp module 4 may adopt another arrangement, and the potential capture unit 42 and the potential write unit 43 may be adopted to constitute the clamp module 4. The potential grasping unit 42 is connected to the third node N3 of the pixel circuit 1, and the potential grasping unit 42 operates during a grasping period t1 in which the potential grasping unit 42 grasps and stores the potential of the third node N3 in the pixel circuit 1. The potential writing unit 43 is connected to the potential grasping unit 42 and the second node N2 of the pixel circuit 1, respectively, the potential writing unit 43 operates in the writing period t2, and in the writing period t2, the potential writing unit 43 writes the potential of the third node N3 grasped by the potential grasping unit 42 into the second node N2 of the pixel circuit 1.

It will be appreciated that since the first sub-phase B3 is within the dual gate off phase B5, both the fetch period t1 and the write period t2 should be within the dual gate off phase B5. In addition, the potential should be grasped first and then potential writing should be performed, and therefore, the writing period t2 should be located after the grasping period t1 in the time dimension. It should be noted that, in order to ensure that the potential of the third node N3 can be charged into the second node N2 in the writing period t2, the writing period t2 should be located in the first sub-phase B3. The capturing period t1 may be located in the first sub-phase B3 or before the first sub-phase B3, which is not limited in this embodiment.

It can be understood by those skilled in the art that, compared to the embodiment shown in fig. 3 in which the third node N3 is directly electrically connected to the second node N2 of the corresponding pixel circuit 1, in this embodiment, there is a transition stage of potential capture, and the operation of the whole pixel circuit 1 is more stable.

Optionally, the embodiment of the present invention does not limit the specific arrangement manner of the potential capture unit 42 and the potential write unit 43, and a person skilled in the art may perform the arrangement according to actual requirements, and any method capable of implementing the potential capture and the potential write is within the scope of the technical solution protected by the embodiment of the present invention.

With continued reference to fig. 8, in an exemplary embodiment, the potential capture unit 42 may include a second transistor 44 and a first storage capacitor 45, two ends of the second transistor 44 are respectively electrically connected to the third node N3 and the first plate c1 of the first storage capacitor 45, and the second plate c2 of the first storage capacitor 45 is connected to a fixed potential; a control terminal of the second transistor 44 receives the potential capture control signal S3, and the second transistor 44 is configured to be turned on in the capture period t1 under the control of the potential capture control signal S3; the potential writing unit 43 includes a third transistor 46, two ends of the third transistor 46 are respectively electrically connected to the second node N2 and the first plate c1 of the first storage capacitor 45, a control end of the third transistor 46 receives the potential writing control signal S4, and the third transistor 46 is configured to be turned on in the writing period t2 under the control of the potential writing control signal S4.

As shown in fig. 8, the potential capture unit 42 is composed of a second transistor 44 and a first storage capacitor 45, a control terminal of the second transistor 44 receives the potential capture control signal S3, the second transistor 44 is further configured to connect the third node N3 and a certain plate (which may be a first plate c 1) of the first storage capacitor 45, and another plate (which may be a second plate c 2) of the first storage capacitor 45 is connected to the fixed potential signal. In the capture period t1, the potential capture control signal S3 controls the second transistor 44 to be turned on, and when the second transistor 44 is turned on, the potential of the third node N3 connected to the second transistor 44 is stored in the first storage capacitor 45.

The potential writing unit 43 may be formed by a third transistor 46, a control terminal of the third transistor 46 receives the potential writing control signal S4, and the third transistor 46 may be used to connect the second node N2 of the pixel circuit and the first plate c1 of the first storage capacitor 45. In the writing period t2, the potential writing control signal S4 controls the third transistor 46 to be turned on, and the third transistor 46 writes the potential of the third node N3 of the pixel circuit 1 to the second node N2 of the pixel circuit 1.

Optionally, when the reset module 5 includes the dual-gate transistor 3, the third transistor 46 is further configured to turn off in the second sub-phase B4 under the control of the potential writing control signal S4; when the compensation module 6 comprises the double-gate transistor 3, the third transistor 46 is further used to turn off in the second sub-phase B4 under the control of the potential write control signal S4.

Specifically, when the reset module 5 is the dual-gate transistor 3, the second sub-phase B4 is the reset phase ta, and in the second sub-phase B4, the potential writing control signal S4 controls the third transistor 46 to turn off; when the compensation module 6 is the dual-gate transistor 3, the second sub-stage B4 is a threshold compensation stage tb, and the potential write control signal S4 controls the third transistor 46 to turn off during the threshold compensation stage tb. For example, when the third transistor 46 is a P-type transistor, in the second sub-phase B4 (the reset phase ta or the threshold compensation phase tb), the potential writing control signal S4 should be at a high level to control the third transistor 46 to turn off. Therefore, the reset effect of the reset module 5 on the potential of the first node N1 or the compensation effect of the compensation module 6 on the potential of the first node N1 can be ensured, and the turn-off of the third transistor 46 is ensured in the bit stage ta or the threshold compensation stage tb, so that the third transistor 46 is prevented from charging the potential of the third node N3 into the first node N1.

With continued reference to fig. 8, as an alternative embodiment, the second plate c2 of the first storage capacitor 45 may be electrically connected to the cathode of the light emitting element 2. The cathode of the light emitting device 2 is connected to a fixed low potential, so that the cathode of the light emitting device 2 can be directly connected to the second electrode c2, thereby simplifying the manufacturing process of the potential capture unit 42.

In the display panel shown in the above embodiment, each of the clamping modules 4 provided corresponding to each of the pixel circuits 1 includes a potential capture unit 42 and a potential write unit 43. Alternatively, in other possible embodiments, the display panel may include a plurality of pixel circuits 1 sequentially arranged in the row direction and the column direction, respectively; all the pixel circuits 1 or the clamp modules 4 in the pixel circuits 1 in the same row share the same potential grasping unit 42.

Specifically, the plurality of pixel circuits 1 are sequentially arranged in a row direction and a column direction, which is a first direction. Since the potential capture unit 42 is used for capturing and storing the potential of the third node N3 in the pixel circuit 1, different pixel circuits 1 can be set to share one potential capture unit 42, and the potential write-in unit 43 in the pixel circuit 1 sharing the potential capture unit 42 is electrically connected to the same potential capture unit 42. For example, the clamp blocks 4 of all the pixel circuits 1 share one potential grasping unit 42, each clamp block 4 extracts a potential from the potential grasping unit 42, and only one potential grasping unit 42 may be provided in the display panel. For another example, the clamping modules 4 of the same row of pixel circuits 1 share one potential capture unit 42, the clamping modules 4 of the same row extract potentials from the same potential capture unit 42, and when N rows of pixel circuits 1 are disposed in the display panel, N potential capture units 42 may be disposed in the display panel.

Alternatively, and still referring to fig. 4, when the compensation module 6 is provided in the pixel circuit, the compensation module 6 is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor in the second sub-phase B4; the display panel comprises a first working mode, wherein the first working mode comprises a writing frame A1 and a maintaining frame A2; in the writing frame A1, the non-emission phase B2 of the pixel circuit 1 includes a second sub-phase B4; in the non-emission period B2 in the holding frame A2, the pixel circuit 1 and the compensation module 6 are normally closed.

In the embodiment mentioned above, the compensation module 6 is used to write the data signal Vdata into the first node N1 during the second sub-phase B4. The low frequency display mode of the display panel may be defined as a first operation mode, the first operation mode including a write frame A1 and a hold frame A2, the write frame A1 and the hold frame A2 being the same as those mentioned in the related art.

Specifically, the second sub-stage B4 is a non-light-emitting stage B2 in the write frame A1, in the second sub-stage B4, the data write control signal S2 is at a low level, the data write module 8 and the compensation module 6 are both turned on, and the data signal Vdata is written into the first node N1; in the non-light-emitting stage B2 of the holding frame A2, the data writing control signal S2 is at a low level, the data writing module 8 and the compensation module 6 are both turned off, the data signal Vdata is not written any more, and the data writing module 8 and the compensation module 6 are in a normally-closed state. At this time, if the compensation module 6 is the dual-gate transistor 3, the first sub-phase B3 can be located in the non-emitting phase B2 in the writing frame A1 and the holding frame A2 in the time dimension. In the partial non-emission period B2 in the write frame A1 and the hold frame A2, the clamp control signal S-RST transitions to a low level, and the clamp block 4 is turned on.

Still referring to fig. 3 or 5, the pixel circuit 1 is further provided with an anode initialization module 9, and the anode initialization module 9 is connected between the anode initialization signal terminal Vref2 and the anode of the light emitting element 2; the control end of the anode initialization module 9 receives an anode initialization signal, and the anode initialization module resets the anode of the light-emitting element 2 under the control of the anode initialization signal; the anode initialization signal is multiplexed into the clamp control signal S-RST.

Specifically, the anode of the light emitting element 2 is also electrically connected to one end of the anode initialization module 9, and the other end of the anode initialization module 9 is connected to the initialization signal terminal Vref2. The control terminal of the anode initialization module 9 is configured to receive an anode initialization signal. In the anode initialization stage, the anode initialization signal controls the anode initialization module 9 to be turned on, and the initialization signal Vref2 provided by the anode initialization signal terminal Vref2 reaches the anode of the light emitting element 2 through the anode initialization module 9, so as to reset the anode of the light emitting element 2.

In this embodiment, the anode initialization signal may be multiplexed into the clamp control signal S-RST, and the anode initialization phase may be set to at least partially overlap the first sub-phase B3 in the time dimension. In the anode initialization phase, the first sub-transistor 31 and the second sub-transistor 32 are both turned off; meanwhile, the clamping module 4 is turned on to clamp the potential of the second node N2 to the potential of the third node N3. The anode initialization module 9 may be, but is not limited to, the anode initialization transistor 91.

The anode initialization signal is multiplexed into the clamping control signal S-RST, no additional clamping control signal S-RST transmission line is needed, the preparation process of the display panel is not increased too much, and the arrangement mode of all the existing control signal transmission lines is not influenced.

Fig. 10 is a driving timing diagram of another pixel circuit according to an embodiment of the invention, and the driving timing diagram shown in fig. 10 is applicable to the pixel circuit shown in fig. 3. As shown in fig. 10, the non-emission phase B2 includes a clamping period B6, and within the clamping period B6, the clamping module 4 is turned on; in the time dimension, the non-light-emitting stage B2 lasts from the light-emitting end time point to the next light-emitting start time point; the distance D1 of the clamping period B6 from the light emission start time point of the non-light emission stage B2 is greater than the distance D2 from the light emission end time point of the non-light emission stage B2.

The clamping period B6 is at least a partial period in the first sub-stage B3. As can be understood by those skilled in the art, in the time dimension, the light emitting end point where one light emitting process ends to the light emitting start point where the next light emitting starts is a non-light emitting stage B2, the clamping time period B6 is in the non-light emitting stage B2, and the clamping control signal S-RST controls the clamping module to be turned on in the clamping time period B6. In the present embodiment, as shown in fig. 10, in one non-emission period B2, a distance D2 between the clamp period B6 and the emission end point where the last emission ends may be set to be smaller than or equal to a distance D1 between the clamp period B6 and the emission start point where the next emission starts. In short, the clamping time period B6 is located at the front stage of the non-light-emitting stage B2, so that the potential of the second node N2 is firstly pulled up in the non-light-emitting stage B2, so that the second node N2 can be kept at a higher potential for a certain time, which is beneficial to improving the stability of the potential of the second node N2.

With continuing reference to fig. 10, the non-emission phase B2 includes a clamping period B6 and a second sub-phase B4; in the clamping time period B6, the clamping module 9 is turned on; in the second sub-phase B4, both the first sub-transistor 31 and the second sub-transistor 32 are turned on; the duration T1 of the clamp period B6 satisfies: t2 is more than or equal to T1 and is more than or equal to T3-T2; wherein, T2 is the duration of the second sub-phase B4, and T3 is the duration of the non-emitting phase B2.

As shown in fig. 10, in the present embodiment, the non-emission phase B2 may be divided into the clamping period B6 and the second sub-phase B4, and the clamping period B6 may overlap with the first sub-phase B3 in a time dimension. During the clamping period B6, both the first sub-transistor 31 and the second sub-transistor 32 are turned off. The second sub-stage B4 and the clamping period B6 alternate, and both the first sub-transistor 31 and the second sub-transistor 32 are turned on during the second sub-stage B4.

Referring to fig. 10, in the present embodiment, the duration T1 of the clamping period B6, the duration T2 of the second sub-phase B4, and the duration T3 of the non-emission phase B2 may satisfy the following relationship: t2 is more than or equal to T1 and is more than or equal to T3-T2. It can be understood that the total duration of the clamping period B6 and the second sub-phase B4 in the same non-emission phase B2 does not exceed the total duration of the non-emission phase B2, i.e., T1 ≦ T3-T2; meanwhile, the working time of the clamping module 9 should be not less than the working time of the reset module 5 or the compensation module 6, that is, T2 is not more than T1, so as to ensure that the potential of the third node N3 has enough time to be charged into the second node N2.

The embodiment of the present invention does not limit the specific setting value of the time length of each phase, and those skilled in the art can set the time length according to actual requirements.

Based on the same concept, an embodiment of the present invention further provides a display device, fig. 11 is a schematic structural diagram of the display device according to the embodiment of the present invention, and referring to fig. 11, the display device may include any one of the display panels 100 provided in the above embodiments. Moreover, the display device is manufactured by adopting the display panel, so that the same or corresponding technical effects of the display panel are achieved. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device may be a mobile phone, a tablet, a computer, a television, a wearable smart device, and the like, and the embodiment of the present invention is not limited.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel includes a pixel circuit and a light emitting element;

the clamping module is respectively connected with the second node and the third node, and is used for clamping the potential of the second node to the potential of the third node in at least part of the time period of the first sub-stage.

2. The display panel according to claim 1, wherein the non-emission phase further comprises a second sub-phase in which the first sub-transistor and the second sub-transistor are both turned on;

the pixel circuit further comprises a reset module for providing a reset signal to the first node in the second sub-phase, the reset module comprising the dual-gate transistor; alternatively, the first and second electrodes may be,

the pixel circuit further comprises a compensation module for detecting and self-compensating for deviations of the threshold voltage of the drive transistor in the second sub-phase, the compensation module comprising the dual gate transistor.

3. The display panel according to claim 2, wherein the clamping module comprises a first transistor, two ends of the first transistor are respectively connected to the second node and the third node, and a control terminal of the first transistor receives a clamping control signal;

the first transistor is used for conducting in at least partial time of the first sub-stage under the control of the clamping control signal.

4. The display panel according to claim 3, wherein when the reset module comprises the dual gate transistor, the first transistor is further configured to turn off in the second sub-phase under the control of the clamp control signal;

when the compensation module comprises the double-gate transistor, the first transistor is also used for being switched off in the second sub-stage under the control of the clamping control signal.

5. The display panel according to claim 4, wherein the pixel circuit further comprises a data storage block;

the reset module is connected between a reset signal end and the first node, a control end of the reset module receives a reset control signal, and the reset module is used for providing a reset signal for the first node under the control of the reset control signal;

the data writing module is connected to a data signal end and the first pole of the driving transistor, and a control end of the data writing module receives a data writing control signal; the compensation module is connected between the second pole of the driving transistor and the first node; the data storage module is connected between a first power supply voltage end and the first node;

the data writing module is used for writing data signals into the first node sequentially through the driving transistor and the compensation module under the control of the data writing control signal, and the data storage module is used for storing the data signals written into the first node.

6. The display panel according to claim 5, wherein the display panel comprises N rows of pixel circuits and M cascaded first shift registers, wherein N and M are positive integers greater than or equal to 1, and N < M;

the first shift register is used for providing a first scanning signal for the pixel circuit, and the first scanning signals provided by the first shift registers at all stages are sequentially shifted by the same distance in time sequence;

in the pixel circuits in the nth row, the nth stage of the first shift register supplies the first scan signal to the control terminal of the reset module as the reset control signal, and the (n + 1) th stage of the first shift register supplies the first scan signal to the control terminal of the data write module as the data write control signal;

wherein N is a positive integer greater than or equal to 1 and less than or equal to N.

7. The display panel of claim 6, wherein the display panel further comprises N cascaded second shift registers;

the second shift register is used for providing a second scanning signal for the pixel circuit, and the second scanning signals provided by the second shift registers at all stages are sequentially shifted by the same distance in time sequence;

the second shift register of the nth stage supplies the second scan signal as the clamp control signal to the first transistor in the pixel circuit of the nth row.

8. The display panel according to claim 7, wherein the display panel comprises a display area, and the first shift register and the second shift register are respectively located on both sides of the display area in a row direction.

9. The display panel according to claim 2, wherein the operation of the pixel circuit further comprises a dual-gate off phase in which both the first sub-transistor and the second sub-transistor are turned off; the first sub-phase is within the dual gate off phase;

the clamping module comprises a potential grabbing unit and a potential writing-in unit, and the potential grabbing unit is used for grabbing and storing the potential of the third node in a grabbing time period;

the potential writing unit is used for writing the potential of the third node onto the second node in a writing period;

wherein, in the time dimension, the grabbing period and the writing period are both located in the dual-gate off phase, and the writing period is located in the first sub-phase and is located after the grabbing period.

10. The display panel according to claim 9, wherein the potential capture unit comprises a second transistor and a first storage capacitor, two ends of the second transistor are respectively electrically connected to the third node and a first plate of the first storage capacitor, and a second plate of the first storage capacitor receives a fixed potential signal;

the control end of the second transistor receives a potential capture control signal, and the second transistor is used for being conducted in the capture time period under the control of the potential capture control signal;

the potential writing unit comprises a third transistor, two ends of the third transistor are respectively and electrically connected with the second node and the first polar plate of the first storage capacitor, a control end of the third transistor receives a potential writing control signal, and the third transistor is used for being conducted in the writing time period under the control of the potential writing control signal.

11. The display panel according to claim 10,

when the reset module comprises the double-gate transistor, the third transistor is also used for being turned off in the second sub-stage under the control of the potential writing control signal;

when the compensation module comprises the double-gate transistor, the third transistor is also used for being switched off in the second sub-phase under the control of the potential writing control signal.

12. The display panel according to claim 10, wherein the second plate of the first storage capacitor is electrically connected to a cathode of the light-emitting element.

13. The display panel according to claim 9, wherein the display panel includes a plurality of pixel circuits arranged in order in a row direction and a column direction, respectively;

and the clamping modules in all the pixel circuits or the pixel circuits in the same row share the same potential grabbing unit.

14. The display panel according to claim 1, wherein the pixel circuit further comprises a compensation module for detecting and self-compensating a deviation of the threshold voltage of the driving transistor in the second sub-phase;

the display panel comprises a first working mode, and the first working mode comprises a writing frame and a holding frame;

in the writing frame, the non-emission phase of the pixel circuit includes a third sub-phase; in the third sub-phase, the compensation module is conducted;

the pixel circuit compensation module is normally-off during the non-emission period in the hold frame.

15. The display panel according to claim 1, wherein the pixel circuit further comprises an anode initialization module connected between an anode initialization signal terminal and an anode of the light emitting element;

the control end of the anode initialization module receives an anode initialization signal, and the anode initialization module resets the anode of the light-emitting element under the control of the anode initialization signal;

the anode initialization signal is multiplexed into the clamp control signal.

16. The display panel according to claim 1, wherein the non-emission phase includes a clamp period during which the clamp module is turned on;

in the time dimension, the non-light-emitting stage lasts from the light-emitting termination time point to the next light-emitting starting time point; the distance between the clamping time period and the light-emitting starting time point of the non-light-emitting stage is greater than the distance between the clamping time period and the light-emitting ending time point of the non-light-emitting stage.

17. The display panel according to claim 2, wherein the non-emission phase comprises a clamp period and a second sub-phase; within the clamping time period, the clamping module is conducted; in the second sub-phase, the first sub-transistor and the second sub-transistor are both turned on;

the clamping time period has a duration T1 satisfying: t2 is more than or equal to T1 and more than or equal to T3-T2;

wherein, T2 is the duration of the second sub-phase, and T3 is the duration of the non-light-emitting phase.

18. A display device comprising the display panel according to any one of claims 1 to 17.