KR20210083918A - Electroluminescent display device - Google Patents

Abstract

The present invention is to provide a method capable of reducing the size of a gate-in-panel (GIP) driving circuit and accordingly, reducing the width of a bezel. The present invention provides an electroluminescent display device which includes: a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, and a light emitting diode; and a scan driver including a first gate driving circuit for outputting a first gate signal to a first gate line connected to the first switching transistor.

Description

Electroluminescent display device

The present invention relates to an electroluminescent display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, an organic light emitting diode (OLED) display device and a quantum dot light emitting device (QLED: Quantum Dot Light) are increasing. Various flat display devices such as an electroluminescence display device including an emitting-diode display device and a micro-LED (Micro-Light Emitting Diode) display device are being utilized. .

Among these flat panel display devices, the electroluminescent display device has advantages of miniaturization, weight reduction, thinness, and low power driving, and thus is widely used.

In recent years, an electroluminescent display device capable of low power consumption and high-speed operation has been demanded. To this end, a transistor using polysilicon and a transistor using an oxide semiconductor are formed together in the pixel to configure the pixel with an internal compensation structure.

However, as such heterogeneous transistors are used, the size of a driving circuit configured in a gate in panel (GIP) method increases to drive them, and accordingly, the width of a bezel of the display device increases.

An object of the present invention is to provide a method capable of reducing the size of the GIP driving circuit and thus reducing the width of the bezel.

In order to achieve the above object, the present invention provides a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, and a light emitting diode, and a first switching transistor An electroluminescent display device including a scan driver including a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to a transistor can be provided. In addition, the first gate driving circuit is a control circuit including a Q transistor including P-type or N-type polysilicon, a Qb transistor including an N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. It may include a stage configured to include.

The pixel may further include a first switching transistor including the P-type or N-type polysilicon on the substrate.

The control circuit of the stage includes a first transistor including P-type or N-type polysilicon and receiving the first gate signal output from the previous stage, and P-type or N-type polysilicon between the first transistor and the Q node. It may include a second transistor connected to the gate to which a low voltage is applied.

The control circuit of the stage further includes a fourth transistor including an N-type oxide semiconductor and having a gate connected to the Q node, and a third transistor including a P-type or N-type polysilicon and connected between the fourth transistor and the first transistor. may include

The control circuit of the stage includes a fifth transistor including P-type or N-type polysilicon and connected between the Q node and the gate of the Qb transistor, and an N-type oxide semiconductor, the source receiving the second high voltage and the drain may further include a sixth transistor connected to the gate of the Qb transistor. In addition, the second high voltage may be higher than the first high voltage input to the Qb transistor.

The control circuit of the stage includes a seventh transistor including an N-type oxide semiconductor, a gate connected to the drain of the first transistor, a source applied with a second high voltage, and a drain connected to the source of the second transistor, and a P-type or an eighth transistor comprising N-type polysilicon, the gate and the source connected to the drain of the first transistor and the drain connected to the source of the second transistor, the second high voltage being input to the Qb transistor It may be higher than the first high voltage.

The control circuit of the stage may further include an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.

The scan driver further includes a second gate driver circuit for outputting a second gate signal to a second gate line connected to the second switching transistor, wherein the second gate driver circuit includes a Q transistor including P-type or N-type polysilicon. and a Qb transistor including an N-type oxide semiconductor, a control circuit including a Q node to which the Q transistor and the gates of the Qb transistor are commonly connected, and an inverter connected to an output node between the Q transistor and the Qb transistor. may include.

The pixel includes a P-type or N-type polysilicon and further includes a light emitting transistor for controlling the emission timing of the light emitting diode, and the scan driver further includes a light emitting driving circuit for outputting a light emitting signal to a light emitting line connected to the light emitting transistor and a control circuit including a Q transistor including P-type or N-type polysilicon, a Qb transistor including an N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are commonly connected. It may include a stage configured to include.

The pixel further includes an initialization transistor including P-type or N-type polysilicon, a gate connected to a first gate wiring connected to a pixel in a previous row line, and an initialization transistor connected to a drain connected to a second switching transistor, and the scan driver includes: An initialization driving circuit for outputting an initialization signal to an initialization line connected to the source of the transistor may be further included.

The scan driver may be formed on the substrate in a GIP manner.

The electroluminescent display device may be driven by a variable frequency driving method.

In another aspect, the present invention provides a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, and a light emitting diode; a scan driver including a second gate driving circuit for outputting a second gate signal to a second gate wiring connected to the second switching transistor, wherein the second gate driving circuit is a Q transistor including P-type or N-type polysilicon and a Qb transistor including an N-type oxide semiconductor, a control circuit including a Q node to which the Q transistor and the gates of the Qb transistor are commonly connected, and an inverter connected to an output node between the Q transistor and the Qb transistor. Including, the control circuit of the stage includes a first transistor including a P-type or N-type polysilicon and receiving a signal output from an output node between the Q transistor and the Qb transistor of the previous stage, and a P-type or N-type polysilicon Provided is an electroluminescence display including silicon and connected between a first transistor and a Q node and including a second transistor to which a gate is applied with a low voltage.

A first switching transistor including P-type or N-type polysilicon on the substrate may be further included.

The control circuit of the stage includes: a fourth transistor including an N-type oxide semiconductor and having a gate connected to a Q node; A third transistor including P-type or N-type polysilicon and connected between the fourth transistor and the first transistor may be further included.

The control circuit of the stage includes: a fifth transistor including P-type or N-type polysilicon and connected between the Q node and the gate of the Qb transistor; and a sixth transistor including an N-type oxide semiconductor, the source receiving a second high voltage and the drain further comprising a sixth transistor connected to the gate of the Qb transistor, wherein the second high voltage is higher than the first high voltage input to the Qb transistor can be high

The control circuit of the stage includes: a seventh transistor including an N-type oxide semiconductor, a gate connected to a drain of the first transistor, a source applied with a second high voltage, and a drain connected to the source of the second transistor; An eighth transistor comprising P-type or N-type polysilicon, the gate and the source are connected to the drain of the first transistor, and the drain is connected to the source of the second transistor, and the second high voltage is applied to the Qb transistor. It may be higher than the input first high voltage.

The control circuit of the stage may further include an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.

The scan driver further includes a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to the first switching transistor, wherein the first gate driving circuit includes a Q transistor including P-type or N-type polysilicon and a stage including a control circuit including a Qb transistor including an N-type oxide semiconductor and a Q node to which the Q transistor and the gate of the Qb transistor are commonly connected.

The pixel includes a P-type or N-type polysilicon and further includes a light emitting transistor for controlling the emission timing of the light emitting diode, and the scan driver further includes a light emitting driving circuit for outputting a light emitting signal to a light emitting line connected to the light emitting transistor and a control circuit including a Q transistor including P-type or N-type polysilicon, a Qb transistor including an N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are commonly connected. It may include a stage configured to include.

The pixel further includes an initialization transistor including P-type or N-type polysilicon, the gate connected to the first gate wiring connected to the pixel of the previous row line, the source connected to the initialization wiring, and the drain connected to the second switching transistor and the scan driving unit may further include an initialization driving circuit for outputting an initialization signal to the initialization line.

The scan driver may be formed on the substrate in a GIP manner.

The electroluminescent display device may be driven by a variable frequency driving method.

In another aspect, the present invention provides a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, a light emitting diode, and a light emitting transistor for controlling the light emission timing of the light emitting diode a pixel comprising; a scan driver including a light emitting driving circuit for outputting a light emitting signal to a light emitting wiring connected to the light emitting transistor, wherein the light emitting driving circuit includes a Q transistor including P-type or N-type polysilicon and a Qb transistor including an N-type oxide semiconductor and a stage including a control circuit having a Q node to which gates of a Q transistor and a Qb transistor are commonly connected.

The control circuit of the stage may include a first transistor including P-type or N-type polysilicon and receiving the light emitting signal output from the previous stage.

The control circuit of the stage may further include a second transistor including P-type or N-type polysilicon, a gate and a drain connected to a Q node, and a source receiving a low voltage.

The control circuit of the stage may further include a third transistor including P-type or N-type polysilicon, connected between the first transistor and the Q node, and a gate to which a low voltage is applied.

The control circuit of the stage may further include an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.

The scan driver further includes a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to the first switching transistor, wherein the first gate driving circuit includes a Q transistor including P-type or N-type polysilicon and a stage including a control circuit including a Qb transistor including an N-type oxide semiconductor, and a Q node to which the Q transistor and the Qb transistor gate are connected in common.

The scan driver further includes a second gate driver circuit for outputting a second gate signal to a second gate line connected to the second switching transistor, wherein the second gate driver circuit includes a Q transistor including P-type or N-type polysilicon. and a Qb transistor including an N-type oxide semiconductor, a control circuit including a Q node to which the Q transistor and the gates of the Qb transistor are commonly connected, and an inverter connected to an output node between the Q transistor and the Qb transistor. may include.

The pixel further includes an initialization transistor including P-type or N-type polysilicon, a gate connected to a first gate wiring connected to a pixel in a previous row line, and an initialization transistor connected to a drain connected to a second switching transistor, and the scan driver includes: An initialization driving circuit for outputting an initialization signal to an initialization line connected to the source of the transistor may be further included.

The scan driver may be formed on the substrate in a GIP manner.

The electroluminescent display device may be driven by a variable frequency driving method.

A first switching transistor including P-type or N-type polysilicon may be further included on the substrate.

The light emitting transistor may include and include P-type or N-type polysilicon.

In the present invention, in the scan driver of the GIP method, the corresponding Q transistor and the Qb transistor are of the opposite type with respect to at least one of the driving circuits outputting the gate signal and the light emission signal as the corresponding scan signals. As the semiconductor material of the P-type or N-type polysilicon and N-type oxide semiconductor may be used.

Accordingly, since the Q transistor and the Qb transistor can be driven by sharing the Q node, the transistor and the capacitor, which are driving elements for realizing the Qb node, can be eliminated.

Accordingly, it is possible to reduce the number of driving elements constituting the corresponding driving circuit, thereby reducing the size of the GIP-type scan driving unit and reducing the width of the bezel of the display device.

1 is a block diagram schematically showing an electroluminescent display device according to a first embodiment of the present invention;
2 is a circuit diagram illustrating an example of a pixel structure of an electroluminescent display device according to a first embodiment of the present invention;
3 is a block diagram schematically showing the configuration of a GIP-type scan driver of the electroluminescent display device according to the first embodiment of the present invention.
4 is a circuit diagram schematically showing a first structure of a first gate driving circuit according to a first example of the first embodiment of the present invention;
5 is a circuit diagram schematically showing a second structure of a first gate driving circuit according to a second example of the first embodiment of the present invention;
6 is a circuit diagram schematically showing a third structure of a first gate driving circuit according to a third example of the first embodiment of the present invention;
7 is a circuit diagram schematically showing a fourth structure of a first gate driving circuit according to a fourth example of the first embodiment of the present invention;
Fig. 8 is a waveform diagram showing simulation results for the gate signal output of the first gate driving circuit having the structures of the first and second examples of the first embodiment of the present invention;
Fig. 9 is a waveform diagram showing simulation results for the gate signal output of the first gate driving circuit having the structures of the third and fourth examples of the first embodiment of the present invention;
Fig. 10 is a circuit diagram schematically showing a first structure of a second gate driving circuit according to a first example of a second embodiment of the present invention;
11 is a circuit diagram schematically showing a second structure of a second gate driving circuit according to a second example of the second embodiment of the present invention;
12 is a circuit diagram schematically showing a third structure of a second gate driving circuit according to a third example of the second embodiment of the present invention;
13 is a circuit diagram schematically showing a fourth structure of a second gate driving circuit according to a fourth example of the second embodiment of the present invention;
Fig. 14 is a circuit diagram schematically showing a first structure of a light emission driving circuit according to a first example of a third embodiment of the present invention;
Fig. 15 is a circuit diagram schematically showing a second structure of a light emission driving circuit according to a second example of the third embodiment of the present invention;
Fig. 16 is a circuit diagram schematically showing a third structure of a light emission driving circuit according to a third example of the third embodiment of the present invention;
Fig. 17 is a waveform diagram showing simulation results for light emission signal output of the light emission driving circuit having the structures of the first to third examples of the third embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First embodiment>

1 is a block diagram schematically showing an electroluminescent display device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a pixel structure of the electroluminescent display device according to the first embodiment of the present invention. 3 is a block diagram schematically showing the configuration of a GIP type scan driver of the electroluminescent display device according to the first embodiment of the present invention.

Referring to FIG. 1 , an electroluminescent display device 10 according to the present embodiment includes a display panel 100 in which a plurality of pixels P are arranged in a matrix form, and a panel driving circuit for driving the display panel 100 . may include.

Here, the panel driving circuit for driving the display panel 110 may include a data driver 200 , a scan driver 300 , and a timing controller 400 .

Meanwhile, the electroluminescent display device 10 of the present embodiment may be an electroluminescent display device that operates in a variable refresh rate (VRR) driving method (ie, a variable frequency driving method) in which a driving frequency is varied according to a display image.

In this regard, for example, when displaying a general image in which a change of an image is general, the electroluminescent display device 10 may be driven in a general mode of a driving frequency of, for example, 60 Hz as a general driving frequency.

In addition, when displaying a high-speed image having a larger image change than a general image, the electroluminescent display device 10 may be driven in a high-speed mode with a higher frequency than a general driving frequency. In this regard, for example, the high frequency driving frequency greater than the general driving frequency may be 120 Hz or the like as a multiple of 60 Hz, which is the general driving frequency.

When driven at a high frequency in this way, it is possible to realistically display a rapidly changing image by minimizing actual distortion.

In addition, in the case of displaying a low-speed image or a still image having a smaller image change than a general image, the electroluminescent display device 10 may be driven in a low-speed mode with a small general driving frequency and low frequency. In this regard, the driving frequency of the low frequency, which is smaller than the general driving frequency, may be 30 Hz, 20 Hz, 15 Hz, 12 Hz, 10 Hz, 6 Hz, 1 Hz, etc. as a divisor of 60 Hz, which is a general driving frequency.

When driving at a low frequency as described above, power consumption can be reduced without substantially degrading image quality.

In the VRR driving method of this embodiment, as the driving frequency is changed, a frame displaying an image, that is, a refresh frame in which a data signal is written to the pixel P of the display panel 100 to refresh the image display. The number is changed to correspond to the changed driving frequency.

In this regard, for example, in driving the electroluminescence display 10 of the present embodiment in the VRR method, it is assumed that the highest driving frequency among a plurality of variable driving frequencies is 120 Hz.

At this time, when driving at 120 Hz, which is the highest driving frequency, 120 refresh frames equal to the driving frequency are generated for 1 second, which is a unit time. Meanwhile, 120 refresh frames may exist continuously.

And, when the driving frequency is lower than the maximum driving frequency, the same number of refresh frames as the corresponding driving frequency is generated for 1 second. For example, in the case of a normal driving frequency of 60 Hz, 60 refresh frames are generated.

As such, when driving at a lower driving frequency than the highest driving frequency, the refresh frames are not continuous with each other, and no refresh operation is performed between neighboring frames, and a blank section (or holding) that is a stopped (or stopped) section. (holding) period) can be set. That is, the refresh operation may be driven to be skipped during the blank period.

As described above, as the driving frequency is varied in the VRR driving method, the number of refresh frames is varied to correspond to the driving frequency.

Referring to the display panel 100 , various signal wirings for transmitting driving signals for driving the pixels P are formed on the display panel 100 .

In this regard, for example, a plurality of data lines DL for transmitting a data signal, which is an image signal, may extend along each column line direction (or a second direction) to be connected to the pixels P of the corresponding column line.

The gate wirings GL1 and GL2 that transmit the gate signal may extend along each row line direction (or the first direction) to be connected to the pixel P of the corresponding row line.

Meanwhile, in the present exemplary embodiment, first and second gate wirings GL1 and GL2 that are two different gate wirings GL1 and GL2 may be disposed on each row line.

In contrast, as will be described later, heterogeneous transistors having different semiconductor layer forming materials may be provided in each pixel P, so that the first and second gate signals are transmitted to individually switch the different types of transistors. The first and second gate lines GL1 and GL2 may be disposed on each row line.

In addition, a light emitting line EL extending along each row line direction parallel to the gate line GL and transmitting a light emitting signal may be connected to the pixel of the corresponding row line P.

Also, an initialization line IL extending in parallel to the gate line GL along each row line direction to transmit an initialization signal may be connected to the pixel of the corresponding row line P.

The timing controller 400 controls driving timings of the data driver 200 and the scan driver 300 .

In this regard, the timing controller 400 may process the digital data signal Da input from the external system to match the optical characteristics of the display panel 100 and supply it to the data driver 200 .

In addition, the timing controller 400 drives the data driver 200 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data enable signal DE. A data control signal DCS for controlling timing and a scan control signal SCS for controlling driving timing of the scan driver 300 may be generated.

The data driver 200 may drive the data line DL. In this regard, the data driver 200 may convert the digital data signal Da into an analog data signal during the refresh frame based on the data control signal DCS and supply it to the corresponding data line DL.

On the other hand, as a driving frequency at which a blank section exists between adjacent refresh frames, for example, when driving a normal driving frequency or a low frequency driving frequency, the output of the data driver 200 is turned off during the blank section, so that the data signal is It may not be output to the display panel 100 . Accordingly, during the blank period, the refresh operation on the display panel 100 may not be performed and may be skipped.

The scan driver 300 may output and drive corresponding scan signals to the gate wirings GL1 and GL2, the light emitting wiring EL, and the initialization wiring IL connected thereto.

In this regard, the scan driver 300 may generate, for example, a gate signal, an emission signal, and an initialization signal as scan signals based on the scan control signal SCS during the refresh frame. The scan driver 300 may output each of the first and second gate signals to the corresponding first and second gate wirings GL1 and GL2 in a line sequential manner. In addition, the light emitting signal may be output to the light emitting line EL in a line sequential manner. Also, the initialization signal may be output to the initialization line IL in a line sequential manner.

On the other hand, when driving the driving frequency in which the blank section exists, the gate signal output of the scan driver 300 is turned off during the blank section, so that the gate signal may not be output to the display panel 100 . Similarly, during the blank period, the initialization signal output of the scan driver 300 may be turned off, so that the gate signal may not be output to the display panel 100 .

And, during the blank period, the output of the light emission signal of the scan driver 300 may be in an on state. In this regard, for example, the turn-on level state of the light emitting signal in the refresh frame immediately before the blank period may be continuously maintained. As another example, the output of the emission signal may be generated at substantially the same timing as that of the output of the emission signal in the refresh frame.

According to the operation of the scan driver 300 in the blank section, the refresh operation in the display panel 100 is not performed and can be skipped during the blank section.

The scan driver 300 may be directly formed on the array substrate of the display panel 100 by a gate in panel (GIP) method.

A detailed configuration and operation of the scan driver 300 will be described in more detail below.

An example of the configuration of driving elements configured in the pixel P of the display panel 100 will be described with reference to FIG. 2 together.

In FIG. 2 , for convenience of explanation, a pixel having a 7T1C structure is illustrated as an example, and a row line in which the pixel is disposed is referred to as an n-th row line.

Referring to FIG. 2 , an internal compensation structure may be applied to the pixel P of this embodiment to compensate for the threshold voltage of the driving transistor T2 .

In contrast, in each pixel P, as driving elements, the first switching transistor T1, the driving transistor T2, the second switching transistor T3, the first and second light emitting transistors T4, T5, and the first, Two initialization transistors T6 and T7 and a storage capacitor Cst may be provided, and a light emitting diode OD as a light emitting device may be provided.

The first switching transistor T1 is turned on in response to the first gate signal applied through the first gate wiring GL1(n) of the n-th row line, which is the corresponding row line, and thus is turned on through the data line DL. The provided data signal can be applied to the driving transistor T2.

The source of the first switching transistor T1 is connected to the data line DL, the gate is connected to the first gate line GL1(n), and the drain is the source of the driving transistor T2, that is, the third node. (N3) can be connected.

The driving transistor T2 controls the emission current applied to the light emitting diode OD by the gate-source voltage. The gate of the driving transistor T2 may be connected to the first node N1 , and the drain may be connected to the second node N2 .

The first initialization transistor T6 is turned on in response to the first gate signal applied through the first gate wiring GL1(n-1) of the n−1th row line, which is the previous row line, and thus the initialization wiring ( The initialization signal transmitted through IL(n) may be applied to the second node N2.

Here, the initialization signal applied through the first initialization transistor T6 has an initialization voltage for initializing the gate of the driving transistor T2, and the initialization voltage may be a low-level voltage. The gate of the first initialization transistor T6 as described above is connected to the first gate wiring GL1(n-1) of the previous row line, the source is connected to the initialization wiring IL(n), and the drain is connected to the second It may be connected to the node N2.

The second initialization transistor T7 is turned on in response to the first gate signal applied through the first gate wiring GL1(n) of the n-th row line, which is the current row line, and thus the initialization voltage Vi emits light. It can be applied to the first electrode (or anode) of the diode OD, that is, the fourth node N4. The gate of the second initialization transistor T7 is connected to the first gate wiring GL1(n) of the current row line, the source is connected to the power supply line transmitting the initialization voltage Vi, and the drain is the fourth It may be connected to the node N4. Here, the initialization voltage Vi may be a low-level voltage, and may be the same as or different from the initialization voltage of the initialization signal.

The first light emitting transistor T4 includes a power supply line that transmits a first power voltage VDD (or a high potential driving voltage) in response to a light emitting signal applied through the light emitting line EL(n) of the corresponding row line; A current path between the driving transistors T2 may be controlled. The gate of the first light emitting transistor T4 is connected to the light emitting line EL(n) of the corresponding row line, the source is connected to the power line transmitting the first driving voltage VDD, and the drain is the driving transistor It may be connected to the source of (T2), that is, the third node (N3).

The second light emitting transistor T5 may control the current path between the light emitting diode OD and the driving transistor T2 in response to the light emitting signal applied through the light emitting line EL(n) of the corresponding row line. The gate of the second light emitting transistor T5 is connected to the light emitting line EL(n) of the corresponding row line, and the drain is connected to the first electrode of the light emitting diode OD, that is, the fourth node N4, The source may be connected to the drain of the driving transistor T2 , that is, the second node N2 .

The light emitting diode OD may be, for example, a light emitting diode formed of an organic material, and emits light by a light emitting current supplied from the driving transistor T2 . The first electrode of the light emitting diode OD may be connected to the fourth node N4 , and the second electrode (or cathode) may receive a second power supply voltage VSS (or a low potential driving voltage).

The second switching transistor T3 is connected between the gate and the drain of the driving transistor T2 (ie, between the first node N1 and the second node N2) in a diode connection method, and thus the driving transistor T2 ) may be sampled at the gate of the driving transistor T2. Also, the initialization signal applied to the second node N2 may be applied to the gate of the driving transistor T2 through the second switching transistor T3 to be initialized. As such, initialization of the driving transistor T2 and threshold voltage sampling may be performed through the second switching transistor T3 .

The gate of the second switching transistor T3 may be connected to the second gate wiring GL2(n) of the corresponding row line.

The storage capacitor Cst may be connected between the first node N2 and a power supply line of the first power voltage VDD. The storage capacitor Cst may store and maintain the voltage applied to the gate of the driving transistor T2 until the next refresh frame.

As described above, in the plurality of transistors T1 to T7 provided in each pixel P, an oxide semiconductor having excellent off-current characteristics may be used as a semiconductor layer for some of these transistors, and the remaining transistors may have mobility. Polysilicon having excellent characteristics may be used as the semiconductor layer.

In this regard, for example, the second switching transistor T3 connected to the gate of the driving transistor T2 (or connected to the first node N1 ) may be formed using an oxide semiconductor.

In this case, it is possible to effectively prevent leakage of the gate voltage of the driving transistor T2. Accordingly, the gate voltage of the driving transistor T2 may be stably maintained during a relatively long blank period in the low frequency mode, thereby effectively securing image quality characteristics in the low frequency mode.

As described above, the second switching transistor T3 using the oxide semiconductor may be configured as an N-type transistor.

Meanwhile, among transistors different from the second switching transistor T3 , at least some transistors including the driving transistor T2 may use a polysilicon semiconductor layer.

In contrast, in the present embodiment, as six transistors different from the second switching transistor T3, the first switching transistor T1, the driving transistor T2, the first and second light-emitting transistors T4, T5, and the first The case where all of the ,2 initialization transistors T6 and T7 are made of polysilicon is taken as an example.

As described above, the transistors T1 , T2 , T4 to T7 using polysilicon may be configured as P-type transistors. However, the present invention is not limited thereto, and the polysilicon transistors T1 , T2 , T4 to T7 are not limited thereto. may be composed of an N-type transistor.

As described above, when heterogeneous transistors having different semiconductor materials are formed in the pixel P, VRR driving can be effectively implemented.

As such, as the heterogeneous transistors are provided, the scan driver 300 may include a plurality of driving circuits that provide scan signals for driving the heterogeneous transistors.

In this regard, referring to FIG. 3 together, the scan driver 300 may include first and second gate driving circuits GC1 and GC2 , a light emission driving circuit EC, and an initialization driving circuit VIC.

The first gate driving circuit GC1 corresponds to a scan circuit that generates the first gate signal Vg1 to drive the first gate wiring GL1 of each row line.

Such a first gate driving circuit GC1 may include a plurality of stages corresponding to each of a plurality of row lines, and each stage corresponds to a first gate wiring GL1 of a corresponding row line connected to an output terminal thereof. One gate signal Vg1 may be output.

As described above, the first gate signal Vg1 transmitted through the first gate line GL1 is a transistor made of polysilicon in the pixel P of the corresponding row line, for example, a P-type first switching transistor T1 and It may be applied to the second initialization transistor T7. As another example, the first gate signal Vg1 transmitted through the first gate line GL1 may include an N-type first switching transistor T1 and a second initialization transistor made of polysilicon in the pixel P of the corresponding row line. (T7) can be applied.

Meanwhile, as another P-type transistor made of polysilicon in the pixel P of the current row line, for example, the first initialization transistor T6 is connected to the first gate wiring GL1 of the previous row line and is connected to the previous row line. of the first gate signal Vg1 may be applied. As another example, the first initialization transistor T6 made of N-type polysilicon may be connected to the first gate line GL1 of the previous row line to receive the first gate signal Vg1 of the previous row line.

As such, the first gate driving circuit GC1 may control the operation of the transistors T1 , T6 , and T7 formed of P-type or N-type polysilicon.

The second gate driving circuit GC2 corresponds to a scan circuit that generates the second gate signal Vg2 to drive the second gate wiring GL2 of each row line.

Such a second gate driving circuit GC2 may include a plurality of stages corresponding to each of a plurality of row lines, and each stage corresponds to a second gate wiring GL2 of a corresponding row line connected to an output terminal thereof. A two-gate signal Vg2 may be output.

As described above, the second gate signal Vg2 transmitted through the second gate line GL2 is a transistor composed of an oxide semiconductor in the pixel P of the corresponding row line, for example, to the N-type second switching transistor T3. can be authorized

As such, the second gate driving circuit GC2 may control the operation of the transistor T3 formed of the N-type oxide semiconductor.

The light emission driving circuit EC corresponds to a scan circuit that generates a light emission signal Vem to drive the light emission wiring EL of each row line.

Such a light emission driving circuit EC may include a plurality of stages corresponding to each of a plurality of row lines, and each stage receives a light emission signal Vem from a light emission line EL of a corresponding row line connected to an output terminal thereof. can be printed out.

As described above, the light emitting signal Vem transmitted through the light emitting line EL is a transistor made of P-type or N-type polysilicon in the pixel P of the corresponding row line, for example, the first and second light emitting transistors T4, T5) can be applied.

As such, the light emission driving circuit EC may control the operation of the transistors T4 and T5 using P-type or N-type polysilicon.

The initialization driving circuit VIC corresponds to a scan circuit that generates an initialization signal DVi to drive the initialization line IL of each row line.

The initialization driving circuit EC may include a plurality of stages corresponding to each of a plurality of row lines, and each stage receives an initialization signal DVi to an initialization line IL of a corresponding row line connected to an output terminal thereof. can be printed out.

As described above, the initialization signal DVi transmitted through the initialization line IL is a transistor made of polysilicon in the pixel P of the corresponding row line and is applied to, for example, the P-type or N-type first initialization transistor T6. can be The initialization signal applied as described above may be transmitted to the second switching transistor T3 and may be applied to the gate of the driving transistor T2 when it is turned on.

As such, the initialization driving circuit VIC may implement initialization for the gate of the driving transistor T2 connected to the transistor T3 formed of an N-type oxide semiconductor.

As described above, in the present embodiment in which the pixel P is composed of heterogeneous transistors, a driving circuit needs to be added to the scan driver 300 compared to the case in which the pixel P is composed of the same type of transistor, for example, a polysilicon transistor. .

In contrast, when all the transistors in the pixel P are made of the same P-type or N-type polysilicon, one gate driving circuit and one light emission driving circuit are required.

On the contrary, when the second switching transistor T3 in the pixel P is formed of an N-type oxide semiconductor as in the present embodiment, the gate driving circuit GC2 for controlling the switching operation of the second switching transistor T3 ) is additionally required, and an initialization driving circuit VIC that provides an initialization signal DVi for initialization of the driving transistor T2 connected to the second switching transistor T3 is additionally required.

As such, when heterogeneous transistors are used in the pixel P, an additional driving circuit is required for the scan driver 300 . Accordingly, the area of the scan driver 300 may increase and the width of the bezel may increase.

To improve this, in the present embodiment, the number of driving elements used in the first gate driving circuit GC1 is reduced. Accordingly, the size of the scan driver 300 can be reduced and the width of the bezel of the electroluminescent display device 10 can be reduced.

The first gate driving circuit GC1 will be described in more detail below.

In this embodiment, a driving circuit having four structures is proposed as the first gate driving circuit GC1 , and each of the four structures will be described with reference to related drawings.

4 is a circuit diagram schematically showing a first structure of a first gate driving circuit according to a first example of the first embodiment of the present invention.

In FIG. 4 , for convenience of explanation, a stage corresponding to the first gate wiring GL1(n) of the n-th row line as one of a plurality of stages constituting the first gate driving circuit GC1 ( GC1_STG(n)) is shown.

Referring to FIG. 4 , in the first gate driving circuit GC1 of the first example of this embodiment configured with the first structure, a stage GC1_STG(n) thereof includes a Q transistor Tgc1_q and a Qb transistor Tgc1_qb and , a control circuit GC1_CC for controlling switching operations of the Q transistor Tgc1_q and the Qb transistor Tgc1_qb may be included.

The Q transistor Tgc1_q may be operable to output the first gate signal Vg1(n) of a low voltage as an on voltage to the corresponding first gate line GL(n). .

The Q transistor Tgc1_q may be configured using P-type or N-type polysilicon.

The source of the Q transistor Tgc1_q may receive the first gate clock CGLKgc1_1 among the gate clocks GCLKgc1_1 and GCLKgc1_2 input to the stage GC1_STG(n). The drain of the Q transistor Tgc1_q may be connected to the output node Ngc1_o of the stage GC1_STG(n), that is, it may be connected to the output node Ngc1_o between the Q transistor Tgc1_q and the Qb transistor Tgc1_qb.

The Qb transistor Tgc1_qb connected in series with the Q transistor Tgc1_q is an off voltage to the corresponding first gate line GL(n), for example, a high voltage VGH gate signal Vg1( n)).

The Qb transistor Tgc1_qb may be formed using an N-type oxide semiconductor.

A drain of the Qb transistor Tgc1_qb may be connected to the output node Ngc1_o of the stage GC1_STG(n). A source of the Qb transistor Tgc1_qb may be configured to receive a high voltage VGH (or a gate high voltage).

As described above, the Q transistor Tgc1_q may be formed of P-type or N-type polysilicon in the same manner as the P-type or N-type transistor in the pixel P. That is, the Q transistor Tgc1_q may be formed in the same manner in the process of forming the P-type or N-type polysilicon transistor in the pixel P.

Also, the Qb transistor Tgc1_qb may be formed of an N-type oxide semiconductor in the same manner as the N-type transistor in the pixel P. That is, the Qb transistor Tgc1_qb may be formed in the same manner in the process of forming the transistor of the N-type oxide semiconductor in the pixel P.

As described above, since the Q transistor Tgc1_q and the Qb transistor Tgc1_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc1_q and the Qb transistor Tgc1_qb are out of phase with each other through the same control signal. can be switched to In this regard, when the control signal is a low voltage, the Q transistor Tgc1_q is turned on, on the contrary, the Qb transistor Tgc1_qb is turned off, and when the control signal is a high voltage, the Q transistor Tgc1_q is turned off. Conversely, the Qb transistor Tgc1_qb is turned on.

Accordingly, the Q transistor Tgc1_q and the Qb transistor Tgc1_qb do not need to separately receive control signals whose phases are 180 degrees opposite to each other in order to control their respective switching, and one (or a single) control signal can be configured to share.

Accordingly, the control circuit GC1_CC may be configured to output one control signal capable of simultaneously controlling the Q transistor Tgc1_q and the Qb transistor Tgc1_qb in common. That is, the control circuit GC1_CC may be configured to include, for example, the Q node Ngc1_q as one control node, without having to separately include the Q node and the Qb node as the control node (or output node). .

As described above, since it is sufficient for the control circuit GC1_CC to include one Q node Ngc1_q as a control node, the circuit configuration in the control circuit GC1_CC can be simplified, so that the size of the first gate driving circuit GC1 is increased. can be reduced.

In this regard, when the Q transistor Tgc1_q and the Qb transistor Tgc1_qb are the same type of transistor, individual Q signals and Qb signals output to the Q node and the Qb node must be generated, so that a relatively large number of driving devices are required. is required

On the other hand, as in the present embodiment, the control circuit CC only needs to generate a Q signal that is one control signal output to one Q node Ngc1_q, so a relatively small number of driving elements is required. Accordingly, the size of the first gate driving circuit GC1 may be reduced, and accordingly, the size of the GIP-type scan driver 300 including the same may be reduced, thereby reducing the width of the bezel of the display device. there will be

Such a control circuit GC1_CC may include two first and second transistors Tgc1_1 and Tgc1_2 and one capacitor Cgc1_q.

Here, the first and second transistors Tgc1_1 and Tgc1_2 may be formed of, for example, P-type or N-type polysilicon.

The first transistor Tgc1_1 may be configured such that its gate receives the second gate clock GCLKgc1_2 from among the gate clocks GCLKgc1_1 and GCLKgc1_2 input to the stage GC1_STG(n). The source of the first transistor Tgc1_1 may be configured to receive the first gate signal Vg1(n-1) output from the previous stage. A drain of the first transistor Tgc1_1 may be configured to be connected to a source of the second transistor Tgc1_2 .

The second transistor Tgc1_2 is a bridge voltage transistor and is connected between the first transistor Tgc1_1 and the Q node Ngc1_q. The source of the second transistor Tgc1_2 is connected to the drain of the first transistor Tgc1_1, the drain of the second transistor Tgc1_2 is connected to the Q node Ngc1_q, and the gate of the second transistor Tgc1_2 has a low voltage. (VGL) may be configured to be authorized.

The second transistor Tgc1_2 continuously maintains an on state by the low voltage VGL. Accordingly, since the electrical connection between the first transistor Tgc1_1 and the Q node Ngc1_q can be maintained, the output voltage of the first transistor Tgc1_1 and the voltage of the Q node Nq can be maintained substantially the same. have.

The capacitor Cgc1_q may be connected between the Q node Ngc1_q and the output node No to store the voltage of the Q node Ngc1_q.

As described above, the control circuit GC1_CC of the first gate driving circuit GC1 of the first structure is a driving device for driving the Q node Ngc1_q, and includes two first and second transistors Tgc1_1 and Tgc1_2 and one capacitor. It may be composed of (Cgc1_q).

As such, it is possible to configure the control circuit GC1_CC using a very small number of driving elements, so that the size of the first gate driving circuit GC1 can be significantly reduced.

In this regard, a stage having a structure having both a Q node and a Qb node is composed of approximately 8 to 10 transistors and 2 capacitors.

On the other hand, the stage GC1_STG(n) of the first structure according to the first example of the present embodiment does not include the Qb node, and thus a transistor constituting the Qb node can be removed.

Accordingly, in the first gate driving circuit GC1 having the first structure of the present embodiment, the number of driving elements thereof can be significantly reduced and can be substantially minimized.

5 is a circuit diagram schematically showing a second structure of a first gate driving circuit according to a second example of the first embodiment of the present invention.

The stage GC1_STG(n) of the second structure according to the second example of the present embodiment shown in FIG. 5 is compared to the stage GC1_STG(n) of the first structure according to the first example of the present embodiment in FIG. 4 . , a transistor is added, so that the voltage of the Q node Ngc1_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 5 , the stage GC1_STG(n) includes a Q transistor Tgc1_q and a Qb transistor Tgc1_qb, and a control circuit GC1_CC for controlling switching operations of the Q transistor Tgc1_q and the Qb transistor Tgc1_qb. may include.

The Q transistor Tgc1_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc1_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc1_q and the Qb transistor Tgc1_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc1_q and the Qb transistor Tgc1_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC1_CC may be configured to include the Q node Ngc1_q, which is one control node capable of simultaneously controlling the Q transistor Tgc1_q and the Qb transistor Tgc1_qb in common.

In this way, since it is sufficient for the control circuit GC1_CC to include one Q node Ngc1_q, the circuit configuration in the control circuit GC1_CC can be simplified, so that the size of the first gate driving circuit GC1 can be reduced. there will be

The control circuit GC1_CC may include four first to fourth transistors Tgc1_1, Tgc1_2, Tgc1_3, and Tgc1_4 and one capacitor Cgc1_q.

The configuration of the first and second transistors Tgc1_1 and Tgc1_2 and the capacitor Cgc1_q may be the same as the configuration of the first example of FIG. 4 .

The third transistor Tgc1_3, like the first and second transistors Tgc1_1 and Tgc1_2, may be formed of P-type or N-type polysilicon.

The third transistor Tgc1_3 may be connected in parallel with the second transistor Tgc1_2 and may be connected between the first and fourth transistors Tgc1_1 and Tgc1_4. In contrast, the gate of the third transistor Tgc1_3 may be configured to receive the first gate clock GCLKgc1_1. A source of the third transistor Tgc1_3 may be connected to a node between the first and second transistors Tgc1_1 and Tgc1_2 . A drain of the third transistor Tgc1_3 may be connected to a drain of the fourth transistor Tgc1_4.

The fourth transistor Tgc1_4, like the Qb transistor Tgc1_qb, may be formed of an N-type oxide semiconductor.

The fourth transistor Tgc1_4 may be connected in parallel with the Qb transistor Tgc1_qb. In contrast, the gate of the fourth transistor Tgc1_4 may be connected to the Q node Ngc1_q. A drain of the fourth transistor Tgc1_4 may be connected to the third transistor Tgc1_3. The source of the fourth transistor Tgc1_4 may be configured to receive the high voltage VGH (or the gate high voltage).

As described above, the stage GC1_STG(n) of the second structure according to the second example of the present embodiment does not include the Qb node, so that the transistor constituting the Qb node can be removed.

Accordingly, in the first gate driving circuit GC1 having the second structure of the present embodiment, the number of driving elements thereof can be reduced.

6 is a circuit diagram schematically showing a third structure of a first gate driving circuit according to a third example of the first embodiment of the present invention.

The stage GC1_STG(n) of the third structure according to the third example of the present embodiment shown in FIG. 6 is compared to the stage GC1_STG(n) of the first structure according to the first example of the present embodiment in FIG. 4 . , a transistor is added, so that the voltage of the Q node Ngc1_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 6 , the stage GC1_STG(n) includes a Q transistor Tgc1_q and a Qb transistor Tgc1_qb, and a control circuit GC1_CC for controlling switching operations of the Q transistor Tgc1_q and the Qb transistor Tgc1_qb. may include.

The Q transistor Tgc1_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc1_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc1_q and the Qb transistor Tgc1_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc1_q and the Qb transistor Tgc1_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC1_CC may be configured to include the Q node Ngc1_q, which is one control node capable of simultaneously controlling the Q transistor Tgc1_q and the Qb transistor Tgc1_qb in common.

In this way, since it is sufficient for the control circuit GC1_CC to include one Q node Ngc1_q, the circuit configuration in the control circuit GC1_CC can be simplified, so that the size of the first gate driving circuit GC1 can be reduced. there will be

The control circuit GC1_CC may include four first, second, fifth, and sixth transistors Tgc1_1, Tgc1_2, Tgc1_5, and Tgc1_6 and one capacitor Cgc1_q.

The configuration of the first and second transistors Tgc1_1 and Tgc1_2 and the capacitor Cgc1_q may be the same as the configuration of the first example of FIG. 4 .

The fifth transistor Tgc1_5, like the first and second transistors Tgc1_1 and Tgc1_2, may be formed of P-type or N-type polysilicon.

The fifth transistor Tgc1_5 is connected between the Q node Ngc1_q and the gate of the Qb transistor Tgc1_qb to turn on/off the connection therebetween. In contrast, the gate of the fifth transistor Tgc1_5 may be connected to a node between the first and second transistors Tgc1_1 and Tgc1_2. A source of the fifth transistor Tgc1_5 may be connected to the Q node Ngc1_q. A drain of the fifth transistor Tgc1_5 may be connected to a gate of the Qb transistor Tgc1_qb.

The sixth transistor Tgc1_6, like the Qb transistor Tgc1_qb, may be formed of an N-type oxide semiconductor.

The sixth transistor Tgc1_6 is connected in parallel with the fifth transistor Tgc1_5 to be switched in opposite phases. In contrast, the gate of the sixth transistor Tgc1_6 may be connected to a node between the first and second transistors Tgc1_1 and Tgc1_2 . A drain of the sixth transistor Tgc1_6 may be connected to a gate of the Qb transistor Tgc1_qb. The source of the sixth transistor Tgc1_4 may be configured to receive another high voltage VQH having a higher level than the high voltage VGH. Here, for convenience of description, the high voltage VGH input to the Qb transistor Tgc1_qb will be referred to as a first high voltage VGH, and a higher high voltage VQH will be referred to as a second high voltage VGH. can

If the fifth and sixth transistors Tgc1_5 and Tgc1_6 are used as described above, even if the Qb transistor Tgc1_qb is deteriorated and the threshold voltage is shifted and fluctuated, robust reliability can be secured.

In this regard, the Qb transistor Tgc1_qb that outputs the first high voltage VGH, which is the off voltage, is in the on state for a relatively long time, and in particular, the on state is maintained for a long time during low frequency driving, so that the Qb transistor Tgc1_qb is deteriorated The threshold voltage can be varied.

As such, when the threshold voltage of the Qb transistor Tgc1_qb is changed, the Qb transistor Tgc1_qb cannot be turned on normally due to the voltage of the Q node Ngc1_q. The high voltage VGH cannot be normally output. Due to this, the pixel may be driven abnormally.

In contrast, in the third structure according to the third example of this embodiment, the fifth transistor Tgc1_5 is turned off during the period in which the first gate signal Vg1(n) outputs the first high voltage VGH. and the sixth transistor Tgc1_6 may be configured to be in an on state.

In this case, the Qb transistor Tgc1_qb may be electrically disconnected from the Q node Ngc1_q, and may receive the second high voltage VQH through the sixth transistor Tgc1_6.

Here, the second high voltage VQH may be configured to have a sufficiently higher level than the first high voltage VGH by reflecting the threshold voltage variation margin of the Qb transistor Tgc1_qb.

Accordingly, even if the threshold voltage is shifted and fluctuated, the Qb transistor Tgc1_qb may be normally in an on state by the second high voltage VQH. Accordingly, the high voltage VGH of the first gate signal Vg1(n) is normally output, so that the pixel can be normally driven.

As described above, the stage GC1_STG(n) of the third structure according to the third example of this embodiment does not include the Qb node, so that the transistor for configuring it can be removed.

Accordingly, in the first gate driving circuit GC1 having the third structure of the present embodiment, the number of driving elements thereof can be reduced.

7 is a circuit diagram schematically showing a fourth structure of a first gate driving circuit according to a fourth example of the first embodiment of the present invention.

The stage GC1_STG(n) of the fourth structure according to the fourth example of the present embodiment shown in FIG. 7 is compared to the stage GC1_STG(n) of the first structure according to the first example of the present embodiment of FIG. 4 . , a transistor is added, so that the voltage of the Q node Ngc1_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 7 , the stage GC1_STG(n) includes a Q transistor Tgc1_q and a Qb transistor Tgc1_qb, and a control circuit GC1_CC for controlling switching operations of the Q transistor Tgc1_q and the Qb transistor Tgc1_qb. may include.

The Q transistor Tgc1_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc1_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc1_q and the Qb transistor Tgc1_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc1_q and the Qb transistor Tgc1_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC1_CC may be configured to include the Q node Nq, which is one control node capable of simultaneously controlling the Q transistor Tgc1_q and the Qb transistor Tgc1_qb in common.

As such, since it is sufficient for the control circuit GC1_CC to include one Q node Nq, the circuit configuration in the control circuit GC1_CC can be simplified, so that the size of the first gate driving circuit GC1 can be reduced. there will be

The control circuit GC1_CC may include four first, second, seventh, and eighth transistors Tgc1_1, Tgc1_2, Tgc1_7, and Tgc1_8 and one capacitor Cgc1_q.

The configuration of the first and second transistors Tgc1_1 and Tgc1_2 and the capacitor Cgc1_q may be the same as the configuration of the first example of FIG. 4 .

Meanwhile, in the fourth example of this embodiment, since the seventh and eighth transistors Tgc1_7 and Tgc1_8 are provided, similarly to the above-described third example, the Qb transistor Tgc1_qb is deteriorated and the threshold voltage fluctuates. can be obtained.

In this regard, the seventh transistor Tgc1_7 may be formed of an N-type oxide semiconductor in the same manner as the Qb transistor Tgc1_qb.

The seventh transistor Tgc1_7 is connected in parallel with the eighth transistor Tgc1_8 to be switched in opposite phases. In contrast, the gate of the seventh transistor Tgc1_7 may be connected to a node between the first and eighth transistors Tgc1_1 and Tgc1_8 . A drain of the seventh transistor Tgc1_7 may be connected to a source of the second transistor Tgc1_2 . The source of the seventh transistor Tgc1_7 may be configured to receive the second high voltage VQH having a higher level than the first high voltage VGH.

The eighth transistor Tgc1_8, like the first and second transistors Tgc1_1 and Tgc1_2, may be formed of P-type or N-type polysilicon.

The eighth transistor Tgc1_8 is configured to be connected between the first transistor Tgc1_1 and the second transistor Tgc1_2 together with the seventh transistor Tgc1_7 to be switched in opposite phases. In contrast, the gate and the source of the eighth transistor Tgc1_8 may be directly connected to each other, and the drain of the first transistor Tgc1_1 and the gate of the seventh transistor Tgc1_7 may be connected to each other. A drain of the eighth transistor Tgc1_8 may be connected to a drain of the seventh transistor Tgc1_7.

When the seventh and eighth transistors Tgc1_7 and Tgc1_8 are used as described above, even if the Qb transistor Tgc1_qb is deteriorated and the threshold voltage is shifted and fluctuated, robust reliability can be secured.

In this regard, in the fourth structure according to the fourth example of this embodiment, the eighth transistor Tgc1_8 is turned off during the period in which the first gate signal Vg1(n) outputs the first high voltage VGH. and the seventh transistor Tgc1_7 may be configured to be in an on state.

In this case, the second high voltage VQH may be applied to the Q node Ngc1_q and the second high voltage VQH may be applied to the Qb transistor Tgc1_qb.

Accordingly, even if the threshold voltage is shifted and fluctuated, the Qb transistor Tgc1_qb may be normally in an on state by the second high voltage VQH. Accordingly, the high voltage VGH of the first gate signal Vg1(n) is normally output, so that the pixel can be normally driven.

As described above, the stage GC1_STG(n) of the fourth structure according to the fourth example of this embodiment does not include the Qb node, so that the transistor constituting the Qb node can be removed.

Accordingly, in the first gate driving circuit GC1 having the fourth structure of the present embodiment, the number of driving elements thereof can be reduced.

8 is a waveform diagram showing a simulation result for the gate signal output of the first gate driving circuit configured with the structures of the first and second examples described above, and FIG. 9 is a waveform diagram with the structures of the third and fourth examples described above. It is a waveform diagram showing the simulation result for the gate signal output of the first gate driving circuit.

In Fig. 8, the signal waveforms shown in the upper part are the output waveforms of the comparative example where both the Q transistor and the Qb transistor are made of P-type or N-type polysilicon, and the signal waveforms shown in the lower part are those of the first and second examples of this embodiment. It is the output waveform in the structure.

Referring to FIG. 8 , it can be seen that the first gate driving circuit configured with the structures of the first and second examples proposed in this embodiment can secure a normal gate signal output characteristic, as in the comparative example.

And, referring to FIG. 9 , it can be confirmed that the first gate driving circuit configured with the structures of the third and fourth examples proposed in this embodiment can also secure normal gate signal output characteristics.

As described above, in the first embodiment of the present invention, with respect to the first gate driving circuit, the Q transistor and Qb transistor of the P-type or N-type polysilicon and N-type oxide as a heterogeneous semiconductor material of opposite types to each other It may be constructed using a semiconductor.

Accordingly, since the Q transistor and the Qb transistor can be driven by sharing the Q node, a driving element for implementing the Qb node can be eliminated.

Accordingly, it is possible to reduce the number of driving elements constituting the first gate driving circuit, thereby reducing the size of the GIP type scan driving unit and reducing the width of the bezel of the display device.

<Second embodiment>

The electroluminescent display device according to the second embodiment of the present invention may be configured similarly to the electroluminescent display device according to the first embodiment described above, and a detailed description of the same and similar configuration may be omitted.

In the electroluminescent display device (10 in FIG. 1) according to the second embodiment of the present invention, the driving element of the second gate driving circuit (GC2 in FIG. 3) included in the GIP-type scan driver (300 in FIG. 3) is used. number can be reduced. Accordingly, the size of the scan driver can be reduced and the width of the bezel of the display device can be reduced.

The second gate driving circuit according to the second embodiment will be described in more detail below.

The second gate driving circuit of this embodiment may have circuit structures similar to those of the first gate driving circuit (GC1 in FIG. 3 ) proposed in the first embodiment.

In this regard, a driving circuit having four structures is proposed as the second gate driving circuit, and each of the four structures will be described with reference to FIGS. 10 to 13 .

10 is a circuit diagram schematically showing a first structure of a second gate driving circuit according to a first example of a second embodiment of the present invention.

Referring to FIG. 10 , the stage GC2_STG(n) of the second gate driving circuit (GC2 in FIG. 3 ) includes a Q transistor Tgc2_q and a Qb transistor Tgc2_qb, a Q transistor Tgc2_q and a Qb transistor Tgc2_qb ) may include a control circuit GC2_CC for controlling the switching operation.

Furthermore, the stage GC2_STG(n) includes an inverter INV connected between the output node Ngc2_o between the Q transistor Tgc2_q and the Qb transistor Tgc2_qb and the corresponding second gate line GL2(n). can do.

The inverter INV inverts the output signal Vout(n) generated at the output node Ngc2_o between the Q transistor Tgc2_q and the Qb transistor Tgc2_qb. The signal Vg2(n) may be supplied to the corresponding second gate line GL2(n). The output terminal of the inverter INV corresponds to the output terminal of the stage GC2_STG(n).

In this regard, the second gate wiring GL2(n) is connected to the second switching transistor (T3 in FIG. 2 ) composed of an N-type oxide semiconductor in the pixel, and the on voltage of the second gate signal Vg2(n) is and the off voltage is a high voltage and a low voltage, which are opposite in phase to the first gate signal (Vgl(n) in FIG. 3).

As such, compared to the stage of the first gate driving circuit (GC1_STG(n) in FIG. 4 ), an inverter INV may be additionally provided to output the corresponding second gate signal Vg2(n).

The Q transistor Tgc2_q may be configured using P-type or N-type polysilicon, and its source is the first gate clock CGLKgc2_1 among the gate clocks GCLKgc2_1 and GCLKgc2_2 input to the stage GC2_STG(n) ) can be approved.

In addition, the Qb transistor Tgc2_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc2_q and the Qb transistor Tgc2_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc2_q and the Qb transistor Tgc2_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC2_CC may be configured to include the Q node Ngc2_q, which is one control node capable of simultaneously controlling the Q transistor Tgc2_q and the Qb transistor Tgc2_qb in common.

As described above, since it is sufficient for the control circuit GC2_CC to include the Q node Ngc2_q, the circuit configuration in the control circuit GC2_CC can be simplified, so that the size of the second gate driving circuit can be reduced.

Such a control circuit GC2_CC may include two first and second transistors Tgc2_1 and Tgc2_2 and one capacitor Cgc2_q.

Here, the first and second transistors Tgc2_1 and Tgc2_2 may be formed of, for example, P-type or N-type polysilicon.

The first transistor Tgc2_1 may be configured such that its gate receives the second gate clock GCLKgc2_2 from among the gate clocks GCLKgc2_1 and GCLKgc2_2 input to the stage GC2_STG(n). The source of the first transistor Tgc2_1 may be configured to receive the output signal Vout(n-1) of the output node Ngc2_o of the previous stage. A drain of the first transistor Tgc2_1 may be configured to be connected to a source of the second transistor Tgc2_2 .

The second transistor Tgc2_2 may be connected between the first transistor Tgc2_1 and the Q node Ngc2_q, and a gate thereof may be configured to receive the low voltage VGL.

As described above, the stage GC2_STG(n) of the first structure according to the first example of the present embodiment does not include the Qb node, and thus a transistor constituting the Qb node can be removed.

Accordingly, in the second gate driving circuit configured with the first structure of the present embodiment, the number of driving elements thereof can be significantly reduced, and can be substantially minimized.

11 is a circuit diagram schematically showing a second structure of a second gate driving circuit according to a second example of the second embodiment of the present invention.

The stage GC2_STG(n) of the second structure according to the second example of the present embodiment shown in FIG. 11 is compared with the stage GC2_STG(n) of the first structure according to the first example of the present embodiment in FIG. 10 . , a transistor is added, so that the voltage of the Q node Ngc2_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 11 , the stage GC2_STG(n) includes a Q transistor Tgc2_q and a Qb transistor Tgc2_qb, and a control circuit GC2_CC for controlling switching operations of the Q transistor Tgc2_q and the Qb transistor Tgc2_qb. may include.

Furthermore, the stage GC2_STG(n) includes an inverter INV connected between the output node Ngc2_o between the Q transistor Tgc2_q and the Qb transistor Tgc2_qb and the corresponding second gate line GL2(n). can do.

The Q transistor Tgc2_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc2_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc2_q and the Qb transistor Tgc2_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc2_q and the Qb transistor Tgc2_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC2_CC may be configured to include the Q node Ngc2_q, which is one control node capable of simultaneously controlling the Q transistor Tgc2_q and the Qb transistor Tgc2_qb in common.

As such, since it is sufficient for the control circuit GC2_CC to include one control node, the Q node Ngc2_q, the circuit configuration in the control circuit GC2_CC can be simplified, and the size of the second gate driving circuit can be reduced. there will be

The control circuit GC2_CC may include two first to fourth transistors Tgc2_1, Tgc2_2, Tgc2_3, and Tgc2_4 and one capacitor Cgc2_q.

The configuration of the first and second transistors Tgc2_1 and Tgc2_2 and the capacitor Cgc2_q may be the same as the configuration of the first example of FIG. 10 .

The third transistor Tgc2_3, like the first and second transistors Tgc2_1 and Tgc2_2, may be formed of P-type or N-type polysilicon.

The third transistor Tgc2_3 may be connected in parallel with the second transistor Tgc2_2 and may be connected between the first and fourth transistors Tgc2_1 and Tgc2_4. In contrast, the gate of the third transistor Tgc2_3 may be configured to receive the first gate clock GCLKgc2_1. A source of the third transistor Tgc2_3 may be connected to a node between the first and second transistors Tgc2_1 and Tgc2_2 . A drain of the third transistor Tgc2_3 may be connected to a drain of the fourth transistor Tgc2_4 .

The fourth transistor Tgc2_4, like the Qb transistor Tgc2_qb, may be formed of an N-type oxide semiconductor.

The fourth transistor Tgc2_4 may be connected in parallel with the Qb transistor Tgc2_qb. In contrast, the gate of the fourth transistor Tgc2_4 may be connected to the Q node Ngc2_q. A drain of the fourth transistor Tgc2_4 may be connected to the third transistor Tgc2_3 . The source of the fourth transistor Tgc2_4 may be configured to receive the high voltage VGH.

As described above, the stage GC2_STG(n) of the second structure according to the second example of the present embodiment does not include the Qb node, so that the transistor for configuring the stage GC2_STG(n) can be removed.

Accordingly, in the second gate driving circuit configured with the second structure of the present embodiment, the number of driving elements thereof can be reduced.

12 is a circuit diagram schematically showing a third structure of a second gate driving circuit according to a third example of the second embodiment of the present invention.

The stage GC2_STG(n) of the third structure according to the third example of the present embodiment shown in FIG. 12 is compared to the stage GC2_STG(n) of the first structure according to the first example of the present embodiment in FIG. 10 . , a transistor is added, so that the voltage of the Q node Ngc2_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 12 , the stage GC2_STG(n) includes a Q transistor Tgc2_q and a Qb transistor Tgc2_qb, and a control circuit GC2_CC for controlling switching operations of the Q transistor Tgc2_q and the Qb transistor Tgc2_qb. may include.

Furthermore, the stage GC2_STG(n) includes an inverter INV connected between the output node Ngc2_o between the Q transistor Tgc2_q and the Qb transistor Tgc2_qb and the corresponding second gate line GL2(n). can do.

The Q transistor Tgc2_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc2_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc2_q and the Qb transistor Tgc2_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc2_q and the Qb transistor Tgc2_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC2_CC may be configured to include the Q node Ngc2_q, which is one control node capable of simultaneously controlling the Q transistor Tgc2_q and the Qb transistor Tgc2_qb in common.

As such, since it is sufficient for the control circuit GC2_CC to include one control node, the Q node Ngc2_q, the circuit configuration in the control circuit GC2_CC can be simplified, and the size of the second gate driving circuit can be reduced. there will be

The control circuit GC2_CC may include four first, second, fifth, and sixth transistors Tgc2_1, Tgc2_2, Tgc2_5, and Tgc2_6 and one capacitor Cgc2_q.

The configuration of the first and second transistors Tgc2_1 and Tgc2_2 and the capacitor Cgc2_q may be the same as the configuration of the first example of FIG. 10 .

The fifth transistor Tgc2_5, like the first and second transistors Tgc2_1 and Tgc2_2, may be formed of P-type or N-type polysilicon.

The fifth transistor Tgc2_5 is connected between the Q node Ngc2_q and the Qb transistor Tgc2_qb to turn on/off the connection therebetween. In contrast, the gate of the fifth transistor Tgc2_5 may be connected to a node between the first and second transistors Tgc2_1 and Tgc2_2. A source of the fifth transistor Tgc2_5 may be connected to the Q node Ngc2_q. A drain of the fifth transistor Tgc2_5 may be connected to a gate of the Qb transistor Tgc2_qb.

The sixth transistor Tgc2_6, like the Qb transistor Tgc2_qb, may be formed of an N-type oxide semiconductor.

The sixth transistor Tgc2_6 is connected in parallel with the fifth transistor Tgc2_5 to be switched in opposite phases. In contrast, the gate of the sixth transistor Tgc2_6 may be connected to a node between the first and second transistors Tgc2_1 and Tgc2_2. A drain of the sixth transistor Tgc2_6 may be connected to a gate of the Qb transistor Tgc2_qb. The source of the sixth transistor Tgc2_6 may be configured to receive the second high voltage VQH, which is another high voltage VQH having a higher level than the first high voltage VGH, which is the high voltage VGH.

When the fifth and sixth transistors Tgc2_5 and Tgc2_6 are used as described above, even if the threshold voltage is shifted and fluctuated due to deterioration of the Qb transistor Tgc2_qb, robust reliability can be secured.

As described above, the stage GC2_STG(n) of the third structure according to the third example of the present embodiment does not include the Qb node, so that the transistor for configuring the stage GC2_STG(n) can be removed.

Accordingly, in the second gate driving circuit configured with the third structure of the present embodiment, the number of driving elements thereof can be reduced.

13 is a circuit diagram schematically showing a fourth structure of a second gate driving circuit according to a fourth example of the first embodiment of the present invention.

The stage GC2_STG(n) of the fourth structure according to the fourth example of the present embodiment shown in FIG. 13 is compared to the stage GC2_STG(n) of the first structure according to the first example of the present embodiment in FIG. 10 . , a transistor is added, so that the voltage of the Q node Ngc2_q may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 13 , the stage GC2_STG(n) includes a Q transistor Tgc2_q and a Qb transistor Tgc2_qb, and a control circuit GC2_CC for controlling switching operations of the Q transistor Tgc2_q and the Qb transistor Tgc2_qb. may include.

Furthermore, the stage GC2_STG(n) includes an inverter INV connected between the output node Ngc2_o between the Q transistor Tgc2_q and the Qb transistor Tgc2_qb and the corresponding second gate line GL2(n). can do.

The Q transistor Tgc2_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tgc2_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tgc2_q and the Qb transistor Tgc2_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tgc2_q and the Qb transistor Tgc2_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit GC2_CC may be configured to include the Q node Ngc2_q, which is one control node capable of simultaneously controlling the Q transistor Tgc2_q and the Qb transistor Tgc2_qb in common.

As such, since it is sufficient for the control circuit GC2_CC to include one control node, the Q node Ngc2_q, the circuit configuration in the control circuit GC2_CC can be simplified, and the size of the second gate driving circuit can be reduced. there will be

The control circuit GC2_CC may include four first, second, seventh, and eighth transistors Tgc2_1, Tgc2_2, Tgc2_7, and Tgc2_8 and one capacitor Cgc2_q.

The configuration of the first and second transistors Tgc2_1 and Tgc2_2 and the capacitor Cgc2_q may be the same as the configuration of the first example of FIG. 10 .

Meanwhile, in the fourth example of this embodiment, since the seventh and eighth transistors Tgc2_7 and Tgc2_8 are provided, similarly to the above-described third example, the Qb transistor Tgc2_qb is deteriorated and the threshold voltage fluctuates. can be obtained.

In this regard, the seventh transistor Tgc2_7 may be formed of an N-type oxide semiconductor in the same manner as the Qb transistor Tgc2_qb.

The seventh transistor Tgc2_7 is connected in parallel with the eighth transistor Tgc2_8 to be switched in opposite phases. In contrast, the gate of the seventh transistor Tgc2_7 may be connected to a node between the first and eighth transistors Tgc2_1 and Tgc2_8 . A drain of the seventh transistor Tgc2_7 may be connected to a source of the second transistor Tgc2_2 . The source of the seventh transistor Tgc2_7 may be configured to receive the second high voltage VQH having a higher level than the first high voltage VGH.

The eighth transistor Tgc2_8, like the first and second transistors Tgc2_1 and Tgc2_2, may be formed of P-type or N-type polysilicon.

The eighth transistor Tgc2_8 is configured to be connected between the first transistor Tgc2_1 and the second transistor Tgc2_2 together with the seventh transistor Tgc2_7 to be switched in opposite phases. In contrast, the gate and the source of the eighth transistor Tgc2_8 may be directly connected to each other, and may also be connected to the drain of the first transistor Tgc2_1 and the gate of the seventh transistor Tgc2_7 . A drain of the eighth transistor Tgc2_8 may be connected to a drain of the seventh transistor Tgc2_7.

As described above, the stage GC2_STG(n) of the fourth structure according to the fourth example of the present embodiment does not include the Qb node, so that a transistor for configuring the stage GC2_STG(n) can be removed.

Accordingly, in the second gate driving circuit configured with the fourth structure of the present embodiment, the number of driving elements thereof can be reduced.

As described above, in the second embodiment of the present invention, with respect to the second gate driving circuit, the Q transistor and Qb transistor of the P-type or N-type polysilicon and N-type oxide are different types of semiconductor materials opposite to each other. It may be constructed using a semiconductor.

Accordingly, since the Q transistor and the Qb transistor can be driven by sharing the Q node, a driving element for implementing the Qb node can be eliminated.

Accordingly, it is possible to reduce the number of driving elements constituting the second gate driving circuit, thereby reducing the size of the GIP type scan driving unit and reducing the width of the bezel of the display device.

Meanwhile, the electroluminescent display device of the present embodiment may be configured to include the structure of the first gate driving circuit of the first embodiment. In this case, the size of the GIP type scan driver can be further reduced and the width of the bezel of the display device can be further reduced.

<Third embodiment>

The electroluminescent display device according to the third embodiment of the present invention may be configured similarly to the electroluminescent display device according to the first embodiment described above, and a detailed description of the same and similar configuration may be omitted.

In the electroluminescent display device according to the third embodiment of the present invention, the number of driving elements of the light emitting driving circuit (EC of FIG. 3 ) included in the GIP type scan driving unit (300 of FIG. 3 ) can be reduced. Accordingly, the size of the scan driver can be reduced and the width of the bezel of the display device can be reduced.

The light emission driving circuit of the third embodiment will be described in more detail below.

In this embodiment, a driving circuit having three structures is proposed as a light emission driving circuit, and each of the three structures will be described with reference to FIGS. 14 to 16 .

14 is a circuit diagram schematically showing a first structure of a light emitting driving circuit according to a first example of a third embodiment of the present invention.

Referring to FIG. 14 , the stage EC_STG(n) of the light emission driving circuit (EC in FIG. 3 ) includes Q transistors Tec_q and Qb transistors Tec_qb, and Q transistors Tec_q and Qb transistors Tec_qb. A control circuit EC_CC for controlling the switching operation may be included.

The Q transistor Tec_q may operate to output the light emission signal Vem(n) of the low voltage VLG as an on voltage to the corresponding light emitting line EL(n).

The Q transistor Tec_q may be configured using P-type or N-type polysilicon.

The source of the Q transistor Tec_q may be configured to receive the low voltage VGL. The drain of the Q transistor Tec_q may be connected to the output node Nec_o of the stage EC_STG(n), that is, it may be connected to the output node Nec_o between the Q transistor Tec_q and the Qb transistor Tec_qb.

The Qb transistor Tec_qb connected in series with the Q transistor Tec_q is operated to output the light emitting signal Vem(n) of the high voltage VGH as an off voltage to the corresponding light emitting line EL(n). can

Such a Qb transistor Tec_qb may be configured using an N-type oxide semiconductor.

A drain of the Qb transistor Tec_qb may be connected to the output node Nec_o of the stage EC_STG(n). The source of the Qb transistor Tec_qb may be configured to receive the high voltage VGH.

As described above, since the Q transistor Tec_q and the Qb transistor Tec_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tec_q and the Qb transistor Tec_qb are opposite to each other through the same control signal. phase can be switched.

Accordingly, the control circuit EC_CC may be configured to include the Q node Nec_q, which is one control node capable of simultaneously controlling the Q transistor Tec_q and the Qb transistor Tec_qb in common.

As such, since it is sufficient for the control circuit EC_CC to include one control node, the Q node Nec_q, the circuit configuration in the control circuit EC_CC can be simplified, and the size of the light emission driving circuit can be reduced. .

Such a control circuit EC_CC may include one first transistor Tec_1 and one capacitor Cec_q.

Here, the first transistor Tec_1 may be made of, for example, P-type or N-type polysilicon.

The first transistor Tec_1 may be configured such that its gate receives the emission clock ECLK input corresponding to the stage EC_STG(n). The source of the first transistor Tec_1 may be configured to receive the light emission signal Vem(n-1) output from the previous stage. The drain of the first transistor Tec_1 may be configured to be connected to the Q node Nec_q.

The capacitor Cec_q may be connected between the Q node Nec_q and the output node Nec_o to store the voltage of the Q node Nec_q.

As described above, the control circuit EC_CC of the light emitting driving circuit having the first structure is a driving device for driving the Q node Nec_q, and may include one first transistor Tec_1 and one capacitor Cec_q.

As such, it is possible to configure the control circuit CC using a very small number of driving elements, so that the size of the light emission driving circuit can be significantly reduced.

That is, in the light emission driving circuit configured with the first structure of the present embodiment, the number of driving elements thereof can be significantly reduced and can be substantially minimized.

15 is a circuit diagram schematically showing a second structure of a light emission driving circuit according to a second example of the third embodiment of the present invention.

The stage EC_STG(n) of the second structure according to the second example of the present embodiment shown in FIG. 15 is compared with the stage EC_STG(n) of the first structure according to the first example of the present embodiment in FIG. 14 . , a transistor is added, so that the voltage of the Q node (Nec_q) may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 15 , the stage EC_STG(n) includes a Q transistor Tec_q and a Qb transistor Tec_qb, and a control circuit EC_CC for controlling switching operations of the Q transistor Tec_q and the Qb transistor Tec_qb. may include.

The Q transistor Tec_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tec_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tec_q and the Qb transistor Tec_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tec_q and the Qb transistor Tec_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit EC_CC may be configured to include the Q node Nec_q, which is one control node capable of simultaneously controlling the Q transistor Tec_q and the Qb transistor Tec_qb in common.

As such, since it is sufficient for the control circuit EC_CC to include one control node, the Q node Nec_q, the circuit configuration in the control circuit EC_CC can be simplified, and the size of the light emission driving circuit can be reduced. .

The control circuit EC_CC may include two first and second transistors Tec_1 and Tec_2 and one capacitor Cec_q.

The configuration of the first transistor Tec_1 and the capacitor Cec_q may be the same as the configuration in the first example of FIG. 14 .

Like the first transistor Tec_1 , the second transistor Tec_2 may be formed of P-type or N-type polysilicon.

The second transistor Tec_2 may be connected in parallel with the first transistor Tec_1 and connected to the Q node Nec_q. In contrast, the gate and the source of the second transistor Tec_2 may be directly connected to each other and also connected to the Q node Nec_q. The source of the first transistor Tec_1 may be configured to receive the low voltage VGL.

As described above, the stage EC_STG(n) of the second structure according to the second example of the present embodiment does not include the Qb node, so that the transistor constituting it can be removed.

Accordingly, the light emission driving circuit configured with the second structure of the present embodiment can reduce the number of driving elements thereof.

16 is a circuit diagram schematically showing a third structure of a light emission driving circuit according to a third example of the third embodiment of the present invention.

The stage EC_STG(n) of the third structure according to the third example of the present embodiment shown in FIG. 16 is compared to the stage EC_STG(n) of the first structure according to the first example of the present embodiment in FIG. 14 . , a transistor is added, so that the voltage of the Q node (Nec_q) may be further stabilized.

For convenience of description, a detailed description of the same and similar configuration as the first structure of the above-described first example may be omitted.

Referring to FIG. 16 , the stage EC_STG(n) includes a Q transistor Tec_q and a Qb transistor Tec_qb, and a control circuit EC_CC for controlling switching operations of the Q transistor Tec_q and the Qb transistor Tec_qb. may include.

The Q transistor Tec_q may be configured using P-type or N-type polysilicon. In addition, the Qb transistor Tec_qb may be configured using an N-type oxide semiconductor.

As described above, since the Q transistor Tec_q and the Qb transistor Tec_qb may be configured using heterogeneous transistors of opposite types, the Q transistor Tec_q and the Qb transistor Tec_qb are out of phase with each other through the same control signal. can be switched to

Accordingly, the control circuit EC_CC may be configured to include the Q node Nec_q, which is one control node capable of simultaneously controlling the Q transistor Tec_q and the Qb transistor Tec_qb in common.

As such, since it is sufficient for the control circuit EC_CC to include one control node, the Q node Nec_q, the circuit configuration in the control circuit EC_CC can be simplified, and the size of the light emission driving circuit can be reduced. .

The control circuit EC_CC may include two first and third transistors Tec_1 and Tec_3 and one capacitor Cec_q.

The configuration of the first transistor Tec_1 and the capacitor Cec_q may be the same as the configuration in the first example of FIG. 14 .

The third transistor Tec_3, like the first transistor Tec_1, may be formed of P-type or N-type polysilicon.

The third transistor Tec_3 is a bridge voltage transistor and is connected between the first transistor Tec_1 and the Q node Nec_q, and a gate thereof may be configured to receive a low voltage VGL.

As described above, the stage EC_STG(n) of the third structure according to the third example of the present embodiment does not include the Qb node, so that the transistor constituting it can be removed.

Accordingly, the light emission driving circuit configured with the third structure of the present embodiment can reduce the number of its driving elements.

FIG. 17 is a waveform diagram illustrating simulation results for outputting a light emission signal of the light emission driving circuit having the structures of the first to third examples described above.

In Fig. 17, the signal waveform shown in the upper part is the output waveform of the comparative example in which both the Q transistor and the Qb transistor are made of P-type or N-type polysilicon, and the signal waveform shown in the lower part is the output in the structure proposed in this embodiment is a waveform.

Referring to FIG. 17 , it can be confirmed that the light emission driving circuit configured with the structure proposed in this embodiment can secure normal light emission signal output characteristics.

As described above, in the third embodiment of the present invention, for the light emitting driving circuit, the Q transistor and the Qb transistor of the P-type or N-type polysilicon and N-type oxide semiconductor are used as heterogeneous semiconductor materials of opposite types. It can be configured using

Accordingly, since the Q transistor and the Qb transistor can be driven by sharing the Q node, a driving element for implementing the Qb node can be eliminated.

Accordingly, it is possible to reduce the number of driving elements constituting the light emitting driving circuit, thereby reducing the size of the GIP type scan driving unit and reducing the width of the bezel of the display device.

Meanwhile, the electroluminescent display device of this embodiment may be configured to include the first gate driving circuit structure of the first embodiment and/or the second gate driving circuit structure of the second embodiment. In this case, the size of the GIP type scan driver can be further reduced and the width of the bezel of the display device can be further reduced.

As described above, according to an embodiment of the present invention, in the GIP type scan driver, for at least one of the driving circuits outputting a gate signal, a light emitting signal, etc. as the corresponding scan signals, a corresponding Q transistor and The Qb transistor may be formed using a P-type or N-type polysilicon and an N-type oxide semiconductor as heterogeneous semiconductor materials of opposite types.

Accordingly, since the Q transistor and the Qb transistor can be driven by sharing the Q node, the transistor and the capacitor, which are driving elements for realizing the Qb node, can be eliminated.

Accordingly, it is possible to reduce the number of driving elements constituting the corresponding driving circuit, thereby reducing the size of the GIP-type scan driving unit and reducing the width of the bezel of the display device.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

10: electroluminescent display device 100: display panel
200: data driving unit 300: scan driving unit
400: timing control unit
P: pixel
T1: first switching transistor
T2: drive transistor
T3: 2nd switching transistor
T4: first emission control transistor
T5: second light emission control transistor
T6: first initialization transistor
T7: second initialization transistor
Cst: storage capacitor
OD: light emitting diode
GC1: first gate driving circuit
GC2: second gate driving circuit
EC: light emission driving circuit
VIC: Initialization drive circuit
GC1_STG: stage of the first gate driving circuit
GC1_CC: control circuit of the first gate driving circuit
Tgc1_q: Q transistor of the first gate driving circuit
Tgc1_qb: Qb transistor of the first gate driving circuit
Tgc1_1: the first transistor of the first gate driving circuit
Tgc1_2: the second transistor of the first gate driving circuit
Cgc1_q: capacitor of the first gate driving circuit
Ngc1_q: Q node of the first gate driving circuit
Ngc1_o: output node of the first gate driving circuit

Claims (35)

A pixel comprising: a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, and a light emitting diode;
A scan driver including a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to the first switching transistor
including,
The first gate driving circuit is a control circuit including a Q transistor including P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which gates of the Q transistor and the Qb transistor are connected in common. Containing a stage configured including,
electroluminescent display.
The method of claim 1,
The pixel is
Further comprising a first switching transistor including the P-type or N-type polysilicon on the substrate
electroluminescent display.
The method of claim 1,
The control circuit of the stage includes a first transistor including the P-type or N-type polysilicon and receiving the first gate signal output from the previous stage, and the P-type or N-type polysilicon, and includes the first transistor and a second transistor connected between the Q node and to which a gate is applied with a low voltage,
electroluminescent display.
4. The method of claim 3,
The control circuit of the stage,
a fourth transistor including the N-type oxide semiconductor and having a gate connected to the Q node;
Including the P-type or N-type polysilicon and further comprising a third transistor connected between the fourth transistor and the first transistor
electroluminescent display.
5. The method of claim 4,
The control circuit of the stage,
a fifth transistor including the P-type or N-type polysilicon and connected between the Q node and a gate of the Qb transistor;
A sixth transistor comprising the N-type oxide semiconductor, a source receiving a second high voltage and a drain connected to the gate of the Qb transistor,
The second high voltage is higher than the first high voltage input to the Qb transistor.
electroluminescent display.
6. The method of claim 5,
The control circuit of the stage,
a seventh transistor including the N-type oxide semiconductor, a gate connected to a drain of the first transistor, a source applied with a second high voltage, and a drain connected to a source of the second transistor;
An eighth transistor comprising the P-type or N-type polysilicon, a gate and a source connected to a drain of the first transistor, and a drain connected to a source of the second transistor,
The second high voltage is higher than the first high voltage input to the Qb transistor.
electroluminescent display.
4. The method of claim 3,
The control circuit of the stage,
an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.
electroluminescent display.
The method of claim 1,
The scan driver further includes a second gate driving circuit for outputting a second gate signal to a second gate wiring connected to the second switching transistor,
The second gate driving circuit includes a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. A stage comprising a control circuit and a stage comprising an inverter coupled to an output node between the Q transistor and the Qb transistor.
electroluminescent display.
The method of claim 1,
The pixel further includes a light emitting transistor including the P-type or N-type polysilicon and controlling the emission timing of the light emitting diode,
The scan driving unit further comprises a light emitting driving circuit for outputting a light emitting signal to the light emitting wiring connected to the light emitting transistor,
The light emission driving circuit is a control circuit including a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. comprising a stage composed of
electroluminescent display.
The method of claim 1,
The pixel further includes an initialization transistor comprising the P-type or N-type polysilicon, a gate connected to a first gate wiring connected to a pixel of a previous row line, and an initialization transistor having a drain connected to the second switching transistor,
The scan driving unit further includes an initialization driving circuit configured to output an initialization signal to an initialization line connected to a source of the initialization transistor.
electroluminescent display.
The method of claim 1,
The scan driver is formed on the substrate in a GIP method
electroluminescent display.
The method of claim 1,
The electroluminescent display device is driven by a variable frequency driving method.
electroluminescent display.
a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, and a light emitting diode;
A scan driver including a second gate driving circuit for outputting a second gate signal to a second gate line connected to the second switching transistor
including,
The second gate driving circuit is a control having a Q transistor including a P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. a stage comprising a circuit and an inverter coupled to an output node between the Q transistor and the Qb transistor;
The control circuit of the stage includes a first transistor including the P-type or N-type polysilicon and receiving a signal output from an output node between the Q transistor and the Qb transistor of the previous stage, and the P-type or N-type polysilicon and a second transistor connected between the first transistor and the Q node and to which a gate is applied with a low voltage.
electroluminescent display.
14. The method of claim 13,
Further comprising a first switching transistor including the P-type or N-type polysilicon on the substrate,
electroluminescent display.
14. The method of claim 13,
The control circuit of the stage,
a fourth transistor including the N-type oxide semiconductor and having a gate connected to the Q node;
Including the P-type or N-type polysilicon and further comprising a third transistor connected between the fourth transistor and the first transistor
electroluminescent display.
16. The method of claim 15,
The control circuit of the stage,
a fifth transistor including the P-type or N-type polysilicon and connected between the Q node and a gate of the Qb transistor;
A sixth transistor comprising the N-type oxide semiconductor, a source receiving a second high voltage and a drain connected to the gate of the Qb transistor,
The second high voltage is higher than the first high voltage input to the Qb transistor.
electroluminescent display.
17. The method of claim 16,
The control circuit of the stage,
a seventh transistor including the N-type oxide semiconductor, a gate connected to a drain of the first transistor, a source applied with a second high voltage, and a drain connected to a source of the second transistor;
An eighth transistor comprising the P-type or N-type polysilicon, a gate and a source connected to a drain of the first transistor, and a drain connected to a source of the second transistor,
The second high voltage is higher than the first high voltage input to the Qb transistor.
electroluminescent display.
14. The method of claim 13,
The control circuit of the stage,
an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.
electroluminescent display.
14. The method of claim 13,
The scan driving unit further includes a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to the first switching transistor,
The first gate driving circuit includes a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. comprising a stage configured including a control circuit
electroluminescent display.
14. The method of claim 13,
The pixel further includes a light emitting transistor including the P-type or N-type polysilicon and controlling the emission timing of the light emitting diode,
The scan driving unit further comprises a light emitting driving circuit for outputting a light emitting signal to the light emitting wiring connected to the light emitting transistor,
The light emission driving circuit is a control circuit including a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. comprising a stage composed of
electroluminescent display.
14. The method of claim 13,
The pixel includes the P-type or N-type polysilicon, a gate is connected to a first gate wiring connected to a pixel of a previous row line, a source is connected to an initialization line, and a drain is connected to the second switching transistor. further comprising,
The scan driving unit further includes an initialization driving circuit for outputting an initialization signal to the initialization wiring.
electroluminescent display.
14. The method of claim 13,
The scan driver is formed on the substrate in a GIP method
electroluminescent display.
14. The method of claim 13,
The electroluminescent display device is driven by a variable frequency driving method.
electroluminescent display.
A pixel comprising: a pixel including a second switching transistor including an N-type oxide semiconductor on a substrate, a driving transistor having a gate connected to the second switching transistor, a light emitting diode, and a light emitting transistor controlling emission timing of the light emitting diode;
A scan driver including a light emitting driving circuit for outputting a light emitting signal to a light emitting wiring connected to the light emitting transistor
including,
The light emission driving circuit is a control circuit including a Q transistor including P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which gates of the Q transistor and the Qb transistor are connected in common. Containing a stage configured including,
electroluminescent display.
25. The method of claim 24,
The control circuit of the stage includes a first transistor including the P-type or N-type polysilicon and receiving the light emitting signal output from the previous stage,
electroluminescent display.
26. The method of claim 25,
The control circuit of the stage,
A second transistor comprising the P-type or N-type polysilicon, a gate and a drain connected to the Q node, and a source receiving a low voltage.
electroluminescent display.
27. The method of claim 26,
The control circuit of the stage,
A third transistor comprising the P-type or N-type polysilicon and connected between the first transistor and the Q node and to which a gate is applied with a low voltage.
electroluminescent display.
26. The method of claim 25,
The control circuit of the stage,
an output node between the Q transistor and the Qb transistor, and a capacitor connected between the Q node.
electroluminescent display.
25. The method of claim 24,
The scan driving unit further includes a first gate driving circuit for outputting a first gate signal to a first gate wiring connected to the first switching transistor,
The first gate driving circuit includes a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the Q transistor and the Qb transistor gate are connected in common. comprising a stage comprising a circuit
electroluminescent display.
30. The method of claim 29,
The scan driver further includes a second gate driving circuit for outputting a second gate signal to a second gate wiring connected to the second switching transistor,
The second gate driving circuit includes a Q transistor including the P-type or N-type polysilicon, a Qb transistor including the N-type oxide semiconductor, and a Q node to which the gates of the Q transistor and the Qb transistor are connected in common. A stage comprising a control circuit and a stage comprising an inverter coupled to an output node between the Q transistor and the Qb transistor.
electroluminescent display.
25. The method of claim 24,
The pixel further includes an initialization transistor comprising the P-type or N-type polysilicon, a gate connected to a first gate wiring connected to a pixel of a previous row line, and an initialization transistor having a drain connected to the second switching transistor,
The scan driving unit further includes an initialization driving circuit configured to output an initialization signal to an initialization line connected to a source of the initialization transistor.
electroluminescent display.
25. The method of claim 24,
The scan driver is formed on the substrate in a GIP method
electroluminescent display.
25. The method of claim 24,
The electroluminescent display device is driven by a variable frequency driving method.
electroluminescent display.
25. The method of claim 24,
Further comprising a first switching transistor including a P-type or N-type polysilicon on the substrate,
electroluminescent display.
35. The method of claim 34,
The light emitting transistor comprises the P-type or N-type polysilicon,
electroluminescent display.

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