CN115547930B - Semiconductor integrated circuit and method for manufacturing the same - Google Patents
Semiconductor integrated circuit and method for manufacturing the same Download PDFInfo
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- CN115547930B CN115547930B CN202211502713.9A CN202211502713A CN115547930B CN 115547930 B CN115547930 B CN 115547930B CN 202211502713 A CN202211502713 A CN 202211502713A CN 115547930 B CN115547930 B CN 115547930B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The invention provides a semiconductor integrated circuit and a manufacturing method thereof. According to the preparation method, the first etching process is utilized to completely remove the part of the first grid dielectric layer, which is positioned at the side edge of the first grid conducting layer, and then the oxidation process is utilized to form the oxidation layer with larger thickness on the substrate at the side edge of the first grid conducting layer, so that the thickness difference between the oxidation layer at the side edge of the first grid conducting layer and the second grid dielectric layer at the side edge of the second grid conducting layer is reduced, the oxidation layer and the second grid dielectric layer can be consumed in a balanced manner when the second etching process is executed, the problem that the formed transistor device has larger leakage current due to excessive consumption of the oxidation layer in individual areas is avoided, the hot carrier effect of the device can be effectively relieved, and the performance of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor integrated circuit and a method for manufacturing the same.
Background
In ultra large scale integrated circuits (ULSI), a high voltage device and a low voltage device are generally integrated on the same chip by using a Dual Gate Oxide (DGO) process, and then Gate dielectric layers with different thicknesses are required to be prepared in the high voltage device and the low voltage device, respectively.
For example, referring to fig. 1, a low voltage transistor and a high voltage transistor are formed in a first region 10A and a second region 10B of a substrate 10, respectively, and a thickness of a first gate dielectric layer 21 in the first region 10A is smaller than a thickness of a second gate dielectric layer 22 in the second region 10B. And forming a source drain region in the substrate at the side of the gate conductive layer by using an ion implantation process after forming the first gate conductive layer 31 and the second gate conductive layer 32 in the first region 10A and the second region 10B, respectively. In the second region 10B, since the second gate dielectric layer 22 has a larger thickness and is not beneficial to ion implantation, a back etching process needs to be performed before the ion implantation process is performed to reduce the thickness of the second gate dielectric layer 22. Referring specifically to fig. 2, while etching back the second gate dielectric layer 22, the first gate dielectric layer 21 is also consumed, resulting in an excessively small thickness of the first gate dielectric layer 21, and the first gate dielectric layer 21 is also susceptible to lateral erosion below the end of the first gate conductive layer 31, as shown by the dashed box in fig. 2. At this time, although the ion implantation into the first region 10A and the second region 10B may be simultaneously performed to form the source/drain regions 40, since the thickness of the first gate dielectric layer 21 at the side of the first gate conductive layer is reduced or even completely consumed, a problem of leakage current between the first gate conductive layer 31 and the adjacent source/drain regions 40 is easily caused.
Disclosure of Invention
The invention aims to provide a semiconductor integrated circuit and a preparation method thereof, which aim to solve the problem that the current leakage of a device is easily caused by the thickness difference of a grid dielectric layer between a high-voltage area and a low-voltage area which are difficult to balance in the existing preparation process.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor integrated circuit, including: providing a substrate having a first region and a second region; forming a first grid dielectric layer on a first area of the substrate, and forming a second grid dielectric layer on a second area of the substrate, wherein the thickness of the second grid dielectric layer is greater than that of the first grid dielectric layer; forming a first grid conducting layer and a second grid conducting layer on the first grid dielectric layer and the second grid dielectric layer respectively; executing a first etching process to etch the part of the first grid dielectric layer positioned at the side edge of the first grid conducting layer and the part of the second grid dielectric layer positioned at the side edge of the second grid conducting layer, removing the part of the first grid dielectric layer positioned at the side edge of the first grid conducting layer to expose the surface of the substrate, and reducing the thickness of the second grid dielectric layer at the side edge of the second grid conducting layer to a preset thickness; performing an oxidation process to oxidize at least the substrate exposed in the first region to form an oxide layer; executing a second etching process to simultaneously thin the oxide layer and the part of the second grid dielectric layer, which is positioned at the side edge of the second grid conductive layer; and performing an ion implantation process to form source and drain regions in the substrate at the side of the first gate conductive layer and the substrate at the side of the second gate conductive layer.
Optionally, the difference between the thicknesses of the second gate dielectric layer and the first gate dielectric layer is greater than or equal to 400 angstroms.
Optionally, after the first etching process is performed and before the oxidation process is performed, the thickness of the second gate dielectric layer on the side of the second gate conductive layer is less than or equal to 300 angstroms.
Optionally, when the first etching process is performed, a portion of the first gate dielectric layer located below the sidewall of the first gate conductive layer is also laterally eroded.
Optionally, when the oxidation process is performed, oxygen laterally diffuses to a position below the sidewall of the first gate conductive layer to generate an oxidation reaction, so as to increase the thickness of the oxide layer at the sidewall of the first gate conductive layer.
Optionally, the thickness of the oxide layer is greater than that of the first gate dielectric layer.
Optionally, when the oxidation process is performed, the substrate on the side of the second gate conductive layer is further oxidized, so that the thickness of the second gate dielectric layer at the corresponding position is increased, and the oxidation rate of the substrate on the side of the second gate conductive layer is smaller than that of the substrate on the side of the first gate conductive layer.
Optionally, after the oxidation process is performed, a difference between a thickness of the second gate dielectric layer on the side of the second gate conductive layer and a thickness of the oxide layer is less than or equal to 200 angstroms.
Optionally, after the performing the oxidation process and before the performing the second etching process, the method further includes: and forming a side wall on the side walls of the first grid electrode conducting layer and the second grid electrode conducting layer.
Optionally, a second etching process is performed to thin the oxide layer and the portion of the second gate dielectric layer located at the side of the second gate conductive layer to be less than or equal to 300 angstroms.
The present invention also provides a semiconductor integrated circuit including: a substrate having a first region and a second region; a first grid dielectric layer and a first grid conducting layer which are sequentially formed on the substrate of the first area; the oxide layer is formed on the substrate on the side edge of the first grid conducting layer and is mutually connected with the first grid dielectric layer; and the second grid dielectric layer and the second grid conducting layer are sequentially formed on the substrate of the second area, and the second grid dielectric layer comprises a first part positioned right below the second grid conducting layer and a second part positioned on the side edge of the second grid conducting layer. Wherein the thickness of the first portion is greater than the thickness of the first gate dielectric layer, and the difference in thickness between the first portion and the first gate dielectric layer is greater than the difference in thickness between the second portion and the oxide layer.
Optionally, a difference between the thicknesses of the first portion of the second gate dielectric layer and the first gate dielectric layer is greater than or equal to 400 angstroms.
Optionally, the oxide layer further extends laterally to below the sidewall of the first gate conductive layer to be connected to the first gate dielectric layer, and a portion of the oxide layer located below the sidewall of the first gate conductive layer has a bird's beak structure, and a thickness of the bird's beak structure increases gradually from a center of the first gate conductive layer to a direction of the sidewall.
The invention provides a preparation method of a semiconductor integrated circuit, which directly utilizes a first etching process to completely remove the part of a first grid dielectric layer, which is positioned at the side edge of a first grid conducting layer, simultaneously thins the thickness of a second grid dielectric layer, which is positioned at the side edge of a second grid conducting layer, and then utilizes an oxidation process to form an oxidation layer with larger thickness on a substrate at the side edge of the first grid conducting layer, thereby reducing the thickness difference between the oxidation layer at the side edge of the first grid conducting layer and the second grid dielectric layer at the side edge of the second grid conducting layer. Therefore, even if the thickness of the oxide layer and the exposed second gate dielectric layer needs to be thinned before the subsequent ion implantation process is performed, the oxide layer and the second gate dielectric layer can be consumed in a balanced manner, the problem that the formed transistor device has larger leakage current due to excessive consumption of the oxide layer in a certain region is avoided, the hot carrier effect of the device can be effectively relieved, and the performance of the device is improved.
Drawings
Fig. 1-2 are schematic structural diagrams of a conventional semiconductor integrated circuit during a manufacturing process thereof.
Fig. 3 is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention.
Fig. 4-10 are schematic structural diagrams of a semiconductor integrated circuit in a manufacturing process thereof according to an embodiment of the invention.
Wherein the reference numbers are as follows: 10/100-substrate; 10A/100A-first region; 10B/100B-second region; 110-an isolation structure; 21/210-first gate dielectric layer; 210 a-an oxide layer; 22/220-second gate dielectric layer; 220 a-the oxidized second gate dielectric layer; 31/310-first gate conductive layer; 32/320-second gate conductive layer; 400-source drain region; 500-field oxide layer; 610-side wall.
Detailed Description
As described in the background art, in the conventional semiconductor integrated circuit, because the first gate dielectric layer in the first region and the second gate dielectric layer in the second region have a larger thickness difference, at this time, in order to implement the ion implantation in the second region, the thickness of the first gate dielectric layer in the first region has to be sacrificed, which causes a larger leakage current problem of the transistor device formed in the first region, and easily causes a hot carrier effect of the device, which affects the performance of the device.
Therefore, the invention provides a preparation method of a semiconductor integrated circuit, which can avoid the over-thin thickness of the first grid dielectric layer in the first area under the condition of thinning the thickness of the second grid dielectric layer in the second area, and ensure the performance of a transistor device in the first area. Referring specifically to fig. 3, a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention may include the following steps.
Step S100, a substrate is provided, the substrate having a first region and a second region.
Step S200, forming a first grid dielectric layer on the first area of the substrate, and forming a second grid dielectric layer on the second area of the substrate, wherein the thickness of the second grid dielectric layer is larger than that of the first grid dielectric layer.
Step S400, a first etching process is executed to etch the part of the first grid dielectric layer, which is positioned at the side edge of the first grid conducting layer, and the part of the second grid dielectric layer, which is positioned at the side edge of the second grid conducting layer, so as to remove the part of the first grid dielectric layer, which is positioned at the side edge of the first grid conducting layer, so as to expose the surface of the substrate, and the thickness of the second grid dielectric layer, which is positioned at the side edge of the second grid conducting layer, is reduced to a preset thickness.
Step S500 is performed to perform an oxidation process to oxidize at least the substrate exposed in the first region to form an oxide layer.
Step S600, a second etching process is executed to simultaneously thin the oxide layer and the part of the second grid dielectric layer, which is positioned at the side edge of the second grid conducting layer.
Step S700, an ion implantation process is performed to form source and drain regions in the substrate at the side of the first gate conductive layer and the substrate at the side of the second gate conductive layer.
The semiconductor integrated circuit and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
In step S100, as illustrated with particular reference to fig. 4, a substrate 100 is provided, said substrate 100 having a first region 100A and a second region 100B for forming a first transistor device and a second transistor device, respectively.
The substrate 100 includes, for example, a silicon substrate. And, a first region 100A and a second region 100B may be defined by the isolation structure 110, wherein the first region 100A is, for example, a low voltage region for forming a low voltage transistor; the second region 100B is, for example, a high voltage region for forming a high voltage transistor. In a specific example, the second region 100B may be used to form an LDMOS transistor, a field oxide layer 500 may be further formed on the substrate of the second region 100B, and a subsequently formed second gate conductive layer 320 may further extend to cover the field oxide layer 500, so as to form a field plate structure.
In step S200, with reference to fig. 4, a first gate dielectric layer 210 is formed on the first region 100A of the substrate 100, and a second gate dielectric layer 220 is formed on the second region 100B of the substrate 100, where the thickness of the second gate dielectric layer 210 is greater than the thickness of the first gate dielectric layer 210.
In a specific example, the thickness of the second gate dielectric layer 220 is greater than the thickness of the first gate dielectric layer 210 by 400 angstroms. For example, the thickness of the first gate dielectric layer is 50 angstroms to 200 angstroms, and the thickness of the second gate dielectric layer 220 is 450 angstroms to 600 angstroms.
In step S300, referring to fig. 4 in particular, a first gate conductive layer 310 and a second gate conductive layer 320 are formed on the first gate dielectric layer 210 and the second gate dielectric layer 220, respectively. In this embodiment, the second gate conductive layer 320 further extends to cover the field oxide layer 500, so as to form a field plate structure.
Specifically, the preparation method of the first gate conductive layer 310 and the second gate conductive layer 320 includes, for example: depositing a conductive material layer, and forming a mask layer on the conductive material layer, wherein the mask layer defines a pattern of a first gate conductive layer 310 and a second gate conductive layer 320; next, the conductive material layer is etched using the mask layer as a mask to form a first gate conductive layer 310 in the first region 100A and a second gate conductive layer 320 in the second region 100B.
In step S400, referring to fig. 5 specifically, a first etching process is performed to etch a portion of the first gate dielectric layer 210 located at the side of the first gate conductive layer 310 and a portion of the second gate dielectric layer 220 located at the side of the second gate conductive layer 320, remove the portion of the first gate dielectric layer 210 located at the side of the first gate conductive layer 310 to expose the surface of the substrate, and reduce the thickness of the second gate dielectric layer 220 at the side of the second gate conductive layer 320 to a predetermined thickness.
Specifically, before the first etching process is performed, the thickness of the second gate dielectric layer 220 is greater than the thickness of the first gate dielectric layer 210 (for example, the difference between the thickness of the second gate dielectric layer 220 and the thickness of the first gate dielectric layer is greater than or equal to 400 angstroms), so when the portion of the first gate dielectric layer 210 on the side of the first gate conductive layer 310 is removed, the portion of the second gate dielectric layer 220 on the side of the second gate conductive layer 320 is not completely consumed and still has a partial thickness on the substrate 100, and the exposed second gate dielectric layer 220 may be etched to a predetermined thickness, for example, the thickness of the etched second gate dielectric layer 220 on the side of the second gate conductive layer may not be greater than 300 angstroms.
In this embodiment, when the exposed first gate dielectric layer is etched, the portion of the first gate dielectric layer located below the sidewall of the first gate conductive layer 310 is also laterally eroded, the thickness of the oxide layer in the lateral erosion region may be compensated by an oxidation process in the subsequent step, and the oxidation process is further beneficial to further increase the thickness of the oxide layer in the lateral erosion region, which refers to step S500.
In step S500, referring to fig. 6 in particular, an oxidation process is performed to oxidize at least the substrate exposed in the first region 100A to form an oxide layer 210A.
In a specific example, a furnace oxidation process may be employed to oxidize the substrate in the first region 100A and simultaneously oxidize the substrate in the second region 100B, so as to increase the thickness of the second gate dielectric layer (as indicated in fig. 6, the thickness of the oxidized second gate dielectric layer 220A on the side of the second gate conductive layer 320 is increased).
It should be noted that, since the second gate dielectric layer is still covered in the second region 100B with a certain thickness, the oxidation rate of the substrate in the second region 100B is relatively low during the oxidation process, and the substrate is not oxidized any more even after being oxidized to a certain thickness. In the first region 100A, the exposed substrate has a higher oxidation rate, so that the oxide layer 210A with a larger thickness can be quickly formed, the thickness of the formed oxide layer 210A is closer to that of the oxidized second gate dielectric layer 220A, and the thickness difference between the oxide layer 210A and the oxidized second gate dielectric layer 220A is reduced.
Specifically, the difference between the thicknesses of the oxide layer 210a and the oxidized second gate dielectric layer 220a can be controlled within 200 angstroms. For example, the thickness of the oxide layer 210a can reach 500 a-700 a, and the thickness of the oxidized second gate dielectric layer 220a can be controlled within 800 a. In a specific example, the thickness of the oxide layer 210A is 600A, and the thickness of the oxidized second gate dielectric layer 220A can be controlled within 700A, so that the difference between the thicknesses of the oxide layer 210A and the oxidized second gate dielectric layer 220A can be controlled within 100A.
It should be noted that, through the oxidation process, the thickness of the oxide layer 210a on the side of the first gate conductive layer 310 may be increased, and the oxide layer may be laterally diffused during the oxidation process, which is also beneficial to increase the thickness of the oxide layer on the sidewall of the first gate conductive layer 310, so as to reduce the leakage current of the device and improve the hot carrier effect of the device. In particular, in the present embodiment, the sidewall of the first gate conductive layer 310 has a void generated by lateral erosion, so that in the oxidation process, oxygen laterally diffuses to the lower portion of the sidewall of the gate conductive layer 310 to generate an oxidation reaction, and has a faster oxidation rate, so as to compensate the void generated by the lateral erosion at the sidewall of the gate conductive layer 310, and further increase the thickness of the oxide layer in the lateral erosion area, so that the thickness of the oxide layer in the lateral erosion area is greater than the thickness of the first gate dielectric layer 210 directly below the first gate conductive layer 310.
That is, the oxide layer 210a formed in this embodiment is located at the side of the first gate conductive layer 310 and laterally extends to the lower portion of the sidewall of the first gate conductive layer 310, and is connected to the first gate dielectric layer 210. The portion of the oxide layer 210a located on the sidewall of the first gate conductive layer 310 may be, for example, a bird's beak structure, and the thickness of the bird's beak structure increases gradually from the middle of the first gate conductive layer 310 to the edge, so as to further improve the problem of the leakage current of the device and effectively alleviate the hot carrier effect of the device.
It should be appreciated that, since the thickness of the oxide layer 210a is close to the thickness of the oxidized second gate dielectric layer 220a, even if the thicknesses of the oxide layer 210a and the oxidized second gate dielectric layer 220a need to be thinned before the ion implantation process is performed subsequently, the oxide layer 210a and the oxidized second gate dielectric layer 220a can be thinned in a balanced manner at this time, so as to avoid the problem that the thickness of the oxide layer in any region is too small, specifically referring to step S600.
In step S600, referring specifically to fig. 9, a second etching process is performed to simultaneously thin the oxide layer 210A in the first region 100A and the oxidized second gate dielectric layer 220A in the second region 100B.
As described above, in the etching step, the oxide layer 210a and the oxidized second gate dielectric layer 220a can be consumed uniformly, so that the oxide layer 210a and the second gate dielectric layer which are remained after the etching have a smaller thickness difference. The thickness of the oxide layer 210a and the oxidized second gate dielectric layer 220a is reduced to facilitate the ion implantation process. In a specific example, the thickness of the oxide layer 210a and the oxidized second gate dielectric layer 220a can be reduced to not more than 300 angstroms, for example.
In this embodiment, referring to fig. 7 to 8, before etching the oxide layer 210a and the oxidized second gate dielectric layer 220a, a sidewall 610 is further formed on sidewalls of the first gate conductive layer 310 and the second gate conductive layer 320, so that an etching process can be performed under protection of the sidewall 610, and it is avoided that the oxide layer thickness at the sidewall position is easily reduced due to lateral erosion of the etching process under the sidewalls of the first gate conductive layer 310 and the second gate conductive layer 320.
With continued reference to fig. 7-8, the method for forming the sidewall spacers 610 includes: depositing a side wall material layer 600, wherein the side wall material layer 600 covers the first gate conductive layer 310 and the oxide layer 210A in the first region 100A, the second gate conductive layer 320 and the oxidized second gate dielectric layer 220A in the second region 100B, and the isolation structure 110; then, an etch back process is performed to remove the first gate conductive layer 310, the oxide layer 210a, the second gate conductive layer 320, the oxidized second gate dielectric layer 220a, and the sidewall material on the top surface of the isolation structure 110, and at least the sidewall material on the sidewalls of the first gate conductive layer 310 and the second gate conductive layer 320 is remained to form the sidewall 610.
Then, as shown in fig. 9, an etching process is performed under the protection of the sidewall spacers 610, so that the oxide layer 210a at the sidewall position of the first gate conductive layer 310 and the second gate dielectric layer at the sidewall position of the second gate conductive layer 320 still have a larger thickness.
In step S700, referring specifically to fig. 10, an ion implantation process is performed to form source and drain regions 400 in the substrate at the sides of the first gate conductive layer 310 and the second gate conductive layer 320.
Based on the manufacturing method described above, the structure of the formed semiconductor integrated circuit is explained below with reference to fig. 10. As shown in fig. 10, a semiconductor integrated circuit includes: a substrate 100, the substrate 100 having a first region 100A and a second region 100B; first and second transistor devices formed within the first and second regions 100A and 100B, respectively.
Specifically, a first gate dielectric layer 210 and a first gate conductive layer 310 are sequentially formed on the substrate in the first region 100A, and the first gate dielectric layer 210 is completely located right below the first gate conductive layer 310. And an oxide layer 210A is further formed in the first region 100A, and the oxide layer 210A is formed on the substrate beside the first gate conductive layer 310 and is connected to the first gate dielectric layer 210. The first gate dielectric layer 210 and the oxide layer 210a are made of the same material, for example, both include silicon oxide.
In the second region 100B, a second gate dielectric layer 220 and a second gate conductive layer 320 are sequentially formed on the substrate 100, and the second gate dielectric layer 220 includes a first portion located right below the second gate conductive layer 320 and a second portion located at a side of the second gate conductive layer 320.
The first transistor in the first region 100A may constitute a low voltage transistor, and the second transistor in the second region 100B may constitute a high voltage transistor, so that the thickness of the first portion of the second gate dielectric layer 220 is greater than the thickness of the first gate dielectric layer 210. In addition, in this embodiment, the difference between the thicknesses of the first portion of the second gate dielectric layer 220 and the first gate dielectric layer 210 is greater than the difference between the thicknesses of the second portion of the second gate dielectric layer 220 and the oxide layer 210a. For example, the difference between the thickness of the first portion of the second gate dielectric layer 220 and the thickness of the first gate dielectric layer 210 is greater than or equal to 400 angstroms, and the difference between the thickness of the second portion of the second gate dielectric layer 220 and the thickness of the oxide layer 210a is less than or equal to 200 angstroms.
Further, the oxide layer 210a also extends laterally to below the sidewall of the first gate conductive layer 310 to be connected to the first gate dielectric layer 210. The part of the oxide layer 210a located on the sidewall of the first gate conductive layer 310 may have a bird's beak structure, and the thickness of the bird's beak structure gradually increases from the middle of the first gate conductive layer 310 to the sidewall, which is beneficial to further improving the problem of leakage current of the device and alleviating the hot carrier effect of the device.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Also, while the present invention has been described with reference to the preferred embodiments, the embodiments are not intended to be limiting. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should also be understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and not for describing a sequential or logical relationship between various components, elements, steps, or the like, unless otherwise specified or indicated. It should also be understood that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses.
Claims (13)
1. A method of manufacturing a semiconductor integrated circuit, comprising:
providing a substrate having a first region and a second region;
forming a first grid dielectric layer on a first area of the substrate, and forming a second grid dielectric layer on a second area of the substrate, wherein the thickness of the second grid dielectric layer is greater than that of the first grid dielectric layer;
forming a first grid conducting layer and a second grid conducting layer on the first grid dielectric layer and the second grid dielectric layer respectively;
executing a first etching process to remove the part of the first grid dielectric layer, which is positioned at the side edge of the first grid conducting layer, so as to expose the surface of the substrate, and reducing the thickness of the second grid dielectric layer, which is positioned at the side edge of the second grid conducting layer, to a preset thickness;
performing an oxidation process to oxidize at least the substrate exposed in the first region to form an oxide layer;
executing a second etching process to consume the oxide layer and the part of the second grid dielectric layer, which is positioned at the side edge of the second grid conducting layer, in a balanced manner; and the number of the first and second groups,
and performing an ion implantation process to form source and drain regions in the substrate at the side of the first gate conducting layer and the substrate at the side of the second gate conducting layer.
2. The method of claim 1, wherein a difference in thickness between the second gate dielectric layer and the first gate dielectric layer is greater than or equal to 400 angstroms.
3. The method of claim 1, wherein after the first etching process is performed and before the oxidation process is performed, a thickness of the second gate dielectric layer at a side of the second gate conductive layer is less than or equal to 300 angstroms.
4. The method of claim 1, wherein the first etching process is performed while also laterally eroding a portion of the first gate dielectric layer that is located below the sidewall of the first gate conductive layer.
5. The method for manufacturing a semiconductor integrated circuit according to claim 1 or 4, wherein when the oxidation process is performed, oxygen is laterally diffused to below a sidewall of the first gate conductive layer to cause an oxidation reaction, and a thickness of the oxide layer at a sidewall position of the first gate conductive layer is increased.
6. The method of claim 1, wherein the oxide layer has a thickness greater than a thickness of the first gate dielectric layer.
7. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein in the oxidation process, the substrate on the side of the second gate conductive layer is further oxidized to increase the thickness of the second gate dielectric layer at a corresponding position, and an oxidation rate of the substrate on the side of the second gate conductive layer is smaller than an oxidation rate of the substrate on the side of the first gate conductive layer.
8. The method of manufacturing a semiconductor integrated circuit according to claim 1 or 7, wherein a difference between a thickness of the second gate dielectric layer at a side of the second gate conductive layer and a thickness of the oxide layer after the oxidation process is performed is 200 angstroms or less.
9. The method for manufacturing a semiconductor integrated circuit according to claim 1, further comprising, after the performing of the oxidation process and before the performing of the second etching process: and forming a side wall on the side walls of the first grid conducting layer and the second grid conducting layer.
10. The method of claim 1, wherein a second etching process is performed to thin the oxide layer and a portion of the second gate dielectric layer that is located at a side of the second gate conductive layer to less than or equal to 300 angstroms.
11. A semiconductor integrated circuit formed by the manufacturing method according to any one of claims 1 to 10, comprising:
a substrate having a first region and a second region;
a first grid dielectric layer and a first grid conducting layer which are sequentially formed on the substrate of the first area;
the oxide layer is formed on the substrate on the side edge of the first grid conducting layer and is mutually connected with the first grid dielectric layer;
the second grid dielectric layer and the second grid conducting layer are sequentially formed on the substrate of the second area, and the second grid dielectric layer comprises a first part positioned right below the second grid conducting layer and a second part positioned on the side edge of the second grid conducting layer;
wherein the thickness of the first portion is greater than the thickness of the first gate dielectric layer, and the difference in thickness between the first portion and the first gate dielectric layer is greater than the difference in thickness between the second portion and the oxide layer.
12. The semiconductor integrated circuit of claim 11, wherein a difference in thickness between the first portion of the second gate dielectric layer and the first gate dielectric layer is greater than or equal to 400 angstroms.
13. The semiconductor integrated circuit according to claim 11, wherein the oxide layer further extends laterally below the sidewalls of the first gate conductive layer to meet the first gate dielectric layer, and wherein a portion of the oxide layer below the sidewalls of the first gate conductive layer has a bird's beak structure, a thickness of the bird's beak structure increasing from a center of the first gate conductive layer toward the sidewalls.
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