CN114758954A - Preparation method of trench gate field effect transistor - Google Patents

Preparation method of trench gate field effect transistor Download PDF

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Publication number
CN114758954A
CN114758954A CN202210350829.9A CN202210350829A CN114758954A CN 114758954 A CN114758954 A CN 114758954A CN 202210350829 A CN202210350829 A CN 202210350829A CN 114758954 A CN114758954 A CN 114758954A
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China
Prior art keywords
gate
trench
oxide layer
substrate
field effect
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CN202210350829.9A
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Inventor
袁家贵
何云
肖立
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Priority to CN202210350829.9A priority Critical patent/CN114758954A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a preparation method of a trench gate field effect transistor. The top angle of the grid groove is etched to form a gentle transition section, so that the etching rate of the top angle position of the groove in the etching process is reduced, an oxide layer on the top angle of the groove cannot be consumed quickly and can be reserved, and the problem of ion diffusion between a grid electrode and a well region is effectively solved.

Description

Preparation method of trench gate field effect transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a trench gate field effect transistor.
Background
In a trench gate field effect transistor, a gate structure is disposed in a gate trench of a substrate, and a well region and a source region are formed in the substrate at sides of the gate trench. At present, the preparation method for the trench gate field effect transistor generally comprises the following steps: a gate electrode is first formed in a gate trench of a substrate, and then a well region is formed in the substrate at a side of the gate trench. However, in the trench gate field effect transistor formed according to the current manufacturing process, the problem of mutual diffusion of ions between the gate electrode and the well region is easily caused, so that the electrical performance of the device is shifted.
Disclosure of Invention
The invention aims to provide a preparation method of a trench gate field effect transistor, which aims to solve the problem that ions are easy to diffuse mutually between a gate electrode and a well region in the conventional trench gate field effect transistor.
In order to solve the above technical problem, the present invention provides a method for manufacturing a trench gate field effect transistor, comprising: forming a gate trench in a substrate, and forming a gate oxide layer and a gate electrode, wherein the gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode is filled in the gate trench; etching the gate oxide layer on the top surface of the substrate back until the vertex angle of the gate groove is exposed, and etching the vertex angle of the gate groove to form a transition section; forming an oxide layer at least on the transition section; and performing an ion implantation process to form a well region in the substrate at the side of the gate trench.
Optionally, in the process of etching back the gate oxide layer on the top surface of the substrate, the etching rate at the vertex angle position of the gate trench is higher than the etching rate on the top surface of the substrate, so that when the vertex angle of the gate trench is exposed, a part of the gate oxide layer still remains on the top surface of the substrate.
Optionally, isotropic etching is performed on the top angle of the exposed gate trench to form the transition section.
Optionally, after forming the transition section, the method further includes: and performing a first thermal annealing process, and oxidizing the transition section in the thermal annealing process to form the oxide layer.
Optionally, the first thermal annealing process includes: the thermal annealing treatment is performed in an oxygen atmosphere.
Optionally, in the first thermal annealing process, the top surface of the substrate is also oxidized to form an oxide layer; and, before performing the ion implantation process, further comprising: an etch-back process is performed to reduce the thickness of the oxide layer on the top surface of the substrate.
Optionally, the thickness of the oxide layer on the top surface of the substrate is thinned to less than 300 angstroms.
Optionally, after the ion implantation process is performed, the method further includes: and performing a second thermal annealing process.
Optionally, an inclination angle of a sidewall of the gate trench with respect to a height direction is less than or equal to 5 °
Optionally, the trench gate field effect transistor is a shielded gate field effect transistor. And, before forming the gate electrode, further comprising: and forming a shielding electrode in the gate trench.
In the preparation method of the trench gate field effect transistor provided by the invention, the vertex angle position of the gate trench is changed into a more gentle transition section (for example, an arc-shaped structure) from a convex sharp-angled structure by etching the vertex angle of the gate trench, so that the etching rate at the vertex angle position of the trench in the etching process is reduced, an oxide layer on the vertex angle of the trench can be reserved without being rapidly consumed, and the problem of ion diffusion between a gate electrode and a well region is effectively avoided.
Furthermore, the oxide layer at the vertex angle position of the gate trench (i.e., the oxide layer formed on the transition section) can be formed while performing thermal annealing treatment on the gate electrode, which is beneficial to reducing the preparation steps and simplifying the process.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a trench gate field effect transistor according to an embodiment of the present invention.
Fig. 2-9 are schematic structural diagrams of a trench gate field effect transistor in a manufacturing process of the trench gate field effect transistor according to an embodiment of the invention.
Wherein the reference numbers are as follows:
100-a substrate;
110-a gate trench;
210-an insulating dielectric layer;
220-a gate oxide layer;
310-a shield electrode;
320-a gate electrode;
400-an oxide layer;
500-well region.
Detailed Description
As described in the background, conventional trench gate field effect transistors often suffer from a shift in the electrical performance of the device due to ion diffusion between the gate electrode and the well region. In this regard, the inventors of the present invention found, through research, that one diffusion channel in which ion diffusion occurs between the gate electrode in the gate trench and the well region at the side of the gate trench is mainly the top corner position of the gate trench.
In particular, before performing an ion implantation process to form the well region, it is often necessary to thin a film layer on the top surface of the substrate in order that ions may be implanted into the substrate. However, when an etching process is performed to thin the film layer on the top surface of the substrate, the etching rate for the top corner position of the gate trench is large, so that the film layer at the top corner of the trench is consumed to expose the top corner of the gate trench. As a result, when a high temperature thermal annealing process is performed to activate the doped ions in the well region, the ions in the gate electrode and the ions in the well region are diffused into each other through the top corner of the trench.
In view of the above, the present invention provides a method for manufacturing a trench gate field effect transistor, which can be specifically referred to as fig. 1, and the method includes the following steps.
Step S100, forming a gate trench in a substrate, and forming a gate oxide layer and a gate electrode, wherein the gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode is filled in the gate trench.
And step S200, etching the gate oxide layer on the top surface of the substrate back until the vertex angle of the gate groove is exposed, and etching the vertex angle of the gate groove to form a transition section.
Step S300, forming an oxide layer at least on the transition section.
In step S400, an ion implantation process is performed to form a well region in the substrate beside the gate trench.
In other words, in the preparation method of the trench gate field effect transistor provided by the invention, the vertex angle of the gate trench is changed into the gentle transition section, so that the etching rate at the vertex angle position of the gate trench is reduced, the oxide layer on the vertex angle of the trench can be well reserved, and the problem of ion diffusion between the gate electrode and the well region is avoided. Particularly, the oxide layer at the vertex angle position of the gate trench can be formed while the gate electrode is subjected to thermal annealing treatment, so that the preparation steps can be reduced, and the process can be simplified.
The following describes a method for manufacturing a trench gate field effect transistor according to an embodiment of the present invention in further detail with reference to fig. 2 to 9, where fig. 2 to 9 are schematic structural diagrams of a trench gate field effect transistor in a manufacturing process according to an embodiment of the present invention. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
In step S100, referring to fig. 2-4 in particular, a gate trench 110 is formed in a substrate 100 (e.g., a silicon substrate), and a gate oxide layer 220 and a gate electrode 320 are formed, wherein the gate oxide layer 220 covers an inner wall of the gate trench 110 and a top surface of the substrate 100, and the gate electrode 320 is filled in the gate trench 110.
Specifically, the forming method of the gate trench 110 includes, for example: firstly, forming a mask layer on the top surface of the substrate 100 to define a pattern of the gate trench by using the mask layer; next, the substrate 100 is etched using the mask layer as a mask to form the gate trench 110. In this embodiment, the sidewall of the gate trench 110 may be a vertical sidewall or a sidewall close to the vertical sidewall. That is, the inclination angle of the sidewall of the gate trench 110 with respect to the height direction is small, for example, the inclination angle is 5 ° or less, and even the inclination angle may be further 1 ° or less. Note that the "inclination angle of the sidewall of the gate trench 110 with respect to the height direction" described here is: the angle between the sidewall of the gate trench 110 and the height direction.
After the gate trench 110 is formed, a gate structure may be formed in the gate trench 110. In this embodiment, the Trench Gate field effect transistor is specifically a Shielded Gate field effect transistor (SGT), and based on this, before the Gate electrode 320 is formed, a shielding electrode 310 is further formed in the Gate Trench 110, and the Gate electrode 320 is arranged above the shielding electrode 310 in an isolated manner.
Referring to fig. 3 with emphasis, after forming the gate trench 110 and before forming the shield electrode 310, the method further includes: an insulating medium layer 210 is formed in the gate trench 110, and the insulating medium layer 210 covers the sidewalls and the bottom wall of the gate trench 110. The insulating dielectric layer 210 may be formed by a thermal oxidation process, for example, and the material of the insulating dielectric layer 210 includes silicon oxide (SiO), for example. And after the insulating dielectric layer 210 is formed, i.e., the shielding electrode 310 is filled in the gate trench 110, the shielding electrode 310 is correspondingly formed on the insulating dielectric layer 210. In this embodiment, after the shielding electrode 310 is formed, an isolation layer is further formed on the shielding electrode 310 to isolate the shielding electrode 310 from the subsequently formed gate electrode 320.
Further, a gate oxide layer 220 is formed, the gate oxide layer 220 covering the sidewalls of the gate trench and also covering the top surface of the substrate 100. Wherein the thickness of the gate oxide layer 220 is set to be greater than 500 angstroms, for example, 500 angstroms to 800 angstroms; and, the material of the gate oxide layer 220 includes silicon oxide.
Referring next to fig. 4, a gate electrode 320 is formed. In one example, the method for forming the gate electrode 320 includes, for example: first, an electrode material layer is deposited, the electrode material layer fills the gate trench 110 and covers the top surface of the substrate 100, and the material of the electrode material layer may include polysilicon; next, an etch back process is performed to remove the electrode material on the top surface of the substrate, so that the remaining electrode material remains in the gate trench 110 to form the gate electrode 320. The gate electrode 320 may be specifically an N-doped gate electrode, or a P-doped gate electrode. Alternatively, the doped gate electrode 320 may be formed by in-situ doping; alternatively, an ion implantation process may be performed after the gate electrode is formed to form the doped gate electrode 320.
In step S200, referring to fig. 5-6 in particular, the gate oxide layer 220 on the top surface of the substrate is etched back to expose the top corners of the gate trenches 110, and the top corners of the gate trenches are etched to form transition sections.
Specifically, the top corner of the gate trench 110 has a sharp corner structure, so that during the etching of the gate oxide layer 220 on the top surface of the substrate, the etching rate for the top corner position of the gate trench 110 is higher than the etching rate for the gate oxide layer on the top surface of the substrate, so that when the top corner of the gate trench 110 is exposed, a part of the gate oxide layer 220 still remains on the top surface of the substrate.
With continued reference to fig. 6, the top corners of the exposed gate trenches 110 are etched to form gentle transition sections, thereby alleviating the sharp corner structure at the top corner positions of the gate trenches. In a specific scheme, an isotropic etching process may be performed on the exposed top corner of the gate trench 110 to remove a sharp corner at the top, and further make the top corner of the gate trench 110 have an inward-recessed structure. That is, after the vertex angle of the gate trench 110 is etched, the surface of the vertex angle position after etching is a concave arc surface to form a gentle transition section.
It should be noted that, when the top corner of the gate trench 110 is etched, since the top surface of the substrate is still covered with a portion of the gate oxide layer 220, the top surface of the substrate 100 is not entirely consumed when the top corner of the gate trench 110 is etched, and the protruding sharp corner portion of the trench can be accurately removed.
In step S300, and with particular reference to fig. 7, an oxide layer is formed at least on the transition segment. In this embodiment, the oxide layer 400 may be formed in a first thermal annealing process, which may be used to repair crystal damage in the gate electrode 320 and activate doped ions in the gate electrode 320. That is, in the process of performing the first thermal annealing process, the transition section at the top corner of the gate trench 110 may be simultaneously oxidized to form an oxide layer.
In a specific embodiment, the first thermal annealing process may be performed in an oxygen atmosphere, so that the top corner of the gate trench 110 may be oxidized at the same time, for example, oxygen may be introduced into an annealing furnace to perform a thermal annealing process. Further, the top surface of the substrate is also oxidized to form an oxide layer by the first thermal annealing process, and as shown in fig. 7, an oxide layer 400 may be formed on the top surface of the substrate and the top corner of the trench by the first thermal annealing process.
In this embodiment, the thickness of the oxide layer 400 on the top surface of the substrate is increased to at least 800 angstroms by the first thermal annealing process, for example, the thickness of the oxide layer 400 is 800-1200 angstroms.
It should be noted that in the present embodiment, the oxide layer 400 is formed on both the top surface of the substrate and the top corner of the trench through the first thermal annealing process, so that the thickness of the oxide layer 400 on the top surface of the substrate is larger. For this, before performing the ion implantation process, the method further includes: the thickness of the oxide layer 400 is reduced to facilitate the subsequent ion implantation process. Referring to fig. 8 in detail, in this embodiment, the thickness of the oxide layer 400 may be reduced to less than 400 a through an etch-back process, for example, the thickness of the oxide layer 400 is reduced to 300 a to 200 a.
It should be noted that, in the process of etching the oxide layer 400 to reduce the thickness of the oxide layer 400, since the vertex angle of the gate trench 110 is a gentle transition section and there is no sharp-angled structure, the etching rate at the vertex angle position of the trench can be reduced, so that the oxide layers on the top surface of the substrate and the vertex angle of the trench can be uniformly consumed, and the oxide layer at the vertex angle position of the trench is prevented from being completely removed and exposed.
In step S400, referring specifically to fig. 9, an ion implantation process is performed to form a well region 500 in the substrate beside the gate trench. The ion doping type of the well region 500 is opposite to the ion doping type of the gate electrode 320, for example, if the gate electrode 320 is N-doped, the well region 500 is P-doped.
Furthermore, after the ion implantation process is performed, a second thermal annealing process is also used to repair crystal damage in the ion doped region and activate the doped ions. It should be noted that, in the second thermal annealing process, the gate electrode 320 and the well region 500 have oxide layers isolated from each other, and the vertex angle position of the gate trench 110 is still covered with the oxide layer 400, so that the problem of inter-diffusion of ions between the gate electrode 320 and the well region 500 is effectively avoided in the second thermal annealing process.
In summary, in the method for manufacturing a trench gate field effect transistor provided in this embodiment, the gate oxide layer on the top surface of the substrate is etched to expose the top corner of the gate trench, and the top corner of the gate trench is further etched to form a smooth transition section, for example, the top corner of the gate trench is changed from a convex sharp corner structure to a concave arc structure. And when utilizing first thermal annealing process to carry out crystal restoration and ion activation to the gate electrode, can also form the oxide layer with the apex angle oxidation of grid slot, because the apex angle of grid slot is more slick and sly for the oxide layer of slot apex angle position is difficult by the rapid consumption and can be kept, so, can avoid through the problem that the slot apex angle takes place the ion diffusion between gate electrode and the well region promptly.
Furthermore, in the process of etching the gate oxide layer on the top surface of the substrate to expose the vertex angle of the gate trench, the etching process can be specifically used for the etching rate difference between the top surface of the substrate and the vertex angle position of the trench, so that a part of the gate oxide layer is still remained on the top surface of the substrate under the condition that the vertex angle of the gate trench is exposed, and the vertex angle of the gate trench can be better smoothened under the coverage of the gate oxide layer.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And the word "or" should be understood to have the definition of logical "or" rather than the definition of logical "exclusive or" unless the context clearly dictates otherwise.

Claims (11)

1. A method for manufacturing a trench gate field effect transistor, comprising:
forming a gate trench in a substrate, and forming a gate oxide layer and a gate electrode, wherein the gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode is filled in the gate trench;
etching the gate oxide layer on the top surface of the substrate back until the vertex angle of the gate groove is exposed, and etching the vertex angle of the gate groove to form a transition section;
forming an oxide layer at least on the transition section; and the number of the first and second groups,
and performing an ion implantation process to form a well region in the substrate at the side of the gate trench.
2. The method of claim 1, wherein during the back etching of the gate oxide layer on the top surface of the substrate, the etch rate at the top corner of the gate trench is higher than the etch rate at the top surface of the substrate, such that when the top corner of the gate trench is exposed, a portion of the gate oxide layer remains on the top surface of the substrate.
3. The method of claim 1 wherein the exposed top corners of the gate trenches are isotropically etched to form the transition segments.
4. The method of manufacturing a trench-gate field effect transistor according to claim 1, further comprising, after forming the transition segment: and performing a first thermal annealing process, and oxidizing the transition section in the thermal annealing process to form the oxide layer.
5. The method of manufacturing a trench-gate field effect transistor according to claim 4, wherein the first thermal annealing process comprises: the thermal annealing treatment is performed in an oxygen atmosphere.
6. The method of manufacturing a trench gate field effect transistor according to claim 4, wherein in the first thermal annealing process, a top surface of the substrate is also oxidized to form an oxide layer; and, before performing the ion implantation process, further comprising: an etch-back process is performed to reduce the thickness of the oxide layer on the top surface of the substrate.
7. The method of claim 6 wherein the oxide layer on the top surface of the substrate is thinned to a thickness of less than 300 angstroms.
8. The method of manufacturing a trench gate field effect transistor according to claim 1, further comprising, after performing the ion implantation process: and performing a second thermal annealing process.
9. The method of manufacturing a trench gate field effect transistor according to claim 1, wherein an inclination angle of the sidewall of the gate trench with respect to the height direction is 5 ° or less.
10. The method of manufacturing a trench-gate field effect transistor according to any of claims 1 to 9, wherein the trench-gate field effect transistor is a shielded gate field effect transistor.
11. The method of manufacturing a trench-gate field effect transistor according to claim 10, further comprising, before forming the gate electrode: and forming a shielding electrode in the gate trench.
CN202210350829.9A 2022-04-02 2022-04-02 Preparation method of trench gate field effect transistor Pending CN114758954A (en)

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Application Number Priority Date Filing Date Title
CN202210350829.9A CN114758954A (en) 2022-04-02 2022-04-02 Preparation method of trench gate field effect transistor

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CN114758954A true CN114758954A (en) 2022-07-15

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