CN115514598B - Continuous time linear equalization circuit based on inverter negative capacitance compensation - Google Patents
Continuous time linear equalization circuit based on inverter negative capacitance compensation Download PDFInfo
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Abstract
The application relates to a continuous time linear equalization circuit based on inverter negative capacitance compensation. The device comprises a continuous time linear equalization module and a negative capacitance module, wherein the continuous time linear equalization module is used for performing high-frequency loss compensation on an input differential input signal; the negative capacitance module is formed by cross coupling of a first path and a second path and is respectively connected with the positive output end and the negative output end of the continuous time linear balancing module; the first path and the second path are respectively formed by connecting a transconductance load unit and a coupling capacitor in series; generating a negative capacitor through the transconductance load unit, the coupling capacitor and the cross-coupling structure; the transconductance load unit is composed of an inverter, and transconductance and an equivalent load are provided through the inverter; the size of the negative capacitor is adjusted according to the transconductance and the equivalent load, and the load capacitor in the continuous time linear balancing module is adjusted through the adjusted negative capacitor, so that the compensation effect of channel loss is improved, and wider bandwidth and higher high-frequency gain are realized.
Description
Technical Field
The application relates to the technical field of circuit design, in particular to a continuous time linear equalization circuit based on inverter negative capacitance compensation.
Background
Negative capacitors have found wide application in output drivers, equalizers, and the like, due to the compensating effect on parasitic and load capacitances. The traditional negative capacitance generating circuit is composed of two cross-coupled MOS tubes, a capacitor C and a tail current source, and the equivalent impedance is Z as shown in figure 1 in =-2/g m -1/sC, wherein g m Is transconductance of the MOS tube. The circuit belongs to a current mode structure, is driven by a tail current source, and has high power consumption and large occupied area.
Disclosure of Invention
In view of the foregoing, there is a need to provide a continuous time linear equalizer circuit based on inverter negative capacitance compensation, which can reduce power consumption, reduce occupied area, achieve wider bandwidth and higher high frequency gain, and improve compensation effect of channel loss.
A continuous-time linear equalization circuit based on inverter negative capacitance compensation comprises a continuous-time linear equalization module and a negative capacitance module:
the continuous time linear equalization module is used for carrying out high-frequency loss compensation on the input differential input signal;
the negative capacitance module is formed by cross coupling of a first path and a second path and is respectively connected with the positive output end and the negative output end of the continuous time linear equalization module; the first path and the second path are respectively formed by connecting a transconductance load unit and a coupling capacitor in series; generating a negative capacitor through the transconductance load unit, the coupling capacitor and the cross-coupling structure;
the transconductance load unit is composed of an inverter, and transconductance and an equivalent load are provided through the inverter; and adjusting the size of the negative capacitor according to the transconductance and the equivalent load, and adjusting the load capacitor in the continuous time linear balancing circuit through the adjusted negative capacitor.
In one embodiment, the transconductance load unit is formed by an inverter, and includes:
the transconductance load unit is composed of an inverter and an end-to-end inverter, wherein the inverter provides transconductance, and the end-to-end inverter provides an equivalent load.
In one embodiment, when the number of the transconductance load units is odd, the first path includes odd transconductance load units and first coupling capacitors connected in series; the input end of the first path is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the input end of the second path;
the second path comprises odd transconductance load units and second coupling capacitors which are connected in series; and one end of the second coupling capacitor is cross-coupled to the input end of the first path.
In one embodiment, when the number of the transconductance load units is an odd number, the input impedance of the negative capacitance module is:
when in use
Time, input impedance
Can be equivalent to a negative resistance
And a negative capacitance
By adjusting
And with
Adjusting the size of the negative capacitor according to the ratio of the positive voltage to the negative voltage;
wherein the inverter provides transconductance
The end-to-end phase inverters provide equivalent load
，
Which is indicative of the coupling capacitance, is,
representing the complex impedance of the capacitor.
In one embodiment, when the number of the transconductance load units is even, the first path comprises even transconductance load units and first coupling capacitors which are connected in series; the input end of the first path is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the input end of the second path;
the second path comprises an even number of transconductance load units and second coupling capacitors which are connected in series; and one end of the second coupling capacitor is cross-coupled to the input end of the first path.
In one embodiment, when the number of the transconductance load units is an even number, the input impedance of the negative capacitance module is:
input impedance
Can be equivalent to a negative resistance
And a negative capacitance
By adjusting
And
adjusting the size of the negative capacitor according to the ratio of the positive voltage to the negative voltage;
wherein the inverter provides transconductance
And
the end-to-end phase inverters provide equivalent load
And
，
which is indicative of the coupling capacitance, is,
representing the complex impedance of the capacitor.
In one embodiment, the continuous time linear equalization module comprises a first equalization module and a second equalization module, and is configured to obtain a positive input signal and a negative input signal of the differential input signal, respectively;
the continuous time linear equalization module comprises a first equalization module and a second equalization module, and is used for respectively acquiring a positive differential input signal and a negative differential input signal.
The first equalizing module and the second equalizing module have the same structure and respectively comprise a forward channel and a frequency selection channel, and the forward channel is connected with the frequency selection channel in parallel;
the positive differential input signal is divided into two paths and respectively transmitted to an output end through a forward channel and a frequency selection channel of the first equalization module, and is synthesized at the output end to obtain a compensated positive high-frequency signal;
and the negative differential input signal is divided into two paths and respectively transmitted to the output end through the forward channel and the frequency selection channel of the second equalization module, and is synthesized at the output end to obtain a compensated negative high-frequency signal.
In one embodiment, the forward path is comprised of more than one inverter; the frequency selection channel consists of a phase inverter, a phase inverter connected end to end and a capacitor.
In one embodiment, when the frequency selective channel is a low-pass channel, the method includes:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalization module includes an inverter I c1 The first input signal passes through the inverter I c1 Reaching the output end to obtain a first output signal; the low-pass channel of the first equalizing module comprises inverters I connected in series in sequence c2 Capacitor C c1 Phase inverter I connected end to end c3 And an inverter I c4 (ii) a Second input messageSignal slave inverter I c2 Input, slave inverter I c4 Outputting to obtain a second output signal; and subtracting the first output signal from the second output signal to obtain a compensated positive high-frequency signal.
The negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalization module includes an inverter I c5 The third input signal passes through the inverter I c5 Reaching the output end to obtain a third output signal; the low-pass channel of the second equalizing module comprises inverters I connected in series in sequence c6 Capacitor C c2 An inverter I connected end to end c7 And an inverter I c8 (ii) a Fourth input signal slave inverter I c6 Input, slave inverter I c8 Outputting to obtain a fourth output signal; and subtracting the fourth output signal from the third output signal to obtain a compensated negative high-frequency signal.
In one embodiment, when the frequency selective channel is a high-pass channel, the method includes:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalizing module comprises inverters I connected in series in sequence d1 Phase inverter I connected end to end d2 And an inverter I d3 The first input signal is derived from said inverter I d1 Input, slave inverter I d3 Outputting to obtain a first output signal; the high-pass channel of the first equalizing module comprises inverters I which are sequentially connected in series d4 An inverter I connected end to end d5 Capacitor C d1 Phase inverter I connected end to end d6 And an inverter I d7 (ii) a Second input signal slave inverter I d4 Input, slave inverter I d7 Outputting to obtain a second output signal; adding the second output signal and the first output signal to obtain a compensated positive high-frequency signal;
the negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalizing module comprises inverters I connected in series in sequence d8 An inverter I connected end to end d9 And an inverter I d10 From said inverter I, a third input signal d8 Input, slave inverter I d10 Outputting to obtain a third output signal; the high-pass channel of the second equalizing module comprises inverters I which are connected in series in sequence d11 An inverter I connected end to end d12 Capacitor C d2 Phase inverter I connected end to end d13 And an inverter I d14 (ii) a Second input signal slave inverter I d11 Input, slave inverter I d14 Outputting to obtain a fourth output signal; and adding the third output signal and the fourth output signal to obtain a compensated negative high-frequency signal.
The continuous time linear equalization circuit based on the inverter negative capacitance compensation comprises a continuous time linear equalization module and a negative capacitance module, wherein the continuous time linear equalization module is used for carrying out high-frequency loss compensation on an input differential input signal, and the negative capacitance module is formed by cross coupling of a first path and a second path and is respectively connected with a positive output end and a negative output end of the continuous time linear equalization module; the first path and the second path are respectively formed by connecting a transconductance load unit and a coupling capacitor in series; generating a negative capacitor through the transconductance load unit, the coupling capacitor and the cross-coupling structure; the transconductance load unit is composed of an inverter, transconductance and an equivalent load are provided through the inverter, and the coupling capacitor cuts off direct current extraction from the balancing circuit, so that the negative capacitor module does not need additional devices to form a direct current path under the condition of not influencing the working state of the continuous time linear balancing module, and the occupied area is reduced. Because the negative capacitance module is constructed by the phase inverter, the working speed of the phase inverter is mainly influenced by cut-off frequency, the advantage of high cut-off frequency of the advanced process can be fully utilized, and compared with the traditional structure, the negative capacitance module can obtain high working speed without using large tail current, avoids the dependence on the tail current and reduces the power consumption. Meanwhile, the size of the negative capacitor is adjusted according to the transconductance and the equivalent load, and the load capacitor in the continuous time linear balancing module is adjusted through the adjusted negative capacitor, so that the compensation effect of channel loss is improved, and wider bandwidth and higher high-frequency gain are realized.
Drawings
FIG. 1 is a circuit diagram of a conventional negative capacitance generating circuit;
FIG. 2 is a circuit diagram of a continuous time linear equalization circuit based on inverter negative capacitance compensation;
FIG. 3 is a circuit diagram illustrating an embodiment in which the number of transconductance load cells is odd;
FIG. 4 is a small signal model diagram of the circuit of FIG. 3;
FIG. 5 is a circuit diagram illustrating another embodiment of a transconductance load cell with an even number;
FIG. 6 is a small signal model diagram of the circuit of FIG. 4;
FIG. 7 is a circuit diagram of an inverter-based continuous time linear equalization circuit in one embodiment;
fig. 8 is a diagram of an inverter-based continuous time linear equalization circuit in another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that the descriptions related to "first", "second", etc. in the present invention are only used for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
In one embodiment, as shown in fig. 2, a continuous-time linear equalization circuit based on inverter negative capacitance compensation is provided, comprising a continuous-time linear equalization module and a negative capacitance module.
The continuous time linear equalization module is used for carrying out high-frequency loss compensation on the input differential input signals.
The negative capacitance module is formed by cross coupling of a first path and a second path and is respectively connected with the positive electrode output end and the negative electrode output end of the continuous time linear equalization module; the first path and the second path are respectively formed by connecting a transconductance load unit and a coupling capacitor in series; the negative capacitance is generated by the transconductance load unit, the coupling capacitor and the cross-coupling structure.
The transconductance load unit is composed of an inverter, and transconductance and an equivalent load are provided through the inverter; and adjusting the size of the negative capacitor according to the transconductance and the equivalent load, and adjusting the load capacitor in the continuous time linear balancing circuit through the adjusted negative capacitor.
The invention provides a continuous time linear equalization circuit based on inverter negative capacitance compensation, wherein a negative capacitance module has the following characteristics:
1. the transconductance load units in the structure are all formed by inverters, the common-mode voltage average of the power supply voltage and the input and output is consistent with the continuous time linear balance, and the voltage margin stability is kept.
2. The coupling capacitor cuts off the direct current extraction from the equalizing circuit, so that the negative capacitor module can be directly connected with the equalizing circuit under the condition of not influencing the working state of the equalizing circuit, the current extraction from the equalizing circuit cannot influence the working state of the circuit, and therefore, no additional device is needed to form a direct current path, and the occupied area is reduced.
3. The transconductance load unit in the negative capacitance module is composed of the phase inverter, the working speed of the phase inverter is mainly influenced by cut-off frequency, the advantage of high cut-off frequency of an advanced process can be fully utilized, compared with the traditional structure, the high working speed can be obtained without large current, the dependence on tail current is avoided, and the power consumption is reduced.
4. The size of the negative capacitor is adjusted according to the transconductance and the equivalent load, and the load capacitor in the continuous time linear balancing module is adjusted through the adjusted negative capacitor, so that the compensation effect of channel loss is improved, and wider bandwidth and higher high-frequency gain are realized.
Furthermore, the transconductance load unit is composed of an inverter and an end-to-end inverter, wherein the inverter provides transconductance, and the end-to-end inverter provides an equivalent load.
In one embodiment, when the number of the transconductance load units is odd, the first path includes odd transconductance load units and a first coupling capacitor connected in series; the first path input end is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the second path input end.
The second path comprises odd transconductance load units and second coupling capacitors which are connected in series; and one end of the second coupling capacitor is cross-coupled to the input end of the first path.
Specifically, as shown in fig. 3, the input terminal of the first path and the input terminal of the second path of the negative capacitance module are respectively connected to the positive output terminal and the negative output terminal of the continuous-time linear equalization module.
The first path comprises K transconductance load units I connected in series a1 、I a2 ...I ak And a first coupling capacitor C a1 (ii) a First path input end and transconductance load unit I a1 Connected, a first coupling capacitor C a1 One end is cross-coupled to the second path input. Wherein the transconductance load unit I a1 Comprising an inverter I a11 And an end-to-end phase inverter I a12 Transconductance load cell I a2 Comprising an inverter I a21 And an end-to-end phase inverter I a22 Transconductance load cell I ak Comprising an inverter I ak1 And an end-to-end phase inverter I ak2 . First path input terminal and inverter I a11 Are connected.
The second path comprises K transconductance load units I connected in series a1 、I a2 ...I ak And a second coupling capacitor C a2 (ii) a First path input end and transconductance load unit I a1 Connected to a second coupling capacitor C a2 One end is cross-coupled to the first path input. Wherein the transconductance load unit I a1 Comprising an inverter I a13 And an end-to-end phase inverter I a14 Transconductance load cell I a2 Comprising an inverter I a23 And an end-to-end phase inverter I a24 Transconductance load cell I ak Comprising an inverter I ak3 And an end-to-end phase inverter I ak4 . Second path input terminal and inverter I a13 Are connected.
Wherein K = (1, 2, 3.. K), K being an odd number.
In one embodiment, as shown in fig. 4, which is a small-signal model diagram of fig. 3, the input impedance of the negative capacitance module is:
when in use
Time, input impedance
Can be equivalent to a negative resistance
And a negative capacitance
By adjusting
And
the negative capacitance is adjusted by the ratio of (a) to (b).
Wherein, the inverter I a11 ~I ak1 And an inverter I a13 ~I ak3 Providing transconductance
(ii) a End-to-end phase inverter I a12 ~I ak2 And an end-to-end phase inverter I a14 ~I ak4 Providing equivalent load
，
The coupling capacitance is represented by the capacitance of the coupling,
representing the complex impedance of the capacitor.
In one embodiment, when the number of the transconductance load units is even, the first path comprises even transconductance load units and first coupling capacitors which are connected in series; the input end of the first path is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the input end of the second path.
The second path comprises an even number of transconductance load units and second coupling capacitors which are connected in series; the input end of the second path is connected with the transconductance load unit, and one end of the second coupling capacitor is cross-coupled to the input end of the first path.
Specifically, as shown in fig. 5, the input terminal of the first path and the input terminal of the second path of the negative capacitance module are respectively connected to the positive output terminal and the negative output terminal of the continuous-time linear equalization module.
The first path comprises N transconductance load units I connected in series b1 、I b2 ...I bn And a first coupling capacitor C b1 (ii) a First path input end and transconductance load unit I b1 Connected, a first coupling capacitor C b1 One end is cross-coupled to the second path input. Wherein the transconductance load unit I b1 Comprising an inverter I b11 And an end-to-end phase inverter I b12 Transconductance load cell I b2 Comprising an inverter I b21 And an end-to-end phase inverter I b22 Transconductance load cell I bn Comprising an inverter I bn1 And an end-to-end phase inverter I bn2 . First path input terminal and inverter I b11 Are connected.
The second path comprises N transconductance load units I connected in series b1 、I b2 ...I bn And a second coupling capacitor C b2 (ii) a First path input end and transconductance load unit I b1 Connected to a second coupling capacitor C b2 One end is cross-coupled to the first path input. Wherein the transconductance load unit I b1 Comprising an inverter I b13 And an end-to-end phase inverter I b14 Transconductance load cell I b2 Comprising an inverter I b23 And an end-to-end phase inverter I b24 Transconductance load cell I bn IncludedInverter I bn3 And an end-to-end phase inverter I bn4 . Second path input terminal and inverter I b13 Are connected.
Wherein N = (1, 2, 3.. N), N is an even number.
In one embodiment, as shown in fig. 6, which is a small-signal model diagram of fig. 5, the input impedance of the negative capacitance module is:
input impedance
Can be equivalent to a negative resistance
And a negative capacitance
By adjusting
And
the negative capacitance is adjusted by the ratio of (a) to (b).
Wherein, the inverter I b11 And an inverter I b13 Providing transconductance
An inverter I b21 And an inverter I b23 Providing transconductance
By analogy, inverter I bn1 And an inverter I bn3 Providing transconductance
. End-to-end phase inverter I b12 And an inverter I b14 Providing an equivalent load
An inverter I connected end to end b22 And an inverter I b24 Providing equivalent load
By parity of reasoning, the phase inverter I is connected end to end bn2 And an inverter I bn4 Providing equivalent load
。
The coupling capacitance is represented by the capacitance of the coupling,
representing the complex impedance of the capacitor.
In the formula (I), the compound is shown in the specification,
；
；
；
。
it is worth to be noted that, thanks to the advantages of simple structure, low power consumption, small occupied area and the like, continuous time linear equalization based on the inverter becomes a popular research step by step. With the increase of the transmission rate, the load capacitance becomes an important factor for restricting the equalization effect, and the negative capacitance can offset or reduce the influence of the load capacitance, so that a wider bandwidth and a higher high-frequency gain are realized, and the compensation effect of the channel loss is improved by combining the negative capacitance with the continuous time linear equalization. However, the use of conventional negative-capacitance circuits in combination with inverter-based continuous-time linear equalization circuits has three problems:
1. as the process progresses, the supply voltage gradually decreases, even reaching below 1V. In a continuous time linear equalization circuit based on an inverter, in order to ensure linearity, the input and output common mode voltage of the inverter is generally half of the power supply voltage, and for a traditional negative capacitance circuit, the voltage margin is seriously insufficient, and the design difficulty is increased greatly.
2. The traditional negative capacitor circuit needs additional devices to form a direct current path, cannot be directly connected with a continuous time linear equalization circuit based on an inverter, and otherwise, current is extracted, static working points and working performance are influenced, and therefore area consumption is increased.
3. The traditional structure belongs to a current mode architecture, a tail current source is relied on to provide proper bias and working speed, power consumption is high, and the advantage of reducing power consumption based on continuous time balance of a phase inverter is reduced.
The present invention is directed to an inverter-based negative capacitance module for use in conjunction with an inverter-based continuous-time linear equalizer that solves the above-mentioned problems. When the negative capacitor module with any structure in the graph 3 or the graph 5 is adopted, in order to guarantee the linearity, the V +/V-common mode level of the negative capacitor module is set to be half of the power supply voltage and is balanced and consistent with the continuous time linear equalization module based on the phase inverter, and the problem of insufficient voltage margin in the negative capacitor with the traditional structure is solved. The negative capacitance module based on the inverter can be directly connected with the equalizing circuit, and the working state of the circuit cannot be influenced by current extraction from the equalizing circuit, so that a direct current path is formed without additional devices, and the occupied area is reduced. The circuit can fully utilize the advantage of high cut-off frequency of the advanced process, can obtain high working speed without large current, avoids the dependence on tail current and reduces power consumption.
In one embodiment, the continuous-time linear equalization module comprises a first equalization module and a second equalization module, and is used for respectively acquiring a positive input signal and a negative input signal of the differential input signal; the continuous time linear equalization module comprises a first equalization module and a second equalization module and is used for respectively acquiring a positive differential input signal and a negative differential input signal; the first equalizing module and the second equalizing module have the same structure and respectively comprise a forward channel and a frequency selection channel, and the forward channel is connected with the frequency selection channel in parallel.
The positive differential input signal is divided into two paths and respectively transmitted to the output end through the forward channel and the frequency selection channel of the first equalization module, and is synthesized at the output end to obtain a compensated positive high-frequency signal.
The negative differential input signal is divided into two paths and respectively transmitted to the output end through the forward channel and the frequency selection channel of the second equalization module, and is synthesized at the output end to obtain a compensated negative high-frequency signal.
In one embodiment, the forward path is comprised of more than one inverter; the frequency selection channel consists of an inverter, an end-to-end inverter and a capacitor.
In one embodiment, as shown in fig. 7, there is provided an inverter-based continuous-time linear equalization circuit diagram, when the frequency selection channel is a low-pass channel:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalization module includes an inverter I c1 The first input signal passes through the inverter I c1 Reaching an output end to obtain a first output signal; the low-pass channel of the first equalization module comprises inverters I which are connected in series in sequence c2 Capacitor C c1 Phase inverter I connected end to end c3 And an inverter I c4 (ii) a Second input signal slave inverter I c2 Input, slave inverter I c4 Outputting to obtain a second output signal; and subtracting the first output signal from the second output signal to obtain a compensated positive high-frequency signal.
The negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalization module includes an inverter I c5 The third input signal passes through the inverter I c5 Reaching the output end to obtain a third output signal; the low-pass channel of the second equalization module comprises inverters I which are connected in series in sequence c6 Capacitor C c2 In head-to-tail phase oppositionDevice I c7 And an inverter I c8 (ii) a Fourth input signal slave inverter I c6 Input, slave inverter I c8 Outputting to obtain a fourth output signal; and subtracting the fourth output signal from the third output signal to obtain a compensated negative high-frequency signal.
It is worth to be noted that Vip/Vin is an input differential signal, vop/Von is an output differential signal, and the whole circuit is composed of a continuous-time linear equalization module and a negative capacitance module. The negative capacitance module can adopt any one of the negative capacitance module structures in fig. 3 or fig. 5. The phase inverters in the continuous time linear balancing module provide transconductance, and the phase inverters connected end to end provide equivalent load. Capacitor C L Representing a load capacitor, the phase inverter N5 is equivalent to an active inductive load through a resistor R in an end-to-end connection mode, and the capacitor C c1 And a capacitor C c2 Source and drain connected to provide equivalent capacitance and capacitance value C M From a voltage V ctrl And controlling to change the cut-off frequency of the low-pass path. By adjusting the value of the negative capacitance, the load capacitance C can be reduced or cancelled L Impact, spread bandwidth.
During operation, input signal divide into two the tunnel, and one way is through the preceding output that reaches of passageway, and another way is through low pass channel, and the filtering high frequency component is sent the low frequency component to the output to with the signal subtraction that the preceding passageway sent to, make the low frequency gain compression, thereby promoted the relative gain of high frequency component, realized the purpose of high frequency compensation.
In one embodiment, as shown in fig. 8, another inverter-based continuous-time linear equalization circuit is provided, when the frequency selective channel is a high-pass channel:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalizing module comprises inverters I connected in series in sequence d1 Phase inverter I connected end to end d2 And an inverter I d3 A first input signal from said inverter I d1 Input, slave inverter I d3 Outputting to obtain a first output signal; the high-pass channel of the first equalizing module comprises inverters I which are sequentially connected in series d4 An inverter I connected end to end d5 Capacitor C d1 An inverter I connected end to end d6 And an inverter I d7 (ii) a Second input signal slave inverter I d4 Input, slave inverter I d7 Outputting to obtain a second output signal; and adding the second output signal and the first output signal to obtain a compensated positive high-frequency signal.
The negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalizing module comprises inverters I connected in series in sequence d8 An inverter I connected end to end d9 And an inverter I d10 The third input signal is derived from said inverter I d8 Input, slave inverter I d10 Outputting to obtain a third output signal; the high-pass channel of the second equalizing module comprises inverters I which are connected in series in sequence d11 An inverter I connected end to end d12 Capacitor C d2 An inverter I connected end to end d13 And an inverter I d14 (ii) a Second input signal slave inverter I d11 Input, slave inverter I d14 Outputting to obtain a fourth output signal; and adding the third output signal and the fourth output signal to obtain a compensated negative high-frequency signal.
It is worth to say that, during operation, an input signal is divided into two paths, one path reaches an output end through a forward channel, the other path passes through a high-pass channel, low-frequency components are filtered, high-frequency components are sent to the output end, and the high-frequency components and the signals sent by the forward channel are added. The difference compared to fig. 7 is that the circuit increases the absolute value of the high frequency component, not the relative value. In the circuit, an inverter provides transconductance, an inverter connected end to end provides an equivalent load, and a capacitor C M The capacitance value is defined by a voltage V ctrl And a control for varying the cut-off frequency of the high pass path. When in work, the load capacitance C can be reduced or counteracted by adjusting the capacitance value of the negative capacitance L Impact, spread bandwidth.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (8)
1. A continuous time linear equalization circuit based on inverter negative capacitance compensation comprises a continuous time linear equalization module and a negative capacitance module, and is characterized in that:
the continuous time linear equalization module is used for carrying out high-frequency loss compensation on the input differential input signal;
the negative capacitance module is formed by cross coupling of a first path and a second path and is respectively connected with the positive electrode output end and the negative electrode output end of the continuous time linear equalization module; the first path and the second path are respectively formed by connecting a transconductance load unit and a coupling capacitor in series; generating a negative capacitor through the transconductance load unit, the coupling capacitor and the cross-coupling structure;
the transconductance load unit is composed of an inverter, and transconductance and an equivalent load are provided through the inverter; adjusting the size of a negative capacitor according to the transconductance and the equivalent load, and adjusting a load capacitor in the continuous time linear balancing circuit through the adjusted negative capacitor;
when the number of the transconductance load units is odd, the first path comprises odd transconductance load units and first coupling capacitors which are connected in series; the input end of the first path is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the input end of the second path;
the second path comprises odd transconductance load units and second coupling capacitors which are connected in series; the input end of the second path is connected with the transconductance load unit, and one end of the second coupling capacitor is cross-coupled to the input end of the first path; or
When the number of the transconductance load units is even, the first path comprises even transconductance load units and first coupling capacitors which are connected in series; the input end of the first path is connected with the transconductance load unit, and one end of the first coupling capacitor is cross-coupled to the input end of the second path;
the second path comprises an even number of transconductance load units and second coupling capacitors which are connected in series; and one end of the second coupling capacitor is cross-coupled to the input end of the first path.
2. The circuit of claim 1, wherein the transconductance load cell is formed by an inverter comprising:
the transconductance load unit is composed of an inverter and an end-to-end inverter, wherein the inverter provides transconductance, and the end-to-end inverter provides an equivalent load.
3. The circuit of claim 1, wherein when the number of the transconductance load units is an odd number, the input impedance of the negative capacitance module is:
when in use
Time, input impedance
Can be equivalent to a negative resistance
And a negative capacitance
In the clusterIn combination with, by adjustment of
And
adjusting the negative capacitance value according to the ratio of the positive voltage to the negative voltage;
wherein the inverter provides transconductance
The phase inverters connected end to end provide equivalent load
，
Which is indicative of the coupling capacitance, is,
representing the complex impedance of the capacitor.
4. The circuit of claim 1, wherein when the number of the transconductance load units is an even number, the input impedance of the negative capacitance module is:
input impedance
Can be equivalent to a negative resistance
And a negative capacitance
By adjusting
And with
Adjusting the negative capacitance value according to the ratio of the positive voltage to the negative voltage;
wherein the inverter provides transconductance
And
the end-to-end phase inverters provide equivalent load
And
，
the coupling capacitance is represented by the capacitance of the coupling,
representing the complex impedance of the capacitor.
5. The circuit of any of claims 3 or 4, wherein: the continuous time linear equalization module comprises a first equalization module and a second equalization module, and is used for respectively acquiring a positive input signal and a negative input signal of the differential input signal;
the continuous time linear equalization module comprises a first equalization module and a second equalization module, and is used for respectively acquiring a positive differential input signal and a negative differential input signal;
the first equalizing module and the second equalizing module have the same structure and respectively comprise a forward channel and a frequency selection channel, and the forward channel is connected with the frequency selection channel in parallel;
the positive differential input signal is divided into two paths and respectively transmitted to an output end through a forward channel and a frequency selection channel of the first equalization module, and is synthesized at the output end to obtain a compensated positive high-frequency signal;
and the negative differential input signal is divided into two paths and respectively transmitted to the output end through the forward channel and the frequency selection channel of the second equalization module, and is synthesized at the output end to obtain a compensated negative high-frequency signal.
6. The circuit of claim 5, wherein: the forward channel is comprised of more than one inverter; the frequency selection channel consists of a phase inverter, a phase inverter connected end to end and a capacitor.
7. The circuit of claim 6, wherein when the frequency selective channel is a low pass channel, the circuit comprises:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalization module includes an inverter I c1 The first input signal passes through the inverter I c1 Reaching the output end to obtain a first output signal; the low-pass channel of the first equalizing module comprises inverters I connected in series in sequence c2 Capacitor C c1 Phase inverter I connected end to end c3 And an inverter I c4 (ii) a Second input signal slave inverter I c2 Input, slave inverter I c4 Outputting to obtain a second output signal; subtracting the first output signal from the second output signal to obtain a compensated positive high-frequency signal;
the negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalization module includes an inverter I c5 The third input signal passes through the inverter I c5 Reaching the output end to obtain a third output signal; the low-pass channel of the second equalization module comprises inverters I which are connected in series in sequence c6 Capacitor C c2 Phase inverter I connected end to end c7 And an inverter I c8 (ii) a The fourth input signal is invertedPhoto device I c6 Input, slave inverter I c8 Outputting to obtain a fourth output signal; and subtracting the fourth output signal from the third output signal to obtain a compensated negative high-frequency signal.
8. The circuit of claim 6, wherein when the frequency selective channel is a high pass channel, the circuit comprises:
the positive differential input signal comprises a first input signal and a second input signal; the forward path of the first equalizing module comprises inverters I connected in series in sequence d1 An inverter I connected end to end d2 And an inverter I d3 A first input signal from said inverter I d1 Input, slave inverter I d3 Outputting to obtain a first output signal; the high-pass channel of the first equalizing module comprises inverters I which are sequentially connected in series d4 Phase inverter I connected end to end d5 Capacitor C d1 Phase inverter I connected end to end d6 And an inverter I d7 (ii) a Second input signal slave inverter I d4 Input, slave inverter I d7 Outputting to obtain a second output signal; adding the second output signal and the first output signal to obtain a compensated positive high-frequency signal;
the negative differential input signal comprises a third input signal and a fourth input signal; the forward path of the second equalizing module comprises inverters I connected in series in sequence d8 Phase inverter I connected end to end d9 And an inverter I d10 From said inverter I, a third input signal d8 Input, slave inverter I d10 Outputting to obtain a third output signal; the high-pass channel of the second equalizing module comprises inverters I which are connected in series in sequence d11 Phase inverter I connected end to end d12 Capacitor C d2 Phase inverter I connected end to end d13 And an inverter I d14 (ii) a Second input signal slave inverter I d11 Input, slave inverter I d14 Outputting to obtain a fourth output signal; and adding the third output signal and the fourth output signal to obtain a compensated negative high-frequency signal.
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| CN107094034A (en) * | 2012-12-27 | 2017-08-25 | 英特尔公司 | High-speed receiver circuit and method |
| CN111835305A (en) * | 2020-07-01 | 2020-10-27 | 牛芯半导体(深圳)有限公司 | Novel programmable linear equalization circuit |
| CN115242586A (en) * | 2022-09-21 | 2022-10-25 | 中国人民解放军国防科技大学 | Continuous time linear equalizer circuit based on inverter |
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| GB201406525D0 (en) * | 2014-04-11 | 2014-05-28 | Ibm | Continuous, time linear equalizer for high-speed receiving unit |
| US9503053B1 (en) * | 2015-05-13 | 2016-11-22 | Qualcomm Incorporated | Active balun for wideband applications |
| CN115242585B (en) * | 2022-09-21 | 2022-12-09 | 中国人民解放军国防科技大学 | Continuous time linear equalizer circuit based on feedforward technique |
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|---|---|---|---|---|
| CN107094034A (en) * | 2012-12-27 | 2017-08-25 | 英特尔公司 | High-speed receiver circuit and method |
| CN111835305A (en) * | 2020-07-01 | 2020-10-27 | 牛芯半导体(深圳)有限公司 | Novel programmable linear equalization circuit |
| CN115242586A (en) * | 2022-09-21 | 2022-10-25 | 中国人民解放军国防科技大学 | Continuous time linear equalizer circuit based on inverter |
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| Jay Im et al ; .A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.《IEEE》.2020,第7-18页. * |
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