CN115513339B

CN115513339B - Solar cell and preparation and photovoltaic module thereof

Info

Publication number: CN115513339B
Application number: CN202211003091.5A
Authority: CN
Inventors: 武禄; 孙士洋; 杨苗; 曲铭浩; 徐希翔
Original assignee: Longi Green Energy Technology Co Ltd
Current assignee: Longi Green Energy Technology Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2024-08-02
Anticipated expiration: 2042-08-19
Also published as: CN115513339A

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaics. The preparation method comprises the following steps: forming a front passivation antireflection layer on a light-facing surface of a silicon substrate; patterning the front passivation anti-reflection layer to expose the light facing surface of the silicon substrate; forming a front passivation contact structure on the exposed light-facing surface of the silicon substrate; forming a front electrode on the front passivation contact structure; the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate. The invention at least reduces the times of patterning, simplifies the process and improves the production efficiency of the solar cell. The partial passivation contact structure is formed at the contact part of the front electrode, so that parasitic absorption of light can be effectively reduced, the short-circuit current and the photoelectric conversion efficiency of the solar cell are improved, the uncovered part of the front electrode is not doped, the silicon substrate is covered by the front passivation anti-reflection layer, and a good passivation anti-reflection effect is achieved.

Description

Solar cell and preparation and photovoltaic module thereof

Technical Field

The invention relates to the technical field of photovoltaics, in particular to a solar cell, a preparation method thereof and a photovoltaic module.

Background

Passivation contact structures can provide excellent silicon interface passivation properties and are therefore widely used in solar cells.

However, the existing solar cell with the passivation contact structure on the light facing surface has complex preparation process, which results in lower production efficiency of the solar cell.

Disclosure of Invention

The invention provides a solar cell, a preparation method thereof and a photovoltaic module, and aims to solve the problems that the production efficiency of the solar cell is low due to complex preparation process of the existing solar cell with a passivation contact structure on a light facing surface.

In a first aspect of the present invention, there is provided a method of manufacturing a solar cell, the method comprising:

forming a front passivation antireflection layer on a light-facing surface of a silicon substrate;

patterning the front passivation anti-reflection layer to expose the light facing surface of the silicon substrate;

Forming a front passivation contact structure on the exposed light-facing surface of the silicon substrate;

Forming a front electrode on the front passivation contact structure; and the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate.

In the invention, the front passivation anti-reflection layer is subjected to patterning treatment firstly, so that the light facing surface part of the silicon substrate is exposed, and the front passivation contact structure is formed on the exposed light facing surface of the silicon substrate, so that the local passivation contact structure is formed by only one patterning, at least the number of patterning times is reduced, the process is simplified, and the production efficiency of the solar cell is improved. Meanwhile, the local passivation contact structure can effectively reduce parasitic absorption of light, and improves short-circuit current and photoelectric conversion efficiency of the solar cell. Meanwhile, a front electrode is formed on the front passivation contact structure, the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate, that is, the uncovered part of the front electrode is not doped, and the silicon substrate is covered by the front passivation anti-reflection layer, so that a good passivation anti-reflection effect is achieved, the short-circuit current density can be further improved, and the short-circuit current and the photoelectric conversion efficiency of the solar cell are further improved. And the local passivation contact structure is only positioned at the part covered by the front electrode, the local passivation contact structure only needs to pay attention to the electrical property, the optical property is not required to pay attention to, the process window for preparing the passivation contact structure is widened, the selection range of the conductive material in the front passivation contact structure is widened, the conductive material with low light transmittance is generally lower in cost compared with the conductive material with high light transmittance, and the production cost of the solar cell can be reduced.

Optionally, forming a front passivation contact structure on the exposed light facing surface of the silicon substrate includes:

Forming the front passivation contact structure on the bare light facing surface of the silicon substrate and the rest front passivation anti-reflection layer; after forming the front electrode, the method further comprises: and removing the part, which is not covered by the front electrode, of the front passivation contact structure by taking the front electrode as a mask.

Optionally, the forming the front passivation contact structure on the exposed light-facing surface of the silicon substrate and the remaining front passivation anti-reflection layer includes:

Forming a tunneling oxide layer on the exposed light-facing surface of the silicon substrate;

Forming a doped polysilicon layer on the tunneling oxide layer and the remaining front passivation anti-reflection layer;

the removing, with the front electrode as a mask, a portion of the front passivation contact structure not covered by the front electrode includes:

And removing the part of the doped polysilicon layer which is not covered by the front electrode by taking the front electrode as a mask.

Sequentially forming a front intrinsic amorphous silicon passivation layer and a front doping layer on the bare light-facing surface of the silicon substrate and the rest front passivation anti-reflection layer; the front doped layer is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer;

and removing the parts of the front intrinsic amorphous silicon passivation layer and the front doped layer which are not covered by the front electrode by taking the front electrode as a mask.

Sequentially forming a front intrinsic amorphous silicon passivation layer, a front doping layer and a front TCO layer on the bare light-facing surface of the silicon substrate and the rest front passivation anti-reflection layer; the front doped layer is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer;

and removing the parts of the front intrinsic amorphous silicon passivation layer, the front doped layer and the front TCO layer which are not covered by the front electrode by taking the front electrode as a mask.

Optionally, after the front-side passivation contact structure is formed, the method further comprises: sequentially forming a back intrinsic amorphous silicon passivation layer, a back doped layer and a back TCO layer on the back light surface of the silicon substrate; the back doped layer is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer;

and forming a back electrode on the back TCO layer.

Optionally, in the front passivation contact structure, a thickness of an outermost layer farthest from the silicon substrate is 10 to 300nm, and forming a front electrode on the front passivation contact structure includes:

Electroplating a front electrode layer on the outermost layer, wherein in the electroplating process, the electroplating rate of the front electrode layer in the area corresponding to the exposed light facing surface of the silicon substrate is larger than that of the front electrode layer in the rest area of the outermost layer, and the thickness of the obtained front electrode layer in the part corresponding to the exposed light facing surface of the silicon substrate is larger than that of the rest part of the front electrode layer;

And removing the part with smaller thickness in the front electrode layer to form the front electrode.

Optionally, the removing, with the front electrode as a mask, portions of the front intrinsic amorphous silicon passivation layer, the front doped layer, and the front TCO layer that are not covered by the front electrode includes:

using the front electrode as a mask, and removing the part of the front TCO layer which is not covered by the front electrode by adopting an acid solution so that the front doped layer part is exposed;

and removing the exposed part of the front surface doped layer and the part of the front surface intrinsic amorphous silicon passivation layer corresponding to the exposed front surface doped layer by adopting alkaline solution.

Optionally, the silicon substrate is an N-type silicon substrate, and the forming a doped polysilicon layer on the tunneling oxide layer and the remaining front passivation anti-reflection layer includes:

Depositing an amorphous silicon layer and/or a polycrystalline silicon layer on the tunneling oxide layer and the rest front passivation anti-reflection layer, carrying out phosphorus doping treatment on the amorphous silicon layer and/or the polycrystalline silicon layer to form a phosphorus doped polycrystalline silicon layer, and forming a front phosphosilicate glass layer on the phosphorus doped polycrystalline silicon layer while carrying out phosphorus doping treatment; the thickness of the front-side phosphosilicate glass layer is 5 to 50nm.

Depositing an in-situ phosphorus-doped amorphous silicon layer and/or an in-situ phosphorus-doped polysilicon layer on the tunneling oxide layer and the rest front passivation anti-reflection layer, and annealing to form a phosphorus-doped polysilicon layer, and thermally oxidizing the phosphorus-doped polysilicon layer in an oxygen atmosphere to form a front phosphorus-silicon glass layer; the thickness of the front-side phosphosilicate glass layer is 5 to 50nm.

Optionally, after forming the front-side phosphosilicate glass layer, the method further comprises:

And etching the back surface of the silicon substrate by taking the front phosphosilicate glass layer as a mask layer of the front passivation anti-reflection layer, and then removing the front phosphosilicate glass layer.

Optionally, the front passivation anti-reflection layer includes a front passivation layer and a front anti-reflection layer, and a material of the front passivation layer is selected from the group consisting of: at least one of intrinsic amorphous silicon, silicon oxide, phosphosilicate glass, aluminum oxide and phosphosilicate glass;

the material of the front anti-reflection layer is selected from the following materials: at least one of silicon nitride, silicon carbide, titanium oxide, silicon oxide, magnesium fluoride, silicon oxynitride, TCO.

Optionally, the front anti-reflection layer has a single-layer or laminated structure.

Optionally, the refractive index of the front side anti-reflection layer decreases in a direction away from the silicon substrate.

Optionally, the front side anti-reflection layer includes a silicon nitride film and a magnesium fluoride film, wherein the silicon nitride film is closer to the silicon substrate.

Optionally, the doped polysilicon layer contains carbon element and/or oxygen element.

In a second aspect of the present invention, a solar cell is provided, which is prepared by any one of the aforementioned methods for preparing a solar cell.

In a third aspect of the present invention, a photovoltaic module is provided, comprising a string of cells formed by a plurality of solar cells as described above connected in series.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a flow chart of steps of a solar cell in an embodiment of the invention;

fig. 2 is a schematic diagram showing a manufacturing process structure of a first solar cell according to an embodiment of the present invention;

FIG. 3 is a schematic diagram showing a manufacturing process of a second solar cell according to an embodiment of the present invention;

fig. 4 is a schematic diagram showing a structure of a manufacturing process of a third solar cell according to an embodiment of the present invention;

fig. 5 is a schematic diagram showing a manufacturing process structure of a fourth solar cell according to an embodiment of the present invention;

fig. 6 is a schematic diagram showing a structure of a manufacturing process of a fifth solar cell in the embodiment of the present invention;

Fig. 7 is a schematic view showing a structure of a manufacturing process of a sixth solar cell according to an embodiment of the present invention;

fig. 8 is a schematic view showing a manufacturing process structure of a seventh solar cell in the embodiment of the present invention;

fig. 9 is a schematic view showing a structure of a manufacturing process of an eighth solar cell in the embodiment of the present invention;

fig. 10 is a schematic view showing a structure of a manufacturing process of a ninth solar cell according to an embodiment of the present invention;

Fig. 11 is a schematic view showing a structure of a manufacturing process of a tenth solar cell in the embodiment of the present invention;

fig. 12 is a schematic view showing the structure of a first solar cell in the embodiment of the present invention;

Fig. 13 shows a schematic structural diagram of a second solar cell in an embodiment of the present invention.

Reference numerals illustrate:

1-front electrode, 2-front antireflection layer, 3-front passivation layer, 4-1-doped polysilicon layer, 4-2-front doped layer, 5-1-tunneling oxide layer, 5-2-front intrinsic amorphous silicon passivation layer, 6-silicon substrate, 7-back intrinsic amorphous silicon passivation layer, 8-back doped layer, 9-back TCO layer, 10-back electrode, 11-front PSG layer, 12-back PSG layer.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Fig. 1 shows a flow chart of steps of a solar cell in an embodiment of the invention. Referring to fig. 1, the solar cell includes the steps of:

and 101, forming a front passivation anti-reflection layer on the light-facing surface of the silicon substrate.

The front passivation antireflection layer plays a role in passivating the part of the silicon substrate which is not covered by the front electrode, can obviously reduce the recombination of carriers, and has the effect of reducing the escape reflection of light from the light-facing surface. The formation method of the front passivation anti-reflection layer is not particularly limited.

Fig. 2 is a schematic diagram showing a manufacturing process structure of a first solar cell in an embodiment of the present invention. Fig. 3 is a schematic diagram showing a manufacturing process structure of a second solar cell according to an embodiment of the present invention. Referring to fig. 3, optionally, the front passivation anti-reflection layer includes a front passivation layer 3 and a front anti-reflection layer 2, where the front passivation layer 3 is overlapped with the front anti-reflection layer 2 to play a passivation role on a part of the silicon substrate 6 uncovered by the front electrode 1, so that recombination of carriers can be obviously reduced, and the front anti-reflection layer 2 has a function of reducing escape reflection of light from the light facing surface.

The front passivation layer 3 may be formed by, but not limited to, thermal oxidation or the like, for example, thermal oxidation to produce SiO ₂, phosphorus diffusion to produce PSG (Phospho SILICATE GLASS ), or a combination process of both. The preparation of SiO ₂ by a thermal oxidation method can be as follows: the silicon substrate 6 was placed in a tube apparatus at a reaction temperature of 500 to 1000 c, an oxygen flow rate of 0.1 to 20sccm (standard cubic CENTIMETER PER minutes, standard state ml/min) and a reaction time of 10 to 120 minutes. The preparation method of the other front passivation layer 3 is not limited.

Alternatively, the material of the front passivation layer 3 may be selected from: at least one of intrinsic amorphous silicon, silicon oxide, phosphosilicate glass, aluminum oxide and phosphosilicate glass. The material has good passivation effect, can reduce surface recombination, improves short-circuit current density, further improving the short-circuit current, the open-circuit voltage and the photoelectric conversion efficiency of the solar cell.

For example, the material of the front passivation layer 3 may be: the material of the silicon oxide, or the front passivation layer 3, may be: the material of the phosphosilicate glass, or the front passivation layer 3, may be: alumina and phosphosilicate glass. As another example, the material of the front passivation layer 3 may be: silica, alumina and phosphosilicate glass.

The front side anti-reflection layer 2 is formed by, but not limited to, PECVD (PLASMA ENHANCED CHEMICAL Vapor Deposition), PVD (Physical Vapor Deposition ), ALD (Atomic layer Deposition, atomic layer Deposition) and the like.

Optionally, the material of the front anti-reflection layer 2 is selected from: at least one of silicon nitride, silicon carbide, titanium oxide, silicon oxide, magnesium fluoride, silicon oxynitride, TCO. The material has good anti-reflection effect, can reduce surface recombination, improves short-circuit current density, and further improves short-circuit current, open-circuit voltage and photoelectric conversion efficiency of the solar cell.

For example, siN _x、SiC_x、TiO_x or other film layers with refractive index close to that of the silicon substrate 6 are prepared by PECVD, siO _x、SiO_xN_y、MgF₂.SiO_x or SiO _xN_y can be stacked on the outermost layer of the silicon substrate 6, mgF ₂ can be prepared by PVD, and film layers with lower refractive index such as MgF ₂ can improve the antireflection effect. For example, the front-side anti-reflection layer 2 of a single SiN _x material may be specifically prepared by placing the silicon substrate 6 on which the front-side passivation layer 3 is formed in PECVD, where the deposition temperature is 200 to 600 ℃, the reaction gas is a mixed gas of SiH ₄ and NH ₃, the total flow rate is 100 to 50000sccm, the volume ratio of SiH ₄ and NH ₃ is (1:2) to (1:40), the power is 1 to 20kW, the pressure is 20 to 400Pa, and finally the thickness of the front-side anti-reflection layer 2 may be 50 to 90nm. The other front side antireflection layer 2 is not limited in the manner of preparation.

In the chemical formulas, x and y are each a number greater than 0, and specific numerical values are not limited. Referring to fig. 2, before performing step 101, the method may further include: and (5) texturing treatment. For example, an N-type silicon substrate having a resistivity of 0.1 to 10 Ω cm (ohm cm) and a thickness of 50 to 400 μm is subjected to a texturing process to obtain a textured surface. For example, the silicon substrate can be obtained by surface texturing and cleaning a single crystal silicon wafer prepared by an N-type Czochralski method (or a zone-melting method, an ingot casting method, or the like). In addition, the texturing process may be performed using an alkaline solution containing KOH or NaOH, and the temperature may be 60 to 85 ℃. And then adopting a No. 2 solution or a mixed solution of alkali and H ₂O₂ in an RCA standard cleaning method to clean the surface of the silicon substrate after the texturing to remove surface impurities. Finally, the surface oxide layer may be removed with a solution of HF or NH ₄HF₂ having a concentration of 0.5 to 10% or a mixed solution of one of the two solutions and HCl to obtain the above-mentioned silicon substrate 6. In the present invention, the remaining texturing modes are not particularly limited.

Optionally, the front anti-reflection layer 2 is of a single-layer or laminated structure, the front anti-reflection layer 2 is flexible and various in structure, and the anti-reflection effect is good.

Alternatively, the refractive index of the front side antireflection layer 2 decreases in a direction away from the silicon substrate 6, and the refractive index of the front side antireflection layer 2 decreases in a direction away from the silicon substrate 6, so that the antireflection effect is better.

Optionally, the front anti-reflection layer 2 includes a silicon nitride film and a magnesium fluoride film, wherein the silicon nitride film is close to the silicon substrate, the refractive index of the magnesium fluoride film is smaller than that of the silicon nitride film, the anti-reflection effect is better, and the material of the front anti-reflection layer 2 is easy to obtain and has lower cost.

And 102, performing patterning treatment on the front passivation anti-reflection layer to expose the light facing surface part of the silicon substrate.

Fig. 4 is a schematic diagram showing a manufacturing process structure of a third solar cell according to an embodiment of the present invention. As shown with reference to fig. 4, the patterning process herein may be a laser process or the like. The size of the exposed portion of the light-facing surface of the silicon substrate 6 can be adapted to the size of the subsequent front electrode 1.

Optionally, the step 102 may include: at least one of laser, printing corrosion slurry and spraying corrosion slurry is adopted to open the partial areas of the front passivation layer 3 and the front anti-reflection layer 2. The patterning processing mode is flexible and various.

Alternatively, the front passivation layer 3 and the front anti-reflection layer 2 are locally opened by laser, the wavelength of the laser may be 100 to 800nm, the pulse width may be 100fs (femto seconds, 1fs= ^-15 s) to 1ms, and the frequency may be 100kHz to 100MHz. The laser is more common and has lower cost, and openings are easy to form for the front passivation layer 3 and the front anti-reflection layer 2 of the materials.

Alternatively, the wavelength of the laser can be 532nm or 355nm, the pulse width can be 1ps to 500ns, the laser spot shape is square or round, the length or diameter of the spot is 0.5 to 50 μm, the output power is 1 to 100W, and the linear velocity is 1 to 100m/s. The laser is more common and less costly, and openings are easier to form for the front passivation layer 3 and the front anti-reflection layer 2 of the above materials.

For example, the pulse width of the laser light opening to the partial region of the front passivation layer 3 and the front anti-reflection layer 2 is one of 1ps, 300ps, 1100ps, 2ns, 2.5ns, 250ns, 360ns, 440ns, 500ns, the laser spot shape is square or circular, the length or diameter of the spot is 0.5 μm, 2.3 μm, 6.5 μm, 14.6 μm, 25 μm, 25.5 μm, 30 μm, 37.8 μm, 50 μm, the output power is 1W, 20W, 48W, 50W, 63W, 74W, 87W, 100W, the linear velocity is 1m/s, 21m/s, 45m/s, 50m/s, 56m/s, 70m/s, 80m/s, 86m/s, 90m/s, 100m/s.

Alternatively, the width of the opening here may be 1 to 60 μm. The width of the opening is substantially equal to the width of the subsequently formed front electrode 1. The plane defined by the length and width of the opening is perpendicular to the lamination direction of the front passivation layer 3 and the front anti-reflection layer 2, and the length of the opening may be greater than or equal to the width of the opening.

Fig. 5 is a schematic diagram showing a manufacturing process structure of a fourth solar cell according to an embodiment of the present invention. Referring to fig. 5, optionally, after patterning the front passivation layer 3 and the front anti-reflection layer 2 so that the light facing surface portion of the silicon substrate 6 is exposed, the method may further include: the patterned silicon substrate 6 is subjected to processes such as texturing, etching, alkali polishing and the like, and the etching can be acid etching. Specifically, DI water cleaning and RCA-like oxidation cleaning may be performed first, and then the formed structure is placed in a tank cleaner, and a texturing process is performed using an alkaline solution containing KOH or NaOH under the protection of the front passivation layer 3 and the front anti-reflection layer 2 at a temperature of 60 to 85 ℃. Before the texturing, alkali polishing pretreatment may be performed to obtain a preferable surface morphology, and after the texturing, surface modification may be performed, for example, surface rounding treatment using HNO ₃ or HF. The acid etched surface adopts a groove type etching process, wherein a process groove can comprise HNO ₃, HF and other solutes, and a surface with certain roughness is formed after the surface is subjected to texturing. The alkali polishing surface is subjected to an alkali solution system, such as KOH or NaOH, to form a relatively flat surface.

And 103, forming a front passivation contact structure on the exposed light facing surface of the silicon substrate.

In step 102, the light-facing surface of the silicon substrate 6 is partially exposed, and in this step, a front passivation contact structure, that is, a local front passivation contact structure, is formed on the exposed light-facing surface of the silicon substrate 6. The local front passivation contact structure can effectively inhibit contact recombination and surface recombination, reduces contact resistance of a front contact area, and improves open-circuit voltage, short-circuit current and photoelectric conversion efficiency of the solar cell. Meanwhile, a front electrode is formed on the front passivation contact structure, the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate, that is, the uncovered part of the front electrode is not doped, and the silicon substrate is covered by the front passivation anti-reflection layer, so that a good passivation anti-reflection effect is achieved, the surface recombination and the contact recombination can be further reduced, the short circuit current density is improved, and the short circuit current, the open circuit voltage and the photoelectric conversion efficiency of the solar cell are further improved. And the local passivation contact structure is only positioned at the part covered by the front electrode, the local passivation contact structure only needs to pay attention to the electrical property, the optical property is not required to pay attention to, the process window for preparing the passivation contact structure is widened, the selection range of the conductive material in the front passivation contact structure is widened, the conductive material with low light transmittance is generally lower in cost compared with the conductive material with high light transmittance, and the production cost of the solar cell can be reduced.

Optionally, the step 103 may include: and forming the front passivation contact structure on the exposed light-facing surface of the silicon substrate and the rest front passivation anti-reflection layer. Fig. 6 is a schematic diagram showing a manufacturing process structure of a fifth solar cell in the embodiment of the present invention. Referring to fig. 6, a front passivation contact structure is formed on the exposed light-facing surface of the silicon substrate 6, and the remaining front passivation layer 3 and front anti-reflection layer 2. The manner in which the front passivation contact structure is formed may be particularly related to the material of the front passivation contact structure, etc.

For example, referring to fig. 6, fig. 6 shows that 5-1 may be a tunnel oxide layer, 4-1 may be a doped polysilicon layer, and the main material of the tunnel oxide layer 5-1 may be SiO _x (silicon oxide) or may be doped with an inorganic element such as N, P. The front passivation contact structure of the structure has excellent silicon interface passivation performance, and is simple in process and easy to prepare.

Optionally, the step 103 may further include: a tunneling oxide layer 5-1 is formed on the exposed light-facing surface of the silicon substrate 6, and a doped polysilicon layer 4-1 is formed on the tunneling oxide layer 5-1 and the remaining front passivation anti-reflection layer, such as the front anti-reflection layer 2. The tunnel oxide layer 5-1 is more likely to grow on the silicon substrate 6 than the front side anti-reflection layer 2, and substantially does not grow on the front side anti-reflection layer 2, and thus the tunnel oxide layer 5-1 is formed mainly on the silicon substrate 6.

Optionally, the tunnel oxide layer 5-1 may be formed by at least one of thermal oxidation, wet oxidation, PECVD, and ALD, where the tunnel oxide layer 5-1 is disposed on a bare light facing surface of the silicon substrate 6. It should be noted that, the tunnel oxide layer generally grows only on the silicon substrate 6, but does not grow on the front side anti-reflection layer 2, specifically because, on one hand, the tunnel oxide layer 5-1 grows more easily on the silicon substrate 6, but does not grow on the front side anti-reflection layer 2, and on the other hand, the front side anti-reflection layer 2 does not react substantially in the preparation manner of the tunnel oxide layer 5-1, so that the tunnel oxide layer 5-1 is formed on only the exposed part of the light facing surface of the silicon substrate 6.

For example, the tunnel oxide layer 5-1 is thermally oxidized at a temperature of: the oxidizing agent of the wet oxidation at 200 to 800 ℃ can be HNO ₃、O₃、H₂O₂ and the like, gas SiH ₄ introduced in PECVD can be used as a silicon source, N ₂ O and/or CO ₂ can be used as an oxygen source, TMS (tetramethylsilane) can be introduced in ALD can be used as a silicon source, H ₂ O and/or O ₃ and the like can be used as oxygen sources. Specifically, for example, in a thermal oxidation preparation mode, the N-type silicon substrate 6 is placed in a quartz boat, and a layer of silicon oxide of 0.5 to 2nm is deposited on the surface of the N-type silicon substrate 6 at a temperature of 300 to 700 ℃. The reaction gas used for deposition is O ₂, the flow rate of which can be 0.1 to 20slm (STANDARD LITRE PER minutes, in standard conditions, liters per minute), the deposition pressure can be 100Pa to normal pressure, the specific thermal oxidation mode can be constant oxygen flow rate, variable oxygen flow rate and the like, and the total oxygen ventilation time period can be 5 to 120 minutes. The preparation method of the other tunnel oxide layer 5-1 is not particularly limited.

The main material of the doped polysilicon layer 4-1 may be Si, and the formation mode of the doped polysilicon layer 4-1 may be: the intrinsic polycrystalline silicon with low crystallization rate is formed first, then the doped polycrystalline silicon layer 4-1 with high crystallization rate is prepared, and the doped polycrystalline silicon layer 4-1 with high crystallization rate can also be formed at one time. Intrinsic polysilicon is prepared by methods including, but not limited to, APCVD (Atmospheric Pressure Chemical Vapor Deposition ), LPCVD (Low Pressure Chemical Vapor Deposition low pressure chemical vapor deposition), PECVD, PVD, and the like. For example, the reaction temperature of LPCVD may be 400 to 700 ℃, the gas feed may be SiH ₄, and the PECVD gas feed may be SiH ₄. Specifically, for example, LPCVD is used for preparing intrinsic polysilicon, the preparation is directly carried out after the preparation of the tunneling oxide layer 5-1, and the tunneling oxide layer 5-1 and the intrinsic polysilicon can be completed by one integrated process. Specifically, an intrinsic polysilicon layer with a thickness of 10 to 300nm is deposited on the tunneling oxide layer 5-1 at a temperature of 400 to 700 ℃. The preferred thickness of the intrinsic polysilicon layer is 10 to 100nm. The reaction gas used for depositing the intrinsic polycrystalline silicon layer is SiH ₄, the flow rate is 50-1000 sccm, the deposition pressure is 100-400 Pa, and the time is 2-30 min. When the LPCVD is adopted for preparation, the inserting sheet mode can be a single sheet or double sheets, and the inserting sheet mode can not cause great influence on the process flow. The preparation method of the other intrinsic polycrystalline silicon is not particularly limited.

The direction in which the thickness is located is identical to the lamination direction of the front passivation layer 3 and the front anti-reflection layer 2, or the direction in which the thickness is located is identical to the lamination direction of the front electrode and the front passivation contact structure, and the directions in which the thicknesses are mentioned throughout are defined as such.

Alternatively, the silicon substrate 6 may be an N-type silicon substrate, and forming the doped polysilicon layer 4-1 may include: depositing an amorphous silicon layer and/or a polycrystalline silicon layer on the tunneling oxide layer 5-1 and the rest front passivation anti-reflection layer, and carrying out phosphorus doping treatment on the amorphous silicon layer and/or the polycrystalline silicon layer to form a phosphorus doped polycrystalline silicon layer; simultaneously with the phosphorus doping treatment, a PSG layer 11 with a thickness of 5 to 50nm is generated on the surface of the doped polysilicon layer 4-1. The process mode is mature and stable, and the formed doped polysilicon layer 4-1 has better quality.

Alternatively, the silicon substrate 6 may be an N-type silicon substrate, and the formation of the doped polysilicon layer 4-1 may include: and depositing an in-situ phosphorus-doped amorphous silicon layer and/or an in-situ phosphorus-doped polysilicon layer on the tunneling oxide layer 5-1 and the rest front passivation anti-reflection layer, and annealing to form a phosphorus-doped polysilicon layer, wherein the front phosphorus-silicon glass layer is formed by thermal oxidation on the phosphorus-doped polysilicon layer in an oxygen atmosphere in the annealing process and/or after annealing, and the thickness of the front phosphorus-silicon glass layer is 5-50 nm. The process mode is mature and stable, and the formed doped polysilicon layer 4-1 has better quality.

The main material of the doped polysilicon layer 4-1 is Si, and the main doping element is nitrogen group element such as P. The phosphorus doping treatment can be performed by a phosphorus diffusion (POCl ₃) process, or by post-printing phosphorus paste annealing, etc., to form the doped polysilicon layer 4-1. Specifically, in the thermal diffusion furnace tube, a phosphorus doped polysilicon layer 4-1 is formed on the tunneling oxide layer 5-1 of the surface of the N-type silicon substrate 6 through pre-deposition and promotion by POCl ₃ thermal diffusion, and a front side PSG layer 11 is formed on the phosphorus doped polysilicon layer 4-1. The intrinsic amorphous silicon can be deposited firstly, and then the phosphorus doping treatment is carried out, wherein the phosphorus doping treatment comprises the following steps: the method comprises the steps of pre-depositing a phosphorus source on an intrinsic amorphous silicon layer, forming a PSG on the intrinsic amorphous silicon layer by the pre-depositing phosphorus source, then pushing the PSG, and forming a phosphorus-doped polysilicon layer by pushing phosphorus in the PSG into the intrinsic amorphous silicon layer and crystallizing the phosphorus-doped polysilicon layer. Optionally, the pre-deposited phosphorus source is at a temperature of 700 to 850 ℃ and the deposition time is 5 to 50 minutes. The propelling temperature is 700-1100 ℃, the propelling time is 15-75 min, and the propelling pressure is 100-400 Pa. The thickness of the PSG layer 11 may be 5 to 50nm, and then the sheet resistance of the silicon substrate 6 containing the PSG layer 11 is measured to be 10 to 1000 Ω/sq (ohm/square).

Depositing an in-situ phosphorus doped amorphous silicon layer and/or polysilicon layer on the tunnel oxide layer 5-1 includes, but is not limited to, APCVD, LPCVD, PECVD, PVD and the like. The PECVD process temperature is 400-700 ℃, and the gas is SiH ₄. Specifically, for example, LPCVD is used for preparing in-situ phosphorus doped polysilicon, the preparation is directly carried out after the preparation of tunneling silicon oxide, and the tunneling oxide layer 5-1 and the in-situ phosphorus doped polysilicon can be completed by one-step process. Specifically, a 10-300 nm in-situ phosphorus doped polysilicon layer is deposited on the tunneling oxide layer 5-1 at a temperature of 400-700 ℃. The preferred thickness of the polysilicon layer may be 10 to 100nm. The reaction gases used in the deposition of the polysilicon layer are SiH ₄, PH ₃,SiH₄ and PH ₃, the flow rates are respectively 50-1000 sccm and 2-40 sccm, the deposition pressure is 100-400 Pa, and the time is 5-60 min. When the LPCVD is adopted for preparation, the inserting sheet mode can be a single sheet or double sheets, and the inserting sheet mode can not cause great influence on the process flow. The preparation method of other in-situ phosphorus doped polysilicon is not particularly limited.

Optionally, an in-situ phosphorus-doped amorphous silicon layer and/or a polysilicon layer is deposited on the tunneling oxide layer 5-1, and then the high crystallization rate phosphorus-doped polysilicon layer 4-1 is prepared by annealing, and oxygen can be introduced in the annealing process and/or after the annealing is finished, and a front PSG layer 11 with a certain thickness is generated on the surface of the phosphorus-doped polysilicon layer 4-1 in an oxygen atmosphere. Specifically, in the thermal annealing furnace tube, N ₂ is used for crystallization treatment, and then O ₂ is used for forming the front PSG layer 11 on the phosphorus doped polysilicon layer 4-1. Wherein the temperature of thermal annealing and oxidation is 700-1100 ℃, the annealing time is 15-60 min, the thermal oxidation time is 15-60 min, and the process pressure is 100 Pa-normal pressure. The front side PSG layer 11 has a thickness of 5 to 50nm, and then the sheet resistance of the silicon substrate 6 containing the front side PSG layer 11 is measured to be 10 to 1000 Ω/sq.

Referring to fig. 6, in the process of forming the passivation contact structure, the tunneling oxide layer 5-1, the doped polysilicon layer 4-1, and the back PSG layer 12 may also be formed on the back surface of the silicon substrate 6. Fig. 7 is a schematic view showing a manufacturing process structure of a sixth solar cell in the embodiment of the present invention. Alternatively, referring to fig. 7, the back light surface of the silicon substrate 6 may be etched with the front PSG layer 11 as the front anti-reflection layer 2, that is, the mask layer of the front structure, to remove the tunnel oxide layer 5-1, the doped polysilicon layer 4-1, and the back PSG layer 12 that may be formed on the back light surface of the silicon substrate 6, and then remove the front PSG layer 11. Specifically, but not limited to, single-sided etching, single-sided masking, and then trench etching are performed on the back surface of the silicon substrate 6 to remove the tunneling oxide layer 5-1, the doped polysilicon layer 4-1, and the back PSG layer 12 that may be formed on the back surface of the silicon substrate 6, and to form the features such as an alkaline polished surface, an acid polished surface, or a rounded pyramid texture. For example, the silicon substrate 6 containing the front PSG layer 11 is placed at the feeding position of a single-sided etching machine, a water film is spread on the front side to protect the front side structure, the back side sequentially passes through a HNO ₃/HF/H₂SO₄ mixed solution at 11 ℃ to etch a back PSG layer 12, a doped polysilicon layer 4-1 and a tunneling oxide layer 5-1 possibly formed on the back side of the silicon substrate 6, an acid polished surface with certain roughness is formed on the back side of the silicon substrate 6, then KOH solution at room temperature is entered to remove porous silicon on the back side, then residual k+ is neutralized in HCl/HF solution at room temperature to remove the front side PSG layer 11, and finally N ₂ or CDA (compressed dry air) is introduced at 50 to 80 ℃ to dry.

Fig. 8 is a schematic view showing a manufacturing process structure of a seventh solar cell in the embodiment of the present invention. Optionally, after forming the front passivation contact structure, the method may further include: a back intrinsic amorphous silicon passivation layer 7, a back doped layer 8, and a back TCO layer 9 are sequentially formed on the back surface of the silicon substrate 6. The back doped layer 8 is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer. As shown with reference to fig. 8, after forming the tunnel oxide layer 5-1 and the doped polysilicon layer 4-1, the method may further include: a back intrinsic amorphous silicon passivation layer 7, a back doped layer 8, and a back TCO layer 9 are sequentially formed on the back surface of the silicon substrate 6.

Specifically, the back intrinsic amorphous silicon passivation layer 7 is deposited on the back surface of the silicon substrate 6, including but not limited to PECVD, HWCVD (hot WIRE CHEMICAL vapor deposition) PVD, cat-CVD (CATALYTIC CHEMICAL vapor deposition), ALD, or solution method. Wherein the process temperature of HWCVD is 100-250 ℃, and the gas is SiH ₄、H₂. If a 2-16 nm back intrinsic amorphous silicon passivation layer 7 is deposited by adopting a PECVD method, the reaction gases are SiH ₄ and H ₂, the volume ratio of SiH ₄ and H ₂ in the mixed gas is (1:1) to (1:50), the power density of the power supply is 0.01-0.5W/cm ², the pressure is 20-200 Pa, and the reaction temperature is 100-200 ℃.

A back doped layer 8 is deposited on the back intrinsic amorphous silicon passivation layer 7, the back doped layer 8 being: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer. For example, the back doped layer 8 may be a phosphorus doped amorphous/microcrystalline/nanocrystalline silicon film. The back surface doped layer 8 is formed by methods including, but not limited to PECVD, HWCVD, cat-CVD, PVD, ALD or solution methods. The process temperature of HWCVD is 100-250 ℃, and the gas is SiH ₄、H₂. Specifically, the P-type amorphous, microcrystalline and nanocrystalline doped layers of 10 to 40nm are continuously deposited on the surface of the back intrinsic amorphous silicon passivation layer 7, the reaction gases are SiH ₄、H₂ and B ₂H₆, the volume ratio of SiH ₄ to H ₂ in the mixed gas is (1:1) to (1:50), the volume ratio of SiH ₄ to B ₂H₆ is (5:1) to (100:1), the power density is 0.01 to 0.2W/cm ², the pressure is 20 to 200Pa, and the reaction temperature is 100 to 200 ℃.

The back surface of the back doped layer 8 is deposited with a metal oxide such as ITO, IWO, FTO, AZO or a mixture thereof, or other materials with work functions between the back doped layer 8 and the back electrode 10 of P-type amorphous/microcrystalline/nanocrystalline silicon, and the back TCO layer 9 is formed by, but not limited to, magnetron sputtering, RPD (REACTIVE PLASMA Deposition), vacuum evaporation, PECVD, ALD, and other preparation methods. For example, 75nm of ITO is deposited on the back doped layer 8 by adopting a PVD method, wherein the mass of In element In the ITO is equal to the mass of Sn element In the ITO= (1:1) to (20:1), ar and O ₂ are also filled In the ITO, the flow ratio of O ₂ to Ar is 0.01 to 0.2, the pressure is 0.1 to 5Pa, and the temperature of the silicon substrate 6 is room temperature In the process of preparing the ITO.

Fig. 9 is a schematic diagram showing a manufacturing process structure of an eighth solar cell in the embodiment of the present invention. Referring to fig. 9, optionally, forming the front passivation contact structure on the exposed light facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer may further include: on the bare light-facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer, a front intrinsic amorphous silicon passivation layer 5-2 and a front doped layer 4-2 are sequentially formed, wherein the front doped layer 4-2 may be: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer. The front passivation contact structure of the structure has excellent silicon interface passivation performance, and is simple in process and easy to prepare.

Specifically, a front intrinsic amorphous silicon passivation layer 5-2 is deposited on the bare light facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer by a method including, but not limited to PECVD, HWCVD, cat-CVD, PVD, ALD or a solution method. The PECVD process is at a temperature of 100-250 ℃, and the gas introduced into the PECVD process can be SiH ₄、H₂ and the like. For example, a PECVD method is adopted to deposit a 2-16 nm front intrinsic amorphous silicon passivation layer 5-2, the reaction gases are SiH ₄ and H ₂, the volume ratio of SiH ₄ and H ₂ in the mixed gas is (1:1) to (1:50), the power density of the power supply is 0.01-0.5W/cm ², the pressure is 20-200 Pa, and the reaction temperature is 100-200 ℃.

The front side doped layer 4-2 may be prepared by, but not limited to, PECVD, HWCVD, cat-CVD, PVD, ALD or solution methods. For example, the PECVD process temperature is 100-250 ℃, and the introduced gas can be SiH ₄、H₂. For example, a 10 to 40nm P-type amorphous/microcrystalline/nanocrystalline silicon doped layer is continuously deposited on the surface of the front intrinsic amorphous silicon passivation layer 5-2, the reaction gases are SiH ₄、H₂ and B ₂H₆, the volume ratio of SiH ₄、H₂ in the mixed gas is (1:1) to (1:50), the volume ratio of SiH ₄ to B ₂H₆ is (5:1) to (100:1), the power density of the power supply is 0.01 to 0.2W/cm ², the pressure is 20 to 200Pa, and the reaction temperature is 100 to 200 ℃.

Referring to fig. 9, optionally, the method may further include: a back intrinsic amorphous silicon passivation layer 7, a back doped layer 8 and a back TCO layer 9 are sequentially formed on the back surface of the silicon substrate 6, and the back doped layer 8 is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer. The back intrinsic amorphous silicon passivation layer 7 may be formed in the same manner as the front intrinsic amorphous silicon passivation layer 5-2. The formation mode of the back doped layer 8 can be identical with that of the front doped layer 4-2, and the process method is simple, saves labor hour and has high production efficiency.

The preparation of the back TCO layer 9 refers to the preparation of the back TCO layer 9 described above, and is not repeated here.

Optionally, forming the front passivation contact structure on the exposed light facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer may further include: on the exposed light-facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer, a front intrinsic amorphous silicon passivation layer 5-2, a front doped layer 4-2, and a front TCO layer (not shown in the figure) are sequentially formed, and the front doped layer 4-2 may be: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer. The front passivation contact structure of the structure has excellent silicon interface passivation performance, and is simple in process and easy to prepare.

The intrinsic amorphous silicon passivation layer 5-2 and the front surface doped layer 4-2 may be referred to in the above description correspondingly, and in order to avoid repetition, the description is omitted here. The preparation of the front TCO layer can be referred to the preparation of the back TCO layer 9 described above, and will not be repeated here.

Optionally, the doped polysilicon layer 4-1 of the front passivation contact structure contains carbon element and/or oxygen element, which can improve the light transmittance of the front passivation contact structure and reduce the resistance. The specific content of the carbon element and/or the oxygen element is not particularly limited. It is also possible that the front side doped layer 4-2 of the front side passivation contact structure contains carbon elements and/or oxygen elements.

It should be noted that the front passivation contact structure may form a high-low junction with the silicon substrate 6, and the back doped layer 8 located on the back surface of the silicon substrate 6 and the back intrinsic amorphous silicon passivation layer 7 may form a heterojunction.

104, Forming a front electrode on the front passivation contact structure; and the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate.

Fig. 10 is a schematic view showing a structure of a manufacturing process of a ninth solar cell in the embodiment of the present invention. Fig. 11 is a schematic view showing a manufacturing process structure of a tenth solar cell in the embodiment of the present invention. As shown in fig. 10 and 11, the front electrode 1 is formed on the front passivation contact structure. And the projection of the front electrode 1 on the light-facing surface of the silicon substrate 6 is positioned on the light-facing surface exposed by the silicon substrate 6, so that the projection of the front electrode 1 on the light-facing surface of the silicon substrate 6 falls into the projection of the front passivation contact structure on the light-facing surface of the silicon substrate 6. The front electrode 1 may be formed by screen printing, laser transfer, electroplating, vapor deposition, or by other patterning means such as photolithography.

Alternatively, the thickness of the outermost layer of the front-side passivation contact structure furthest from the silicon substrate 6 is 10 to 300nm, for example 10 to 100nm. The thickness of the outermost layer of the front side passivation contact structure furthest from the silicon substrate 6 may be 10nm, 30nm, 40nm, 60nm, 80nm, 90nm, 100nm, 150nm, 200nm, 260nm, 300nm. The step 104 may include: and electroplating the front electrode layer on the outermost layer, wherein in the electroplating process, the electroplating rate of the front electrode layer in the area corresponding to the exposed light-facing surface of the silicon substrate 6 in the outermost layer is larger than that of the front electrode layer in the rest area of the outermost layer, so that the thickness of the obtained front electrode layer in the part corresponding to the exposed light-facing surface of the silicon substrate 6 is larger than that of the rest part of the front electrode layer, and then removing the part with smaller thickness in the front electrode layer to form the front electrode 1.

Specifically, the thickness of the outermost layer farthest from the silicon substrate 6 in the front passivation contact structure is 10 to 300nm, the thickness of the outermost layer is smaller, in the thickness range, the area corresponding to the exposed light facing surface of the silicon substrate 6 in the outermost layer is affected by the silicon substrate 6, the resistivity of the area is small relative to the resistivity of other areas of the outermost layer, therefore, in the electroplating process, the electroplating rate of the area corresponding to the exposed light facing surface of the silicon substrate 6 in the outermost layer is faster, the total electroplating time is equal, a front electrode layer with unequal thickness is obtained, the thicker part is the part corresponding to the exposed light facing surface of the silicon substrate 6, and the part with smaller thickness is removed, so that the front electrode 1 is obtained, and further, the accurate alignment of the front electrode 1 is realized while the process is simpler.

The resistivity of the region of the outermost layer corresponding to the exposed light-facing surface of the silicon substrate 6 and the resistivity of the remaining region of the outermost layer are not particularly limited. The plating rate of the area of the front electrode layer in the outermost layer corresponding to the bare light-facing surface of the silicon substrate 6, the plating rate of the front electrode layer in the rest of the outermost layer, the difference between the two plating rates are not particularly limited. The thickness of the portion of the front electrode layer corresponding to the exposed light-facing surface of the silicon substrate 6 in the outermost layer, and the thickness of the remaining portion of the front electrode layer are not particularly limited, either. The part of the front electrode layer with smaller thickness can be removed by laser etching, wet etching and other modes, and the method is not particularly limited.

As shown in fig. 10, the front passivation contact structure is composed of a tunneling oxide layer 5-1 and a doped polysilicon layer 4-1, wherein the doped polysilicon layer 4-1 is the outermost layer farthest from the silicon substrate 6 in the front passivation contact structure, the thickness of the doped polysilicon layer 4-1 is 10 to 300nm, and further, the thickness of the doped polysilicon layer 4-1 is 10 to 100nm. The thickness of the doped polysilicon layer 4-1 is smaller, in the thickness range, the resistivity of the area of the doped polysilicon layer 4-1 corresponding to the exposed light-facing surface of the silicon substrate 6 is smaller than that of the other areas of the doped polysilicon layer 4-1 due to the influence of the silicon substrate 6, so that the electroplating rate of the area of the doped polysilicon layer 4-1 corresponding to the exposed light-facing surface of the silicon substrate 6 is faster in the electroplating process, the total electroplating time is equal, the front electrode layer with unequal thickness is further obtained, the thicker part is the part corresponding to the exposed light-facing surface of the silicon substrate 6, and the part with smaller thickness is removed, so that the front electrode 1 is obtained.

As another example, referring to fig. 11, the front passivation contact structure is composed of a front intrinsic amorphous silicon passivation layer 5-2 and a front doped layer 4-2, and the outermost layer of the front passivation contact structure farthest from the silicon substrate 6 is the front doped layer 4-2, and the thickness of the front doped layer 4-2 may be 10 to 40nm. The thickness of the front doped layer 4-2 is smaller, in the thickness range, the resistivity of the area of the front doped layer 4-2 corresponding to the exposed light-facing surface of the silicon substrate 6 is smaller than that of the other areas of the front doped layer 4-2 due to the influence of the silicon substrate 6, so that the electroplating speed of the area of the front doped layer 4-2 corresponding to the exposed light-facing surface of the silicon substrate 6 is faster in the electroplating process, the total electroplating time is equal, the front electrode layers with unequal thicknesses are obtained, the thicker parts are the parts corresponding to the exposed light-facing surface of the silicon substrate 6, and the parts with smaller thickness are removed, so that the front electrode 1 is obtained.

Also for example, the front side passivation contact structure is composed of a front side intrinsic amorphous silicon passivation layer 5-2, a front side doped layer 4-2, and a front side TCO layer, the outermost layer of the front side passivation contact structure furthest from the silicon substrate 6 is the front side TCO layer, which may have a thickness of 10 to 160nm. The thickness of the front TCO layer is smaller, in this thickness range, the resistivity of the area corresponding to the exposed light-facing surface of the silicon substrate 6 in the front TCO layer is smaller than that of the other areas of the front TCO layer due to the influence of the silicon substrate 6, so that in the electroplating process, the electroplating rate of the area corresponding to the exposed light-facing surface of the silicon substrate 6 in the front TCO layer is faster, and the total electroplating time is equal, so that the front electrode layer with unequal thickness is obtained, the thicker part is the part corresponding to the exposed light-facing surface of the silicon substrate 6, and the smaller part is removed, thus obtaining the front electrode 1.

Alternatively, the front electrode 1 and the rear electrode 10 may be formed simultaneously. If electroplating is adopted, the area corresponding to the bare light facing surface of the silicon substrate in the front passivation contact structure and the back surface of the back TCO layer 9 form an electrode structure, and the back electrode 10 may be a whole electrode structure. The width of the front electrode 1 is 1 to 50 μm.

The method may further comprise: the back electrode 10 is formed on the back TCO layer, and the back electrode 10 may be formed by referring to the manner of forming the front electrode 1. For example, the same process is used to form the front electrode 1 and the back electrode 10.

In the invention, the front passivation anti-reflection layer is subjected to patterning treatment firstly, so that the light facing surface part of the silicon substrate is exposed, and the front passivation contact structure is formed on the exposed light facing surface of the silicon substrate, so that the local passivation contact structure is formed by only one patterning, at least the number of patterning times is reduced, the process is simplified, and the production efficiency of the solar cell is improved. Meanwhile, the local passivation contact structure can effectively reduce parasitic absorption of light, and improves short-circuit current and photoelectric conversion efficiency of the solar cell. Meanwhile, a front electrode is formed on the front passivation contact structure, the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate, that is, the uncovered part of the front electrode is not doped, and the silicon substrate is covered by the front passivation anti-reflection layer, so that a good passivation anti-reflection effect is achieved, the short-circuit current density can be further improved, and the short-circuit current and the photoelectric conversion efficiency of the solar cell are further improved. And the local passivation contact structure is only positioned at the part covered by the front electrode, the local passivation contact structure only needs to pay attention to the electrical property, the optical property is not required to pay attention to, the process window for preparing the passivation contact structure is widened, the selection range of the conductive material in the front passivation contact structure is widened, the conductive material with low light transmittance is generally lower in cost compared with the conductive material with high light transmittance, and the production cost of the solar cell can be reduced. For example, the photoelectric conversion efficiency of the solar cell prepared by the invention is about 0.5% abs higher than HIT.

Optionally, if the front passivation contact structure is formed on the bare light facing surface of the silicon substrate 6 and the remaining front passivation anti-reflection layer, after forming the front electrode 1, the method may further include: the front electrode 1 is used as a mask to remove the part of the front passivation contact structure not covered by the front electrode 1. The front electrode 1 is used as a mask, the part of the front passivation contact structure which is not covered by the front electrode 1 is removed, the mask is not required to be specially prepared for forming the local passivation contact structure, the patterning step is simplified, the process flow for forming the local passivation contact structure is simplified, and the production cost is greatly reduced.

Fig. 12 shows a schematic structural diagram of a first solar cell in an embodiment of the present invention. Fig. 13 shows a schematic structural diagram of a second solar cell in an embodiment of the present invention. Referring to fig. 12 and 13, portions of the front passivation contact structure not covered by the front electrode 1 are removed using the front electrode 1 as a mask. If the front electrode 1 is used as a mask, the light facing surface of the front passivation contact structure of the silicon substrate 6 forming the front electrode 1 is subjected to wet treatment, and the part of the front passivation contact structure not covered by the front electrode 1 is removed.

Referring to fig. 12, the front passivation contact structure is composed of a tunneling oxide layer 5-1 and a doped polysilicon layer 4-1, and the tunneling oxide layer 5-1 is only formed on the exposed portion of the silicon substrate 6 facing the light surface after the patterning process is performed on the front passivation layer 3 and the front anti-reflection layer 2 in the silicon substrate 6, so that in this step, the area of the doped polysilicon layer 4-1 not protected by the front electrode 1 is mainly removed.

Optionally, with the front electrode 1 as a mask, removing the portion of the doped polysilicon layer 4-1 not covered by the front electrode 1 may include: the front electrode 1 is used as a mask, and an alkaline solution is used to remove the portion of the doped polysilicon layer 4-1 not covered by the front electrode 1, and the specific alkaline solution is not limited. If a single-sided etching process is adopted, the backlight surface faces upwards and the light facing surface faces downwards, the backlight surface structure of the silicon substrate 6 is covered by a water film to be protected, and under the protection of the front electrode 1, the part of the doped polysilicon layer 4-1 which is not covered by the front electrode 1 is removed in a KOH solution with the concentration of 4% at 50 ℃. After removing the part of the doped polysilicon layer 4-1 not covered by the front electrode 1, the surface can be cleaned by neutralizing k+ with 1% HCl and/or HF solution for a short time, and finally drying.

Alternatively, referring to fig. 13, the front passivation contact structure is composed of a front intrinsic amorphous silicon passivation layer 5-2 and a front doped layer 4-2, and the removing the portion of the doped polysilicon layer 4-1 not covered by the front electrode 1 using the front electrode 1 as a mask may include: with the front electrode 1 as a mask, the portion of the front doped layer 4-2 not covered by the front electrode 1 may be removed using an alkaline solution. The specific alkaline solution is not limited. If a single-sided etching process is adopted, the backlight surface faces upwards and the light facing surface faces downwards, the backlight surface structure of the silicon substrate 6 is covered by a water film to be protected, and under the protection of the front electrode 1, the front doped layer 4-2 and the part of the front intrinsic amorphous silicon passivation layer 5-2 which is not covered by the front electrode 1 are removed in a KOH solution with the concentration of 4% at 50 ℃. After removing the parts of the front doped layer 4-2 and the front intrinsic amorphous silicon passivation layer 5-2 not covered by the front electrode 1, the surface can be cleaned by neutralizing k+ with 1% HCl and/or HF solution for a short time, and finally drying.

Optionally, the front passivation contact structure is composed of a front intrinsic amorphous silicon passivation layer 5-2, a front doped layer 4-2 and a front TCO layer, and the removing the portion of the doped polysilicon layer 4-1 not covered by the front electrode 1 using the front electrode 1 as a mask may include: with the front electrode 1 as a mask, the part of the front TCO layer which is not covered by the front electrode 1 can be removed by using an acidic solution, part of the front doped layer 4-2 is exposed, and then the exposed front doped layer and the part of the front intrinsic amorphous silicon passivation layer 5-2 which is not covered by the front electrode 1 are removed by using an alkaline solution. The specific acidic solution and alkaline solution are not limited. If a single-sided etching process is adopted, the backlight surface is upward and the light facing surface is downward, the backlight surface structure of the silicon substrate 6 is covered by a water film to be protected, under the protection of the front electrode 1, the silicon substrate enters into a 4% hydrochloric acid solution, the part of the front TCO layer which is not covered by the front electrode 1 is removed, and the doped polysilicon layer 4-1 and the part of the front intrinsic amorphous silicon passivation layer 5-2 which is not covered by the front electrode 1 are removed in a 4% KOH solution at 50 ℃. Finally, neutralizing K+ with 1% HCl and/or HF solution, cleaning the surface for a short time, and finally drying.

It should be noted that, before the front electrode 1 is used as a mask to remove the portion of the doped polysilicon layer 4-1 not covered by the front electrode 1, a certain thickness of SiO ₂ or other film with protection effect may be deposited on the backlight surface structure of the silicon substrate 6 by ALD method, and after etching, the SiO ₂ or other film with protection effect may be removed by HF solution.

As shown in fig. 12 and 13, in the solar cell provided by the invention, the backlight surface of the silicon substrate 6 can also be a heterojunction structure, so that better passivation and contact performance can be obtained.

The solar cell formed by the invention further comprises the following treatment processes including but not limited to: curing (solidification), sintering (firing), light injection (Light-Induced Regeneration), electric injection (Electric-Induced Regeneration), or dark state annealing (DARK ANNEALING), etc. The present invention is not particularly limited thereto.

It should be noted that the light-facing surface of the silicon substrate 6 is a pyramid-shaped textured surface, and the backlight surface of the silicon substrate 6 is not fixed, for example, the backlight surface of the silicon substrate 6 may be a textured surface, a plane surface, or other types of surfaces. The back electrode 10 may be a gate line or a global film. The solar cell light-facing surface may have a certain height difference except for the suede shape, the height difference may be several μm, and only the longitudinal distribution of the solar cell is shown in the figure. The lateral direction may be perpendicular to the lamination direction of the front side antireflection layer 2 and the front side passivation layer 3. The cross-sectional shapes of the front electrode 1 and the rear electrode 10 are not fixed. For example, the cross-sections of the front electrode 1 and the rear electrode 10 may be square, semicircular, triangular, trapezoidal, or other irregular shapes. The cross section here may be a cross section perpendicular to the lamination direction of the front side antireflection layer 2 and the front side passivation layer 3. All structures in the picture are schematic diagrams and do not represent relative size relations.

The invention also provides a solar cell prepared by any one of the preparation methods of the solar cell, and the solar cell has the same or similar beneficial effects as any one of the preparation methods of the solar cell, and in order to avoid repetition, the description is omitted.

The invention also provides a photovoltaic module, which comprises a plurality of battery strings formed by connecting the solar batteries in series, and has the same or similar beneficial effects as any one of the preparation methods of the solar batteries and the solar batteries, and in order to avoid repetition, the repeated description is omitted.

The invention is further illustrated by the following examples in conjunction with:

Example 1

Referring to fig. 2, a silicon substrate 6 is subjected to a texturing process. Referring to fig. 3, a front passivation layer 3 and a front anti-reflection layer 2 are formed on a light-facing surface of a silicon substrate 6. Referring to fig. 4, the front passivation layer 3 and the front anti-reflection layer 2 are patterned such that the light facing surface portion of the silicon substrate 6 is exposed. Referring to fig. 5, the patterned silicon substrate 6 is textured. Referring to fig. 6, a tunnel oxide layer 5-1, a doped polysilicon layer 4-1, and a front side PSG layer 11 are formed. Referring to fig. 7, the front PSG layer 11 is used as a mask layer of the front structure, and the back surface of the silicon substrate 6 is etched to remove the tunnel oxide layer 5-1, the doped polysilicon layer 4-1, and the back PSG layer 12 that may be formed on the back surface of the silicon substrate 6, and then the front PSG layer 11 is removed. Referring to fig. 8, a back intrinsic amorphous silicon passivation layer 7, a back doped layer 8, and a back TCO layer 9 are sequentially formed on the back surface of the silicon substrate 6. Referring to fig. 10, a front electrode 1 is formed on the doped polysilicon layer 4-1, and a back electrode 10 is formed on the back TCO layer 9, and a portion of the doped polysilicon layer 4-1 not covered by the front electrode 1 is removed using the front electrode 1 as a mask, to obtain the solar cell shown in fig. 12. In the preparation method, the front passivation contact structure requiring higher temperature is formed first, the process temperature of each subsequent layer is lower, and the preparation of the front passivation contact structure does not have adverse effect on each subsequent layer basically.

In the solar cell shown in fig. 12, the silicon substrate 6 may be N-type mono/polysilicon. The front electrode 1, the doped polysilicon layer 4-1 and the tunneling oxide layer 5-1 below form a multi-sub-end (majority carrier) local passivation contact structure. The front passivation layer 3 is overlapped with the front anti-reflection layer 2 to play a passivation role on the part except the passivation contact area so as to reduce the recombination of carriers, wherein the front anti-reflection layer 2 has the effect of reducing the escape reflection of light from the light facing surface. The back intrinsic amorphous silicon passivation layer 7 and the back doped layer 8 of the back surface of the silicon substrate 6 form a heterojunction structure, wherein the back intrinsic amorphous silicon passivation layer 7 gives consideration to passivation. The back TCO layer 9 makes contact with the back doped layer 8 and aids in the lateral transport of minority carriers, and the back electrode 10 leads out current in contact with the back TCO layer 9.

In the solar cell shown in fig. 12, sunlight irradiates the light-facing surface of the solar cell, most of the light irradiated to the front electrode 1 is reflected back to the atmosphere, and if the front electrode 1 has a regular triangle or trapezoid shape, most of the light is reflected to the area adjacent to the front electrode 1, and the light irradiated to the front anti-reflection layer 2 is refracted, and there is a possibility that a small part of the light is absorbed, and enters the N-type silicon substrate 6 through the front passivation layer 3. The light is excited in the N-type silicon substrate 6 to generate a large number of majority carriers (electrons) and minority carriers (holes), and the carriers are freely diffused in the N-type silicon substrate 6 after being generated. Wherein, part of electrons directly move to the tunneling oxide layer 5-1 and are collected by the front electrode 1 through the N-type doped polysilicon layer 4-1. Most of the holes are diffused to the vicinity of the heterojunction region or carriers generated in the vicinity of the junction region are rapidly moved toward the backlight surface by the built-in electric field generated by the heterojunction structure of the N-type silicon substrate 6, the back intrinsic amorphous silicon passivation layer 7 and the back doped layer 8. Holes are emitted to the back TCO layer 9 via the junction region and transported laterally therein and then collected out by the back electrode 10, and electrons are transported laterally within the silicon body to the adjacent passivation contact structure consisting of the tunnel oxide layer 5-1, the N-doped polysilicon layer 4-1 and out by the front electrode 1. In the working process of the solar cell, the current flows as follows: n-type silicon substrate 6→back electrode 10→external circuit→front electrode 1→n-type silicon substrate 6.

Example 2

Referring to fig. 2, a silicon substrate 6 is subjected to a texturing process. Referring to fig. 3, a front passivation layer 3 and a front anti-reflection layer 2 are formed on a light-facing surface of a silicon substrate 6. Referring to fig. 4, the front passivation layer 3 and the front anti-reflection layer 2 are patterned such that the light facing surface portion of the silicon substrate 6 is exposed. Referring to fig. 5, the patterned silicon substrate 6 is textured. Referring to fig. 9, a front intrinsic amorphous silicon passivation layer 5-2 and a front doped layer 4-2 are sequentially formed on the exposed silicon substrate and the front anti-reflection layer. A back intrinsic amorphous silicon passivation layer 7, a back doped layer 8, and a back TCO layer 9 are sequentially formed on the back surface of the silicon substrate 6. Referring to fig. 11, a front electrode 1 is formed on the front doped layer 4-2, and a back electrode 10 is formed on the back TCO layer 9, and the front doped layer 4-2 and the front intrinsic amorphous silicon passivation layer 5-2 are removed with the front electrode 1 as a mask, so that the solar cell shown in fig. 13 is obtained.

In the solar cell shown in fig. 13, the silicon substrate 6 may be N-type mono/poly silicon. The front electrode 1, the N-type front doped layer 4-2 below and the front intrinsic amorphous silicon passivation layer 5-2 form a multi-sub-terminal (majority carrier) local passivation contact structure. The front passivation layer 3 is overlapped with the front anti-reflection layer 2 to play a passivation role on the part except the passivation contact area so as to reduce the recombination of carriers, wherein the front anti-reflection layer 2 has the effect of reducing the escape reflection of light from the front surface. The back intrinsic amorphous silicon passivation layer 7 and the back doped layer 8 of the solar cell form a heterojunction structure, wherein the back intrinsic amorphous silicon passivation layer 7 gives consideration to passivation. The back TCO layer 9 makes contact with the back doped layer 8 and aids in the lateral transport of minority carriers, and the back electrode 10 leads out current in contact with the back TCO layer 9.

In the solar cell shown in fig. 13, sunlight irradiates the light-facing surface of the solar cell, most of the light irradiated to the front electrode 1 is reflected back to the atmosphere, and if the front electrode 1 has a regular triangle or trapezoid shape, most of the light irradiated to the front antireflection layer 2 is reflected to the area adjacent to the front electrode 1, and the light is refracted or a small part of the light is absorbed, and enters the N-type silicon substrate 6 through the front passivation layer 3. The light excites in the silicon body to generate a large number of majority carriers (electrons) and minority carriers (holes), and the carriers are freely diffused in the N-type silicon substrate 6 after generation. Wherein, part of electrons directly move to the front intrinsic amorphous silicon passivation layer 5-2 and are collected by the front electrode 1 through the N-type front doped layer 4-2. Most of the hole electrons diffuse to the vicinity of the junction region or carriers generated in the vicinity of the junction region are rapidly moved toward the back surface (front surface) by the built-in electric field generated by the heterojunction structure of the N-type silicon substrate 6, the back surface intrinsic amorphous silicon passivation layer 7 and the back surface doped layer 8. Holes are emitted through the junction region to the rear TCO layer 9 where they are transported laterally and are collected and transported away by the rear electrode 10, and electrons are transported laterally within the silicon body to the adjacent passivation contact structure consisting of the front intrinsic amorphous silicon passivation layer 5-2, the N-type front doped layer 4-2 and are transported away by the front electrode 1. In the working process of the solar cell, the current flows as follows: n-type silicon substrate 6→back electrode 10→external circuit→front electrode 1→n-type silicon substrate 6.

The solar cell electrical properties of example 1 and example 2 are compared with the TOPCon and HJT cell top record data, referring to table 1 below.

Table 1: solar cell electrical properties in examples 1 and 2, and TOPCon and HJT cell top record data comparison table

In Table 1, FZ is a float zone method or a zone melting method, and CZ is a Czochralski method. To avoid repetition, the descriptions of the steps in embodiment 1 and embodiment 2 are simpler, reference may be further made to the relevant descriptions in the related drawings, and the same or similar advantages can be achieved.

As can be seen from the comparison, compared with TOPCon and HJT batteries, the photoelectric conversion efficiency in embodiment 1 and embodiment 2 is significantly higher, the current density is significantly higher, and the fill factor is significantly higher, mainly because in embodiment 1 and embodiment 2, the local passivation contact structure is formed at the contact portion of the front electrode 1, and the area of the light-facing surface of the silicon substrate 6 except the projection of the front electrode 1 on the light-facing surface of the silicon substrate 6 is not covered with the local passivation contact structure, so that the parasitic absorption of light by the contact structure can be effectively passivated, and the short-circuit current and the photoelectric conversion efficiency of the solar battery are improved. The uncovered part of the front electrode 1 is not doped, and the silicon substrate 6 is covered by the front passivation layer 3 and the front anti-reflection layer 2, so that a good passivation anti-reflection effect is achieved, and the short-circuit current and the photoelectric conversion efficiency of the solar cell are further improved. Meanwhile, in the solar cell provided by the invention, the backlight surface of the silicon substrate 6 can also be of a heterojunction structure, so that better passivation and contact performance can be obtained.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred, and that the acts are not necessarily all required in accordance with the embodiments of the application.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. A method of manufacturing a solar cell, comprising:

forming a front electrode on the front passivation contact structure; the projection of the front electrode on the light-facing surface of the silicon substrate is positioned on the exposed light-facing surface of the silicon substrate;

In a direction in which the front side passivation anti-reflection layer and the silicon substrate are stacked, the front side passivation contact structure includes: one of the first structure, the second structure, and the third structure; the first structure is as follows: a tunneling oxide layer and a doped polysilicon layer which are sequentially stacked, wherein the tunneling oxide layer is closely adjacent to the silicon substrate; the second structure is as follows: a front intrinsic amorphous silicon passivation layer and a front doped layer stacked in sequence, the front intrinsic amorphous silicon passivation layer being immediately adjacent to the silicon substrate; the third structure is as follows: a front intrinsic amorphous silicon passivation layer, a front doped layer, a front TCO layer, which are laminated in sequence, the front intrinsic amorphous silicon passivation layer being immediately adjacent to the silicon substrate;

forming a front electrode on the front passivation contact structure, including:

In the front passivation contact structure, a front electrode layer is electroplated on the outermost layer farthest from the silicon substrate, in the electroplating process, the electroplating rate of the front electrode layer in the outermost layer, corresponding to the exposed light-facing surface of the silicon substrate, is greater than that of the front electrode layer in the rest of the outermost layer, and the thickness of the obtained front electrode layer in the part corresponding to the exposed light-facing surface of the silicon substrate is greater than that of the rest of the front electrode layer;

2. The method for manufacturing a solar cell according to claim 1, wherein forming a front passivation contact structure on the bare light-facing surface of the silicon substrate comprises:

3. The method for manufacturing a solar cell according to claim 2, wherein forming the front passivation contact structure on the bare light-facing surface of the silicon substrate and the remaining front passivation anti-reflection layer comprises:

4. The method for manufacturing a solar cell according to claim 2, wherein forming the front passivation contact structure on the bare light-facing surface of the silicon substrate and the remaining front passivation anti-reflection layer comprises:

5. The method for manufacturing a solar cell according to claim 2, wherein forming the front passivation contact structure on the bare light-facing surface of the silicon substrate and the remaining front passivation anti-reflection layer comprises:

6. The method of manufacturing a solar cell according to any one of claims 3 to 5, wherein after the front side passivation contact structure is formed, the method further comprises: sequentially forming a back intrinsic amorphous silicon passivation layer, a back doped layer and a back TCO layer on the back light surface of the silicon substrate; the back doped layer is: one of an amorphous silicon doped layer, a microcrystalline silicon doped layer and a nanocrystalline silicon doped layer;

and forming a back electrode on the back TCO layer.

7. The method of any one of claims 1 to 5, wherein the thickness of the outermost layer of the front passivation contact structure furthest from the silicon substrate is 10 to 300nm.

8. The method for manufacturing a solar cell according to claim 5, wherein the removing the portions of the front intrinsic amorphous silicon passivation layer, the front doped layer, and the front TCO layer not covered by the front electrode using the front electrode as a mask comprises:

9. The method of claim 3, wherein the silicon substrate is an N-type silicon substrate, and the forming a doped polysilicon layer on the tunnel oxide layer and the remaining front passivation anti-reflection layer comprises:

10. The method of claim 3, wherein the silicon substrate is an N-type silicon substrate, and the forming a doped polysilicon layer on the tunnel oxide layer and the remaining front passivation anti-reflection layer comprises:

11. The method of manufacturing a solar cell according to claim 9 or 10, wherein after forming the front-side phosphosilicate glass layer, the method further comprises:

12. The method of any one of claims 1 to 5, wherein the front side passivation anti-reflection layer comprises a front side passivation layer and a front side anti-reflection layer, and the front side passivation layer is made of a material selected from the group consisting of: at least one of intrinsic amorphous silicon, silicon oxide, phosphosilicate glass, aluminum oxide and phosphosilicate glass;

13. The method of claim 12, wherein the front side anti-reflection layer has a single layer or a stacked layer structure.

14. The method of claim 12, wherein the refractive index of the front side anti-reflection layer decreases in a direction away from the silicon substrate.

15. The method of claim 12, wherein the front side anti-reflection layer comprises a silicon nitride film and a magnesium fluoride film, wherein the silicon nitride film is closer to the silicon substrate.

16. A method of fabricating a solar cell according to claim 3, wherein the doped polysilicon layer contains elemental carbon and/or elemental oxygen.

17. A solar cell prepared by the method of any one of claims 1 to 16.

18. A photovoltaic module comprising a string of solar cells of claim 17 connected in series.