CN112133763A - P-type crystalline silicon solar cell and production method - Google Patents

P-type crystalline silicon solar cell and production method Download PDF

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CN112133763A
CN112133763A CN201910551147.2A CN201910551147A CN112133763A CN 112133763 A CN112133763 A CN 112133763A CN 201910551147 A CN201910551147 A CN 201910551147A CN 112133763 A CN112133763 A CN 112133763A
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silicon substrate
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李华
刘继宇
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Taizhou Longi Solar Technology Co Ltd
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Taizhou Lerri Solar Technology Co Ltd
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Abstract

The invention provides a p-type crystalline silicon solar cell and a production method thereof, relating to the technical field of solar photovoltaic. The p-type crystalline silicon solar cell includes: a p-type crystalline silicon substrate; the local P + + type doped region is formed on the front surface of the P-type crystal silicon substrate; the front antireflection layer is deposited on the front side of the p-type crystal silicon substrate; a front metal electrode penetrating through the front anti-reflection layer and contacting the local p + + type doped region; passivating the tunneling layer; the P-type crystal silicon substrate is formed on the back surface of the P-type crystal silicon substrate; the n-type doped silicon film layer is formed on the back surface of the passivation tunneling layer; the back passivation layer is deposited on the back of the n-type doped silicon film layer; and a back metal electrode penetrating the back passivation layer and contacting the n-type doped silicon film layer. The p-type crystalline silicon solar cell reduces optical loss, and has the advantages of small contact area recombination, high photoelectric conversion efficiency, large open-circuit voltage and low cost.

Description

P-type crystalline silicon solar cell and production method
Technical Field
The invention relates to the technical field of solar photovoltaics, in particular to a p-type crystalline silicon solar cell, a production method of the p-type crystalline silicon solar cell, production equipment of the p-type crystalline silicon solar cell and a computer readable storage medium.
Background
The heterojunction solar cell has the advantages of low production process temperature, high photoelectric conversion efficiency and the like, so the application prospect is wide.
At present, in a heterojunction solar cell, effective incident light entering a silicon substrate is generally reduced due to the arrangement of a heterojunction, so that a large optical loss is caused, and therefore a transparent conductive film, a low-temperature conductive silver paste and the like need to be matched to maintain a high photoelectric conversion efficiency.
Due to the fact that the cost of the transparent conductive film and the low-temperature conductive silver paste is high, the cost of the heterojunction solar cell is high.
Disclosure of Invention
The invention provides a p-type crystalline silicon solar cell, a p-type crystalline silicon solar cell production method, p-type crystalline silicon solar cell production equipment and a computer-readable storage medium, and aims to solve the problem of high cost of a heterojunction solar cell.
According to a first aspect of the present invention, there is provided a p-type crystalline silicon solar cell comprising: a p-type crystalline silicon substrate;
the local P + + type doped region is formed on the front surface of the P-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate;
the front antireflection layer is deposited on the front side of the p-type crystal silicon substrate;
a front metal electrode penetrating through the front anti-reflection layer and contacting the local p + + type doped region;
passivating the tunneling layer; the P-type crystal silicon substrate is formed on the back surface of the P-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon;
the n-type doped silicon film layer is formed on the back surface of the passivation tunneling layer;
the back passivation layer is deposited on the back of the n-type doped silicon film layer;
and a back metal electrode penetrating the back passivation layer and contacting the n-type doped silicon film layer; the back metal electrode is a grid electrode.
Optionally, the width of the local p + + type doped region is greater than or equal to the width of the front metal electrode.
Optionally, the p-type crystalline silicon solar cell further includes: the p + -type doping layer is doped in a region which is formed between the front antireflection layer and the p-type crystalline silicon substrate and is outside the local p + + -type doping region; and the doping concentration of the p + type doping layer is between the doping concentration of the local p + + type doping region and the doping concentration of the p-type crystal silicon substrate.
Optionally, the material of the n-type doped silicon film layer includes: at least one of microcrystalline silicon and polycrystalline silicon, and doped with a group V element.
Optionally, the group iii element comprises: boron element; the group V elements include: phosphorus element.
Optionally, the thickness of the passivation tunneling layer is 0.5-3 nm.
Optionally, the doping concentration of the p-type crystal silicon substrate is as follows: 1.3X 1015～1×1017(ii) a The doping concentration of the local p + + type doping region is as follows: 1019～1021cm-3The doping concentration of the P + doping layer is as follows: 1018～1020cm-3。
Optionally, the p-type crystalline silicon substrate includes: a p-type monocrystalline silicon substrate or a p-type polycrystalline silicon substrate.
Optionally, the thickness of the p-type crystal silicon substrate is 50-300 μm.
Optionally, the thickness of the n-type doped silicon film layer is 10nm to 500 nm.
Optionally, the materials of the front anti-reflection layer and the back passivation layer are respectively and independently selected from the group consisting of: at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon carbide, silicon oxycarbide, and amorphous silicon.
Optionally, the thickness of the front anti-reflection layer is 40-100 nm; the thickness of the back passivation layer is 40-200 nm.
Optionally, the material of the back passivation layer includes: at least one of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, aluminum oxynitride, silicon carbide, and amorphous silicon.
Optionally, the front metal electrode includes: any one of an Al electrode, an Al/Ag electrode, a Ni/Cu electrode, a Co/Cu electrode, a Ni/Cu/Sn electrode, a Co/Cu/Ag electrode and a Ni/Cu/Ag electrode;
optionally, the back metal electrode includes any one of an Ag electrode, a Ni/Cu electrode, a Co/Ag electrode, a Co/Cu/Sn electrode, a Co/Cu/Ag electrode, a Ni/Cu/Sn electrode, and a Ni/Cu/Ag electrode.
According to a second aspect of the present invention, there is provided a p-type crystalline silicon solar cell production method for producing a p-type crystalline silicon solar cell of any one of the preceding items; the method comprises the following steps:
forming a local p + + type doped region on the front surface of the p-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate;
depositing a front anti-reflection layer on the front side of the p-type crystal silicon substrate;
forming at least one first film opening region in a preset region of the front anti-reflection layer to expose the local p + + type doped region; forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region;
forming a passivation tunneling layer on the back surface of the p-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon;
forming an n-type doped silicon film layer on the back of the passivation tunneling layer;
depositing and forming a back passivation layer on the back of the n-type doped silicon film layer;
irradiating laser on a preset area of the back passivation layer to form at least one second film opening area and expose the n-type doped silicon film layer; and forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region.
Optionally, before depositing and forming a front side anti-reflection layer on the front side of the p-type crystalline silicon substrate, the method further includes:
doping to form a p + type doping layer in a region between the front antireflection layer and the p-type crystal silicon substrate and outside the local p + + type doping region;
the doping concentration of the p + type doping layer is between the doping concentration of the local p + + type doping region and the doping concentration of the p-type crystalline silicon substrate;
depositing a front antireflection layer on the front side of the p-type crystal silicon substrate, wherein the front antireflection layer comprises:
and depositing to form the front antireflection layer on the front surfaces of the local p + + type doped region and the p + type doped layer.
Optionally, before forming the passivation tunneling layer on the back side of the p-type crystalline silicon substrate, the method further includes:
polishing the back surface of the p-type crystal silicon substrate;
the forming of the passivation tunneling layer on the back side of the p-type crystal silicon substrate comprises the following steps:
and depositing and forming the passivation tunneling layer on the back surface of the p-type crystal silicon substrate after the polishing treatment.
In the embodiment of the invention, the method for producing the p-type crystalline silicon solar cell can achieve the same or similar beneficial effects as the p-type crystalline silicon solar cell, and the details are not repeated here in order to avoid repetition.
According to a third aspect of the present invention, there is also provided a p-type crystalline silicon solar cell production apparatus comprising: an interface, a bus, a memory and a processor, wherein the interface, the memory and the processor are connected through the bus, the memory is used for storing an executable program, and the processor is configured to run the executable program to realize the steps of the p-type crystalline silicon solar cell production method according to any one of the preceding claims.
According to a fourth aspect of the present invention, there is also provided a computer readable storage medium having stored thereon an executable program which is executed by a processor to implement the steps of the p-type crystalline silicon solar cell production method as described in any one of the preceding.
In an embodiment of the present invention, a p-type crystalline silicon solar cell includes: a p-type crystalline silicon substrate; the local P + + type doped region is formed on the front surface of the P-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate; the front antireflection layer is deposited on the front side of the p-type crystal silicon substrate; a front metal electrode penetrating through the front anti-reflection layer and contacting the local p + + type doped region; passivating the tunneling layer; the P-type crystal silicon substrate is formed on the back surface of the P-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon; the n-type doped silicon film layer is formed on the back surface of the passivation tunneling layer; the back passivation layer is deposited on the back of the n-type doped silicon film layer; and a back metal electrode penetrating the back passivation layer and contacting the n-type doped silicon film layer; the back metal electrode is a grid electrode. In the embodiment of the invention, the heterojunction is formed on the back surface of the p-type crystalline silicon substrate by the n-type doped silicon film layer and the p-type crystalline silicon substrate, so that a back emitter is formed, the back surface of the p-type crystalline silicon substrate is smoother, the performance of the formed heterojunction is better, and the open-circuit voltage can be improved to a certain extent; and compared with the heterojunction positioned on the front side of the p-type crystalline silicon substrate, the heterojunction positioned on the back side of the p-type crystalline silicon substrate does not reduce effective incident light entering the p-type crystalline silicon substrate, and has less optical loss. The passivation tunneling layer is formed on the back surface of the P-type crystal silicon substrate, the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements, and the tunneling matrix comprises: the passivation tunneling layer can passivate a heterojunction and a contact region of a battery emitter, so that surface recombination of the contact region is reduced, and open-circuit voltage and conversion efficiency of the battery are further improved; and the III group and/or V group elements in the passivation tunneling layer form quantum tunneling points, so that transition of electrons and current transmission are facilitated, and short-circuit current and open-circuit voltage are improved. The back metal electrode is a grid line electrode and is not a metal electrode on the whole surface, so that the cost is reduced; meanwhile, in the p-type crystalline silicon cell with the structure, the front metal electrode is not directly contacted with the p-type crystalline silicon substrate, and the front metal electrode is contacted with the local p + + type doping region with higher doping concentration to form good ohmic contact, so that the contact resistance can be reduced to a great extent; meanwhile, the back metal electrode is not directly contacted with the p-type crystal silicon substrate, and the back metal electrode is contacted with the n-type doped silicon film layer to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode and the back metal electrode with the p-type crystal silicon substrate is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be further improved; meanwhile, the p-type crystalline silicon solar cell with the structure has the advantages that the processing process is compatible with the existing processing technology, and the manufacturing is simple and convenient.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows a schematic structural view of a first p-type crystalline silicon solar cell in an embodiment of the present invention;
fig. 2 shows a schematic structural view of a second p-type crystalline silicon solar cell in an embodiment of the present invention;
fig. 3 shows a flow chart of steps of a method of producing a p-type crystalline silicon solar cell in an embodiment of the invention;
fig. 4 shows a flow chart of steps of yet another method of producing a p-type crystalline silicon solar cell in an embodiment of the invention;
fig. 5 shows a schematic structural diagram of a p-type crystalline silicon solar cell production apparatus according to a fifth embodiment of the present invention.
Description of the figure numbering:
the chip comprises a 1-p type crystal silicon substrate, a 2-local p + + type doped region, a 3-front antireflection layer, a 4-front metal electrode, a 5-n type doped silicon film layer, a 6-back passivation layer, a 7-back metal electrode, an 8-p + type doped layer, a 9-passivation tunneling layer, a 71-interface, a 72-processor, a 73-memory and a 74-bus.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows a schematic structural view of a first p-type crystalline silicon solar cell in an embodiment of the present invention.
In the embodiment of the invention, the p-type crystal silicon substrate 1 can be mainly used for absorbing photons to generate photon-generated carriers.
Referring to fig. 1, the p-type crystalline silicon solar cell may include: the structure comprises a p-type crystal silicon substrate 1, a local p + + type doped region 2, a front antireflection layer 3, a front metal electrode 4, a passivation tunneling layer 9, an n-type doped silicon film layer 5, a back passivation layer 6 and a back metal electrode 7.
In the embodiment of the present invention, the local p + + type doped region 2 and the p-type crystalline silicon substrate 1 are doped with the same type, and the doping type may be a group III element, for example, a boron element. And the doping concentration of the local p + + type doping region 2 is greater than that of the p-type crystal silicon substrate 1.
In the embodiment of the present invention, the region of the front surface of the p-type crystalline silicon substrate 1 corresponding to the front surface metal electrode 4 is provided with the local p + + type doped region 2. The front surface of the p-type crystalline silicon substrate 1, the region corresponding to the front surface metal electrode 4, may be the front surface of the p-type crystalline silicon substrate 1, and the region below the front surface metal electrode 4 and having a width difference with the front surface metal electrode 4 smaller than or equal to a preset difference.
In the embodiment of the invention, the preset difference value can be set according to actual needs. In the embodiment of the present invention, this is not particularly limited.
In the embodiment of the present invention, optionally, the width of the local p + + type doped region 2 may be greater than or equal to the width of the front metal electrode 4. Furthermore, the front metal electrode can be completely contacted with the local p + + type doped region 2 to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode 4 with the p-type crystal silicon substrate 1 is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be improved to a great extent.
For example, the region of the front surface of the p-type crystalline silicon substrate 1 corresponding to the front surface metal electrode 4 may be a region of the front surface of the p-type crystalline silicon substrate 1, which is directly below the front surface metal electrode 4 and has the same width as the front surface metal electrode 4. Furthermore, the width of the local p + + type doped region 2 is exactly the same as the width of the front metal electrode 4, and the front metal electrode may just completely contact the local p + + type doped region 2.
In the present embodiment, the front metal electrode 4 is generally used to collect holes in photogenerated carriers. Alternatively, the front metal electrode 4 may include: any one of Al electrode, Al/Ag electrode, Ni/Cu electrode, Co/Cu electrode, Ni/Cu/Sn electrode, Co/Cu/Ag electrode and Ni/Cu/Ag electrode. For example, the front metal electrode 4 may be an Al electrode formed by screen printing.
In the embodiment of the invention, the front metal electrode has more selectivity, and the front metal electrode with lower cost can be selected, so that the cost of the heterojunction solar cell is reduced. Meanwhile, the metal cobalt Co is used as the material of the front metal electrode, so that the blocking effect on copper is favorably improved, the copper is prevented from entering the p-type crystalline silicon solar cell as impurities, the copper is easy to diffuse in the p-type crystalline silicon solar cell and can cause charge recombination, current carriers are reduced, and the open-circuit voltage is reduced.
In the embodiment of the present invention, the p-type crystalline silicon substrate 1 may optionally include: a p-type monocrystalline silicon substrate or a p-type polycrystalline silicon substrate. Specifically, the p-type crystalline silicon substrate 1 may be a p-type monocrystalline silicon substrate, or the p-type crystalline silicon substrate 1 may be a p-type polycrystalline silicon substrate, or the like. In the embodiment of the present invention, this is not particularly limited.
In the embodiment of the invention, the thickness of the p-type crystal silicon substrate 1 can be 50-300 μm. The p-type crystalline silicon substrate 1 with the thickness can absorb more photons and generate more photon-generated carriers. For example, the thickness of the p-type crystalline silicon substrate 1 may be 180 μm.
In the embodiment of the invention, a front side antireflection layer 3 is deposited on the front side of a p-type crystal silicon substrate 1. The front anti-reflection layer 3 can reduce the reflection of front incident light on the surface of a p-type crystalline silicon substrate and the like to a great extent, and can form good surface passivation on the local p + + type doped region 2 and the like.
In the embodiment of the present invention, optionally, the material of the front antireflection layer 3 may include: at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon carbide, silicon oxycarbide, and amorphous silicon.
In the embodiment of the invention, optionally, the thickness of the front antireflection layer 3 may be 40 to 100 nm. The front anti-reflection layer 3 with the thickness range can further reduce the reflection of front incident light on the surfaces of a p-type crystalline silicon substrate and the like, and can form better surface passivation on the local p + + type doped region 2 and the like.
For example, the front side anti-reflection layer 3 may be a composite film layer formed of aluminum oxide and silicon nitride, the thickness of the aluminum oxide may be 15nm, the thickness of the silicon nitride may be 60nm, and the thickness of the front side anti-reflection layer 3 may be 75 nm.
In the embodiment of the present invention, the front metal electrode 4 penetrates through the front anti-reflective layer 3 and contacts the local p + + type doped region 2. The front metal electrode 4 is not in direct contact with the p-type crystalline silicon substrate 1, the front metal electrode 4 is in contact with the local p + + type doping area 2 with high doping concentration, good ohmic contact is formed, and contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode 4 with the p-type crystal silicon substrate 1 is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be improved to a great extent.
In the embodiment of the invention, the passivation tunneling layer 9 is formed on the back surface of the p-type crystal silicon substrate 1, so that the heterojunction and the contact region of the battery emitter can be passivated, the surface recombination of the contact region is reduced, and the open-circuit voltage and the conversion efficiency of the battery are further improved.
In an embodiment of the present invention, the passivating tunneling layer 9 is a tunneling matrix doped with group iii and/or group v elements. The tunneling substrate may include: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon. Further, the tunneling substrate has a high selectivity.
In an embodiment of the present invention, the passive tunneling layer is a tunneling matrix doped with group iii and/or group v elements. Specifically, the group iii and/or group v elements in the passivation tunneling layer 9 form quantum tunneling points, which are beneficial to transition of electrons and current transmission, and improve short-circuit current and open-circuit voltage. In an embodiment of the present invention, optionally, the group iii element may include a boron element, and the group v element may include a phosphorus element.
In the embodiment of the present invention, optionally, the concentration of the doped group iii element in the passivation tunneling layer 9 is greater than 1013cm-3, the concentration of the group V element is greater than that of the group III element. E.g. if the passive tunneling layer 9 is doped with group IIIElements and group V elements, e.g. boron and phosphorus, the concentration of boron may be 2X 1013cm-3, the concentration of phosphorus element is greater than that of boron element, and the concentration of phosphorus element can be 1015cm-3. If only group III elements are doped in the passivated tunneling layer 9, the concentration of group III elements is greater than 1013cm-3, e.g. the concentration of boron may be 2X 1013cm-3. If only the passive tunneling layer 9 is doped with the group V element, the concentration of the group V element is greater than 1014cm-3, e.g. the concentration of phosphorus element may be 1015cm-3. Under the doping concentration, more quantum tunneling points are formed, transition of electrons and current transmission are facilitated, and short-circuit current and open-circuit voltage are further improved.
In the embodiment of the present invention, optionally, the thickness of the passivation tunneling layer 9 may be 0.5 to 3 nm. The passivation tunneling layer 9 with the thickness range has a good passivation effect, and is more favorable for reducing the surface recombination of the contact region, so that the open-circuit voltage and the conversion efficiency of the battery are further improved. For example, the passivation tunneling layer 9 may be a 1.5nm silicon oxide layer.
In the embodiment of the present invention, the n-type doped silicon film layer 5 is formed on the back surface of the passivation tunneling layer 9. And then the n-type doped silicon film layer 5 and the p-type crystalline silicon substrate 1 form a heterojunction which is positioned on the back surface of the p-type crystalline silicon substrate 1 to form a back emitter. The back surface of the p-type crystal silicon substrate 1 is not required to be subjected to texturing generally, so that the back surface of the p-type crystal silicon substrate 1 is more flat and smooth, the performance of a formed heterojunction is better, and the open-circuit voltage can be improved to a certain extent; and the heterojunction on the back of the p-type crystalline silicon substrate 1 does not reduce the effective incident light entering the p-type crystalline silicon substrate 1 compared with the heterojunction on the front of the p-type crystalline silicon substrate, and has less optical loss.
In an embodiment of the present invention, optionally, the material of the n-type doped silicon film layer 5 may include: at least one of microcrystalline silicon and polycrystalline silicon, and doped with a group V element. The material of the n-type doped silicon film layer 5 may be microcrystalline silicon, the material of the n-type doped silicon film layer 5 may be polycrystalline silicon, or the material of the n-type doped silicon film layer 5 may be a combination of microcrystalline silicon and polycrystalline silicon. Compared with the amorphous silicon with strong light absorption, the n-type doped silicon film layer 5 is made of the following materials: at least one of microcrystalline silicon and polycrystalline silicon is weak in light absorption capacity, so that effective incident light entering the p-type crystalline silicon substrate 1 cannot be reduced, optical loss is low, on one hand, photoelectric conversion efficiency is high, open-circuit voltage is large, on the other hand, the p-type crystalline silicon cell with the structure is low in optical loss, and further a transparent conductive film, low-temperature conductive silver paste and the like are not needed, so that the cost of the heterojunction solar cell is reduced to a great extent.
In the embodiment of the present invention, optionally, the n-type doped silicon film layer 5 is doped with a group V element. For example, the n-type doped silicon film layer 5 may be doped with phosphorus. In the embodiment of the present invention, this is not particularly limited.
In the embodiment of the present invention, the thickness of the n-type doped silicon film layer 5 may be optionally 10nm to 500 nm. For example, the thickness of the n-type doped silicon film layer 5 may be 150 nm. The n-type doped silicon film layer 5 with the thickness range is beneficial to increasing effective incident light entering the p-type crystalline silicon substrate 1, and optical loss is low.
In the embodiment of the present invention, a back passivation layer 6 is deposited on the back of the n-type doped silicon film layer 5. The back passivation layer 6 can largely reduce reflection of back incident light on the surface of a p-type crystalline silicon substrate or the like, and at the same time, can form good surface passivation with a heterojunction, a back emitter, or the like.
In the embodiment of the present invention, the material of the back passivation layer 6 may include: at least one of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, aluminum oxynitride, silicon carbide, and amorphous silicon.
In the embodiment of the invention, the thickness of the back passivation layer 6 may be 40 to 200 nm. The back passivation layer 6 having the above thickness range can further reduce reflection of back incident light on the surface of the p-type crystalline silicon substrate or the like, and can form better surface passivation for a heterojunction or a back emitter or the like. For example, the surface passivation layer 6 may be silicon nitride and may have a thickness of 70 nm.
In the embodiment of the present invention, the back metal electrode 7 penetrates the back passivation layer 6 and contacts the n-type doped silicon film layer 5. The back metal electrode 7 is not in direct contact with the p-type crystalline silicon substrate 1, the back metal electrode 7 is in contact with the n-type doped silicon film layer 5, good ohmic contact is formed, and contact resistance can be further reduced to a great extent; the contact area recombination caused by the fact that the back metal electrode 7 directly contacts the p-type crystalline silicon substrate 1 is avoided, and the open-circuit voltage and the conversion efficiency of the cell can be further improved.
In the present embodiment, the back metal electrode 7 is generally used to collect electrons from photogenerated carriers. Optionally, the back metal electrode 7 may include any one of an Ag electrode, a Ni/Cu electrode, a Co/Ag electrode, a Co/Cu/Sn electrode, a Co/Cu/Ag electrode, a Ni/Cu/Sn electrode, and a Ni/Cu/Ag electrode. For example, the back metal electrode 7 may be an Ag electrode formed by screen printing.
In the embodiment of the invention, the selectivity of the back metal electrode is high, and the back metal electrode with lower cost can be selected, so that the cost of the heterojunction solar cell is reduced. Meanwhile, the metal cobalt Co is used as the material of the back metal electrode, so that the blocking effect on copper is favorably improved, the copper is prevented from entering the p-type crystalline silicon solar cell as impurities, the copper is easy to diffuse in the p-type crystalline silicon solar cell and can cause charge recombination, current carriers are reduced, and the open-circuit voltage is reduced.
In the embodiment of the invention, the p-type crystalline silicon solar cell is manufactured by the existing processing technologies such as doping, deposition and the like, is directly compatible with the existing processing technologies, does not need to adjust the existing processing technologies, and is simple and convenient in manufacturing process.
In an embodiment of the present invention, a p-type crystalline silicon solar cell includes: a p-type crystalline silicon substrate; the local P + + type doped region is formed on the front surface of the P-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate; the front antireflection layer is deposited on the front side of the p-type crystal silicon substrate; a front metal electrode penetrating through the front anti-reflection layer and contacting the local p + + type doped region; passivating the tunneling layer; the P-type crystal silicon substrate is formed on the back surface of the P-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon; the n-type doped silicon film layer is formed on the back surface of the passivation tunneling layer; the back passivation layer is deposited on the back of the n-type doped silicon film layer; and a back metal electrode penetrating the back passivation layer and contacting the n-type doped silicon film layer; the back metal electrode is a grid electrode. In the embodiment of the invention, the heterojunction is formed on the back surface of the p-type crystalline silicon substrate by the n-type doped silicon film layer and the p-type crystalline silicon substrate, so that a back emitter is formed, the back surface of the p-type crystalline silicon substrate is smoother, the performance of the formed heterojunction is better, and the open-circuit voltage can be improved to a certain extent; and compared with the heterojunction positioned on the front side of the p-type crystalline silicon substrate, the heterojunction positioned on the back side of the p-type crystalline silicon substrate does not reduce effective incident light entering the p-type crystalline silicon substrate, and has less optical loss. The passivation tunneling layer is formed on the back surface of the P-type crystal silicon substrate, the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements, and the tunneling matrix comprises: the passivation tunneling layer can passivate a heterojunction and a contact region of a battery emitter, so that surface recombination of the contact region is reduced, and open-circuit voltage and conversion efficiency of the battery are further improved; and the III group and/or V group elements in the passivation tunneling layer form quantum tunneling points, so that transition of electrons and current transmission are facilitated, and short-circuit current and open-circuit voltage are improved. The back metal electrode is a grid line electrode and is not a metal electrode on the whole surface, so that the cost is reduced; meanwhile, in the p-type crystalline silicon cell with the structure, the front metal electrode is not directly contacted with the p-type crystalline silicon substrate, and the front metal electrode is contacted with the local p + + type doping region with higher doping concentration to form good ohmic contact, so that the contact resistance can be reduced to a great extent; meanwhile, the back metal electrode is not directly contacted with the p-type crystal silicon substrate, and the back metal electrode is contacted with the n-type doped silicon film layer to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode and the back metal electrode with the p-type crystal silicon substrate is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be further improved; meanwhile, the p-type crystalline silicon solar cell with the structure has the advantages that the processing process is compatible with the existing processing technology, and the manufacturing is simple and convenient.
Referring to fig. 2, fig. 2 shows a schematic structural view of a second p-type crystalline silicon solar cell in an embodiment of the present invention.
Referring to fig. 2, the p-type crystalline silicon solar cell may further include, in addition to fig. 1: a p + -doped layer 8. And the p + type doping layer 8 is doped in a region which is formed between the front antireflection layer 3 and the p-type crystalline silicon substrate 1 and is outside the local p + + type doping region 2. The local p + + type doped region 2 and the p + type doped layer 8 are of the same doping type, and the doping concentration of the p + type doped layer 8 is between the doping concentration of the local p + + type doped region 2 and the doping concentration of the p-type crystal silicon substrate 1.
Specifically, a p + type doping layer 8 is doped in a region between the front anti-reflection layer 3 and the p-type crystalline silicon substrate 1 and outside the local p + + type doping region 2. That is, a p + -type doped layer 8 is doped around the local p + + -type doped region 2 between the front anti-reflection layer 3 and the p-type crystalline silicon substrate 1. The local p + + type doped region 2 has the same doping type as the p + type doped layer 8 and the p-type crystalline silicon substrate 1, and the doping types can be group III elements, such as boron. The doping concentration of the p + type doping layer 8 is between the doping concentration of the local p + + type doping region 2 and the doping concentration of the p type crystal silicon substrate 1, and then the local p + + type doping region 2 and the p + type doping layer 8 form a p + + p + type high-low junction, so that the contact region on the front side of the battery can be passivated, the surface recombination of the contact region is reduced, meanwhile, good ohmic contact can be formed with the front side metal electrode 4, and the open-circuit voltage and the conversion efficiency of the battery are further improved.
In the implementation of the present invention, referring to fig. 2, the width of the local p + + type doped region 2 is greater than the width of the front metal electrode 4. Furthermore, the front metal electrode 4 can be completely contacted with the local p + + type doped region 2 to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode 4 with the p-type crystal silicon substrate 1 is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be improved to a great extent.
In the implementation of the invention, the front metal electrode 4 may not contact with the p + -type doped layer 8, and the front metal electrode 4 may only contact with the local p + + -type doped region 2 with a higher doping concentration, so as to form a good ohmic contact and reduce the contact resistance to a greater extent.
In the implementation of the present invention, the doping concentration of the p-type crystalline silicon substrate 1 may be, optionally: 1.3X 1015～1×1017(ii) a The doping concentration of the local p + + type doped region 2 may be: 1019～1021cm-3The doping concentration of the P + doping layer 8 is: 1018～1020cm-3. In the doping concentration range, good ohmic contact is further formed, contact resistance is reduced to a greater extent, surface recombination of a contact region is reduced, and open-circuit voltage and conversion efficiency of the battery are further improved.
For example, the doping concentration of the p-type crystalline silicon substrate 1 is: 1.3X 1015～1×1017The resistivity corresponding to the p-type crystal silicon substrate 1 can be 0.3-10 omega cm, and the open-circuit voltage and the conversion efficiency of the cell can be further improved.
In the embodiment of the present invention, optionally, the doping concentration of the P + doping layer 8 may be less than 1018Alternatively, the doping concentration of the P + doped layer 8 may be less than 1017. In the embodiment of the present invention, this is not particularly limited. For example, the doping concentration of the P + doping layer 8 may be 8 × 1016。
Referring to fig. 3, fig. 3 shows a flow chart of steps of a method for producing a p-type crystalline silicon solar cell in an embodiment of the present invention. The method can be applied to the production of any one of the p-type crystalline silicon solar cells in fig. 1 or fig. 2 described above. The method specifically comprises the following steps:
step 101, forming a local p + + type doped region on the front surface of a p-type crystal silicon substrate; and the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate.
In an embodiment of the present invention, referring to any one of fig. 1 to 2, a local p + + type doped region 2 may be formed on a front surface of a p-type crystalline silicon substrate 1, where the local p + + type doped region 2 is doped with the same type as the p-type crystalline silicon substrate 1, and may be all group iii elements, and a doping concentration of the local p + + type doped region 2 is greater than a doping concentration of the p-type crystalline silicon substrate 1.
Specifically, the local p + + type doped region 2 may be formed on the front surface of the p-type crystalline silicon substrate 1 by printing, sintering, or low temperature deposition, which is not particularly limited in the embodiment of the present invention.
And 102, depositing a front side antireflection layer on the front side of the p-type crystal silicon substrate.
In the embodiment of the invention, the front side antireflection layer 3 can be deposited on the front side of the p-type crystal silicon substrate 1.
Specifically, the front side anti-reflection layer 3 may be deposited on the front side of the p-type crystalline silicon substrate 1 and the front side of the local p + + type doped region 2 by a printing sintering or low temperature deposition, which is not particularly limited in the embodiment of the present invention.
Step 103, forming at least one first open film region in a preset region of the front anti-reflection layer to expose the local p + + type doped region.
In the embodiment of the present invention, at least one first open film region is formed in a predetermined region of the front side anti-reflection layer 3 to expose the local p + + type doped region 2. The predetermined area may be: and a region opposite to the local p + + type doped region 2 on the front antireflection layer 3.
And 104, forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region.
In the embodiment of the present invention, a front metal electrode 4 is formed on the front surface of the local p + + type doped region 2 in the first open film region.
Specifically, the front metal electrode 4 connected to the localized p + + type doped region 2 may be formed by printing a sintered electrode paste through the front anti-reflective layer 3. Or, forming a front metal electrode 4 on the front surface of the local p + + type doped region 2 in the first open film region by a combination of low-temperature deposition and high-temperature deposition. Because silver is not used in low-temperature deposition and high-temperature deposition, and the resistivity is low, the formed p-type crystalline silicon solar cell is low in cost and good in conducting effect. In the embodiment of the present invention, this is not particularly limited.
Step 105, forming a passivation tunneling layer on the back surface of the p-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; wherein the tunneling matrix comprises: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon.
In the embodiment of the invention, a passivation tunneling layer 9 is deposited on the back side of the p-type crystalline silicon substrate 1. Specifically, a passivation tunneling layer 9 may be deposited on the back side of the p-type crystalline silicon substrate 1 by using a chemical oxidation or thermal oxidation route. In the embodiment of the present invention, this is not particularly limited.
In the embodiment of the invention, the passivation tunneling layer 9 is formed on the back surface of the p-type crystal silicon substrate 1, and the passivation tunneling layer 9 can passivate a heterojunction and a contact region of a battery emitter, so that the surface recombination of the contact region is reduced, and the open-circuit voltage and the conversion efficiency of the battery are further improved.
In an embodiment of the present invention, the passivating tunneling layer 9 is a tunneling matrix doped with group iii and/or group v elements. The tunneling substrate may include: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon. Further, the tunneling substrate has a high selectivity.
In an embodiment of the present invention, the passive tunneling layer is a tunneling matrix doped with group iii and/or group v elements. Specifically, the group iii and/or group v elements in the passivation tunneling layer 9 form quantum tunneling points, which are beneficial to transition of electrons and current transmission, and improve short-circuit current and open-circuit voltage.
And 106, forming an n-type doped silicon film layer on the back of the passivation tunneling layer.
In the embodiment of the present invention, the n-type doped silicon film layer 5 may be formed on the back surface of the passivation tunneling layer 9.
Specifically, the n-type doped silicon film layer 5 may be formed on the back surface of the passivation tunneling layer 9 by ion implantation or diffusion formation, which is not specifically limited in the embodiment of the present invention.
And 107, depositing a back passivation layer on the back of the n-type doped silicon film layer.
In the embodiment of the present invention, the back passivation layer 6 may be deposited on the back surface of the n-type doped silicon film layer 5, and the specific implementation manner is not particularly limited.
And 108, irradiating laser on a preset area of the back passivation layer to form at least one second film opening area, and exposing the n-type doped silicon film layer.
In the embodiment of the present invention, laser may be irradiated on a predetermined region of the back passivation layer 7 to form at least one second open film region, so as to expose the n-type doped silicon film layer 5. The predetermined region may be a corresponding region of the back passivation layer 7 where the back metal electrode 7 is required to be disposed. In the embodiment of the present invention, this is not particularly limited.
And 109, forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region.
In the embodiment of the present invention, a back metal electrode 7 may be formed on the back surface of the n-type doped silicon film layer 5 in the second opening region.
Specifically, a back metal electrode 7 connected to the back surface of the n-type doped silicon film layer 5 is formed by depositing a metal electrode to the second open film region at a low temperature. Or, a back metal electrode 7 is formed on the back surface of the n-type doped silicon film layer 5 in the second film opening region by a combination of low-temperature deposition and high-temperature deposition. Because silver is not used in low-temperature deposition and high-temperature deposition, and the resistivity is low, the formed p-type crystalline silicon solar cell is low in cost and good in conducting effect. In the embodiment of the present invention, this is not particularly limited.
In this embodiment of the present invention, optionally, the main gate line of the front metal electrode 4 and/or the back metal electrode 7 is composed of a plurality of pads and a connecting gate line between the pads, the pads are formed by sintering electrode paste, and the connecting gate line is formed by sintering electrode paste or depositing a metal layer at a low temperature. The pad electrode slurry is formed by sintering, so that the cost can be reduced, and good welding reliability can be ensured.
In the embodiment of the invention, a local p + + type doped region is formed on the front surface of a p-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate; depositing a front anti-reflection layer on the front side of the p-type crystal silicon substrate; forming at least one first film opening region in a preset region of the front anti-reflection layer to expose the local p + + type doped region; forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region; forming a passivation tunneling layer on the back surface of the p-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon; forming an n-type doped silicon film layer on the back of the passivation tunneling layer; depositing and forming a back passivation layer on the back of the n-type doped silicon film layer; irradiating laser on a preset area of the back passivation layer to form at least one second film opening area and expose the n-type doped silicon film layer; and forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region. The heterojunction formed in the embodiment of the invention is positioned on the back surface of the p-type crystalline silicon substrate to form a back emitter, so that the back surface of the p-type crystalline silicon substrate is smoother, the performance of the formed heterojunction is better, and the open-circuit voltage can be improved to a certain extent; and compared with the heterojunction positioned on the front side of the p-type crystalline silicon substrate, the heterojunction positioned on the back side of the p-type crystalline silicon substrate does not reduce effective incident light entering the p-type crystalline silicon substrate, and has less optical loss. The passivation tunneling layer is formed on the back surface of the P-type crystal silicon substrate, the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements, and the tunneling matrix comprises: the passivation tunneling layer can passivate a heterojunction and a contact region of a battery emitter, so that surface recombination of the contact region is reduced, and open-circuit voltage and conversion efficiency of the battery are further improved; the above-mentioned group iii and/or group v elements in the passivation tunneling layer 9 form quantum tunneling points, which are beneficial to transition of electrons and current transmission, and improve short-circuit current and open-circuit voltage. The back metal electrode is a grid line electrode and is not a metal electrode on the whole surface, so that the cost is reduced; meanwhile, in the p-type crystalline silicon cell with the structure, the front metal electrode is not directly contacted with the p-type crystalline silicon substrate, and the front metal electrode is contacted with the local p + + type doping region with higher doping concentration to form good ohmic contact, so that the contact resistance can be reduced to a great extent; meanwhile, the back metal electrode is not directly contacted with the p-type crystal silicon substrate, and the back metal electrode is contacted with the n-type doped silicon film layer to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode and the back metal electrode with the p-type crystal silicon substrate is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be further improved; meanwhile, the p-type crystalline silicon solar cell with the structure has the advantages that the processing process is compatible with the existing processing technology, and the manufacturing is simple and convenient.
Fig. 4 shows a flow chart of steps of yet another method of producing a p-type crystalline silicon solar cell in an embodiment of the present invention. The method may comprise the steps of:
step 201, forming a local p + + type doped region on the front surface of a p-type crystal silicon substrate; and the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate.
In the embodiment of the present invention, the above step 201 may refer to the related description of the above step 101, and is not described herein again to avoid repetition.
Step 202, doping to form a p + type doping layer in a region between the front anti-reflection layer and the p-type crystalline silicon substrate and outside the local p + + type doping region; and the doping concentration of the p + type doping layer is between the doping concentration of the local p + + type doping region and the doping concentration of the p-type crystal silicon substrate.
In the embodiment of the invention, a p + -type doping layer 8 can be doped in a region between the p-type crystalline silicon substrate 1 and the front antireflection layer 3 and outside the local p + + -type doping region 2; the local p + + type doped region 2 and the p + type doped layer 8 are of the same doping type and can be all group III elements, and the doping concentration of the p + type doped layer 8 is between the doping concentration of the local p + + type doped region 2 and the doping concentration of the p-type crystal silicon substrate 1.
Specifically, the p + -type doped layer 8 may be doped on the front surface of the p-type crystalline silicon substrate 1 in a region other than the local p + + -type doped region 2 through a printing sintering or low-temperature deposition, which is not particularly limited in the embodiment of the present invention.
Step 203, depositing and forming the front side antireflection layer on the front sides of the local p + + type doped region and the p + type doped layer.
In the embodiment of the present invention, after the p + -type doped layer 8 is formed, the front side anti-reflection layer 3 may be deposited on the front sides of the local p + + -type doped region 2 and the p + -type doped layer 8.
And 204, forming at least one first film opening region in a preset region of the front anti-reflection layer to expose the local p + + type doped region.
Step 205, forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region.
In the embodiment of the present invention, the above steps 203 to 205 may refer to the related descriptions of the above steps 102 to 104, and are not repeated herein to avoid repetition.
And step 206, polishing the back surface of the p-type crystal silicon substrate.
In the embodiment of the invention, the back surface of the p-type crystalline silicon substrate 1 is polished, so that the back surface of the p-type crystalline silicon substrate 1 is smoother, and the smooth back surface is favorable for depositing and forming a high-quality compact passivation tunneling layer.
Step 207, depositing the passivation tunneling layer on the back surface of the p-type crystal silicon substrate after the polishing treatment; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon.
In the embodiment of the invention, the passivation tunneling layer 9 is formed by deposition on the back surface of the p-type crystalline silicon substrate 1 after polishing treatment.
Specifically, a passivation tunneling layer 9 can be formed by depositing on the back side of the p-type crystalline silicon substrate 1 after polishing treatment by using a chemical oxidation or thermal oxidation route. In the embodiment of the present invention, this is not particularly limited.
And 208, forming the n-type doped silicon film layer on the back surface of the passivation tunneling layer.
Specifically, after the passivation tunneling layer 9 is formed by deposition on the back surface of the polished p-type crystalline silicon substrate 1, the n-type doped silicon film layer 5 may be formed on the back surface of the passivation tunneling layer 9.
And 209, depositing a back passivation layer on the back of the n-type doped silicon film layer.
Step 210, irradiating laser on a preset area of the back passivation layer to form at least one second film opening area, and exposing the n-type doped silicon film layer.
And step 211, forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region.
In the embodiment of the present invention, the above steps 209 to 211 may refer to the related descriptions of the above steps 107 to 109, respectively, and are not repeated herein for the sake of avoiding repetition.
In the embodiment of the invention, a local p + + type doped region is formed on the front surface of a p-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate; depositing a front anti-reflection layer on the front side of the p-type crystal silicon substrate; forming at least one first film opening region in a preset region of the front anti-reflection layer to expose the local p + + type doped region; forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region; forming a passivation tunneling layer on the back surface of the p-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon; forming an n-type doped silicon film layer on the back of the passivation tunneling layer; depositing and forming a back passivation layer on the back of the n-type doped silicon film layer; irradiating laser on a preset area of the back passivation layer to form at least one second film opening area and expose the n-type doped silicon film layer; and forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region. The heterojunction formed in the embodiment of the invention is positioned on the back surface of the p-type crystalline silicon substrate to form a back emitter, so that the back surface of the p-type crystalline silicon substrate is smoother, the performance of the formed heterojunction is better, and the open-circuit voltage can be improved to a certain extent; and compared with the heterojunction positioned on the front side of the p-type crystalline silicon substrate, the heterojunction positioned on the back side of the p-type crystalline silicon substrate does not reduce effective incident light entering the p-type crystalline silicon substrate, and has less optical loss. The passivation tunneling layer is formed on the back surface of the P-type crystal silicon substrate, the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements, and the tunneling matrix comprises: the passivation tunneling layer can passivate a heterojunction and a contact region of a battery emitter, so that surface recombination of the contact region is reduced, and open-circuit voltage and conversion efficiency of the battery are further improved; and the group III and/or group V elements in the passivation tunneling layer 9 form quantum tunneling points, which are beneficial to transition of electrons and current transmission, and improve short-circuit current and open-circuit voltage. The back metal electrode is a grid line electrode and is not a metal electrode on the whole surface, so that the cost is reduced; meanwhile, in the p-type crystalline silicon cell with the structure, the front metal electrode is not directly contacted with the p-type crystalline silicon substrate, and the front metal electrode is contacted with the local p + + type doping region with higher doping concentration to form good ohmic contact, so that the contact resistance can be reduced to a great extent; meanwhile, the back metal electrode is not directly contacted with the p-type crystal silicon substrate, and the back metal electrode is contacted with the n-type doped silicon film layer to form good ohmic contact, so that the contact resistance can be reduced to a great extent; the contact area recombination caused by the direct contact of the front metal electrode and the back metal electrode with the p-type crystal silicon substrate is avoided, and the open-circuit voltage and the conversion efficiency of the battery can be further improved; meanwhile, the p-type crystalline silicon solar cell with the structure has the advantages that the processing process is compatible with the existing processing technology, and the manufacturing is simple and convenient.
For the above method embodiment, for the relevant parts of each layer or each region of the p-type crystalline silicon solar cell, reference may be made to the relevant parts in the foregoing p-type crystalline silicon solar cell embodiment, and details are not described here again to avoid repetition.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the application.
Fig. 5 shows a schematic structural diagram of a p-type crystalline silicon solar cell production apparatus according to an embodiment of the present invention.
As shown in fig. 5, a p-type crystalline silicon solar cell production apparatus provided by an embodiment of the present invention may include: an interface 71, a processor 72, a memory 73, and a bus 74; wherein, the bus 74 is used for realizing the connection communication among the interface 71, the processor 72 and the memory 73; the memory 73 stores an executable program, and the processor 72 is configured to execute the executable program stored in the memory 73, so as to implement the steps of p-type crystalline silicon solar cell production in the embodiment as shown in fig. 3 or fig. 4, and achieve the same or similar effects, and therefore, in order to avoid repetition, details are not repeated here.
The present invention further provides a computer-readable storage medium, where one or more executable programs are stored, and the one or more executable programs can be executed by one or more processors to implement the steps of p-type crystalline silicon solar cell production in the embodiment shown in fig. 3 or fig. 4, and can achieve the same or similar effects, and therefore, in order to avoid repetition, the details are not repeated here.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A p-type crystalline silicon solar cell, comprising: a p-type crystalline silicon substrate;
the local P + + type doped region is formed on the front surface of the P-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate;
the front antireflection layer is deposited on the front side of the p-type crystal silicon substrate;
a front metal electrode penetrating through the front anti-reflection layer and contacting the local p + + type doped region;
passivating the tunneling layer; the P-type crystal silicon substrate is formed on the back surface of the P-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon;
the n-type doped silicon film layer is formed on the back surface of the passivation tunneling layer;
the back passivation layer is deposited on the back of the n-type doped silicon film layer;
and a back metal electrode penetrating the back passivation layer and contacting the n-type doped silicon film layer; the back metal electrode is a grid electrode.
2. The p-type crystalline silicon solar cell of claim 1, wherein the width of the localized p + + type doped region is greater than or equal to the width of the front metal electrode.
3. The p-type crystalline silicon solar cell of claim 1, further comprising: the p + -type doping layer is doped in a region which is formed between the front antireflection layer and the p-type crystalline silicon substrate and is outside the local p + + -type doping region; and the doping concentration of the p + type doping layer is between the doping concentration of the local p + + type doping region and the doping concentration of the p-type crystal silicon substrate.
4. The p-type crystalline silicon solar cell of claim 1, wherein the group iii element comprises: boron element; the group V elements include: phosphorus element.
5. The p-type crystalline silicon solar cell according to claim 1, wherein the passivation tunneling layer has a thickness of 0.5-3 nm.
6. The p-type crystalline silicon solar cell of claim 3, wherein the p-type crystalline silicon substrate has a doping concentration of: 1.3X 1015～1×1017(ii) a The doping concentration of the local p + + type doping region is as follows: 1019～1021cm-3The doping concentration of the P + doping layer is as follows: 1018～1020cm-3。
7. The p-type crystalline silicon solar cell of claim 1, wherein the thickness of the p-type crystalline silicon substrate is 50-300 μm.
8. The p-type crystalline silicon solar cell of claim 1, wherein the n-type doped silicon film layer has a thickness of 10nm to 500 nm.
9. The p-type crystalline silicon solar cell of claim 1, wherein the front side anti-reflection layer and the back side passivation layer are each independently selected from the group consisting of: at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon carbide, silicon oxycarbide, and amorphous silicon.
10. The p-type crystalline silicon solar cell of claim 1, wherein the front side antireflective layer has a thickness of 40 to 100 nm; the thickness of the back passivation layer is 40-200 nm.
11. The p-type crystalline silicon solar cell of claim 1, wherein the front metal electrode comprises: any one of an Al electrode, an Al/Ag electrode, a Ni/Cu electrode, a Co/Cu electrode, a Ni/Cu/Sn electrode, a Co/Cu/Ag electrode and a Ni/Cu/Ag electrode; the back metal electrode comprises any one of an Ag electrode, a Ni/Cu electrode, a Co/Ag electrode, a Co/Cu/Sn electrode, a Co/Cu/Ag electrode, a Ni/Cu/Sn electrode and a Ni/Cu/Ag electrode.
12. A p-type crystalline silicon solar cell production method, characterized in that the method comprises:
forming a local p + + type doped region on the front surface of the p-type crystal silicon substrate; the doping concentration of the local p + + type doping area is greater than that of the p-type crystal silicon substrate;
depositing a front anti-reflection layer on the front side of the p-type crystal silicon substrate;
forming at least one first film opening region in a preset region of the front anti-reflection layer to expose the local p + + type doped region;
forming a front metal electrode on the front surface of the local p + + type doped region of the first film opening region;
forming a passivation tunneling layer on the back surface of the p-type crystal silicon substrate; the passivation tunneling layer is a tunneling matrix doped with III-group and/or V-group elements; the tunneling substrate includes: any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, or amorphous silicon;
forming an n-type doped silicon film layer on the back of the passivation tunneling layer;
depositing and forming a back passivation layer on the back of the n-type doped silicon film layer;
irradiating laser on a preset area of the back passivation layer to form at least one second film opening area and expose the n-type doped silicon film layer;
and forming a back metal electrode on the back of the n-type doped silicon film layer of the second film opening region.
13. The method of claim 12, wherein before depositing the front side antireflective layer on the front side of the p-type crystalline silicon substrate, further comprising:
doping to form a p + type doping layer in a region between the front antireflection layer and the p-type crystal silicon substrate and outside the local p + + type doping region;
the doping concentration of the p + type doping layer is between the doping concentration of the local p + + type doping region and the doping concentration of the p-type crystalline silicon substrate;
depositing a front antireflection layer on the front side of the p-type crystal silicon substrate, wherein the front antireflection layer comprises:
and depositing to form the front antireflection layer on the front surfaces of the local p + + type doped region and the p + type doped layer.
14. The method of claim 12, further comprising, prior to forming a passivation tunneling layer on a backside of the p-type crystalline silicon substrate:
polishing the back surface of the p-type crystal silicon substrate;
the forming of the passivation tunneling layer on the back side of the p-type crystal silicon substrate comprises the following steps:
and depositing and forming the passivation tunneling layer on the back surface of the p-type crystal silicon substrate after the polishing treatment.
CN201910551147.2A 2019-06-24 2019-06-24 P-type crystalline silicon solar cell and production method Pending CN112133763A (en)

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US11264529B1 (en) * 2020-08-24 2022-03-01 Jinko Green Energy (Shanghai) Management Co., LTD Solar cell and method for manufacturing the same
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US11264529B1 (en) * 2020-08-24 2022-03-01 Jinko Green Energy (Shanghai) Management Co., LTD Solar cell and method for manufacturing the same
US11721783B2 (en) 2020-08-24 2023-08-08 Shangrao Jinko Solar Technology Development Co., Ltd Solar cell and method for manufacturing the same
CN113394309A (en) * 2021-01-30 2021-09-14 宣城睿晖宣晟企业管理中心合伙企业(有限合伙) Solar cell and preparation method thereof
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