CN115440730A - Method for forming capacitor - Google Patents

Abstract

The present disclosure provides a method of forming a capacitor comprising forming a stack on a substrate comprising a support layer, a first material layer on the support layer, and a second material layer over the first material layer, wherein at least the first material layer comprises an ashable material. The method also includes patterning the stack to form a first opening in the stack, forming a first electrode including a second opening in the first opening, removing the second material layer to expose an upper portion of the outer side surface of the first electrode, ashing the first material layer to expose a lower portion of the outer side surface of the first electrode, and forming a dielectric layer and a second electrode in the second opening of the first electrode and on the outer side surface of the first electrode. Since the method of forming the capacitor of the present disclosure removes the material layer at the lower portion of the stack using the ashing process, the electrode in the stack may be prevented from wobbling in the support layer, thereby increasing the reliability of the capacitor.

Description

Method for forming capacitor

Technical Field

The present disclosure relates to methods of forming capacitors, and more particularly, to methods of forming capacitors including support frames.

Background

A Dynamic Random Access Memory (DRAM) includes a plurality of Memory cells, each of which includes a transistor for controlling a switch and a capacitor as a storage, wherein the transistor and the capacitor are coupled to each other to implement an information Access function. When the capacitor of the memory cell has a higher height, the capacitor has a larger overlap area between the electrodes, so that the capacitor can provide a larger voltage signal. In order to maintain the structural stability of the high capacitor, a support frame is formed in the capacitor to fix the position of the electrodes, preventing the electrodes of the plurality of capacitors from swinging (wbling) to contact each other.

Disclosure of Invention

There is provided in accordance with an embodiment of the present disclosure a method of forming a capacitor including forming a stack on a substrate including a first support layer, a first material layer on the first support layer, and a second material layer over the first material layer, wherein at least the first material layer includes an ashable material. The method also includes patterning the stack to form a first opening in the stack, forming a first electrode including a second opening in the first opening, removing the second material layer to expose an upper portion of an outer side surface of the first electrode, ashing the first material layer to expose a lower portion of the outer side surface of the first electrode, and forming a dielectric layer and a second electrode in the second opening of the first electrode and on the outer side surface of the first electrode.

In one embodiment of the present disclosure, forming the stack on the substrate includes forming a first material layer having a first thickness between 50% and 60% of a thickness of the stack.

In one embodiment of the present disclosure, forming the stack on the substrate includes forming a first material layer and a second material layer having an ashed material, and removing the second material layer includes ashing the second material layer.

In one embodiment of the present disclosure, forming the first electrode in the first opening includes forming the first electrode having an aspect ratio between 35 and 45.

In an embodiment of the present disclosure, forming the stack on the substrate further includes forming a second support layer between the first material layer and the second material layer, and forming a third support layer on the second material layer.

In an embodiment of the present disclosure, removing the second material layer includes selectively etching the second material layer using a wet etching process to leave the first electrode and the second support layer.

In an embodiment of the present disclosure, removing the second material layer further includes forming a third opening in the third support layer adjacent to the first electrode to expose the second material layer, and removing the second material layer through the third opening.

In one embodiment of the present disclosure, ashing the first material layer further includes forming a fourth opening adjacent to the first electrode in the second support layer to expose the first material layer, and ashing the first material layer through the fourth opening.

In one embodiment of the present disclosure, ashing the first material layer further includes removing the first material layer using an ashing process, cleaning the stack using a wet chemical cleaning process, and ammonia treating the first electrode.

In an embodiment of the present disclosure, patterning the stack to form the first opening further includes forming an opening in the second material layer, forming a liner layer on a sidewall of the opening, and etching through a bottom of the liner layer and the first material layer to form the first opening.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard methods in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a flow chart of a method of forming a capacitor according to some embodiments of the present disclosure.

Fig. 2A-2D and 2G-2J illustrate cross-sectional views of devices at various intermediate stages of forming a capacitor according to an embodiment of the present disclosure.

Fig. 2E and 2F show top views of devices at intermediate stages of forming capacitors, according to some embodiments of the present disclosure.

Fig. 3A-3H illustrate cross-sectional views of an apparatus at various intermediate stages of forming a capacitor according to another embodiment of the present disclosure.

Detailed Description

To achieve the various features of the subject matter referred to, the following disclosure provides many different embodiments, or examples. Specific examples of components, configurations, etc., are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element or feature as shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure provides a method of forming a capacitor including forming a stack of at least a lower material layer as an ashable material and removing the ashable material layer with an ashing process after forming an electrode in the stack. Since the ashing process reduces damage to the stack structure, the electrodes in the stack can be aligned and form a highly reliable capacitor.

Fig. 1 depicts a flow diagram of a method 1000 of forming a capacitor in accordance with some embodiments of the present disclosure. Fig. 2A-2D and 2G-2J illustrate cross-sectional views of apparatus 20 at various intermediate stages in method 1000, according to one embodiment of the present disclosure. The method 1000 of forming the apparatus 20 provided by the present disclosure may be best described when referring to fig. 1, 2A-2D, and 2G-2J in combination. It is understood that additional steps may be included before, during, or after the steps of method 1000, and that such modified embodiments are also within the scope of the present disclosure.

Please refer to fig. 1 and fig. 2A. Fig. 2A shows a cross-sectional view of the device 20 at step 1002 in fig. 1. As shown in fig. 2A, a stack 205 of alternating support layers and material layers is formed on a substrate 200, with at least a lower material layer comprising an ashable material. Specifically, a first support layer 210 is formed on the substrate 200, and a first material layer 220, a second support layer 212, a second material layer 230, and a third support layer 214 are sequentially formed on the first support layer 210, wherein the first material layer 220 comprises an ashable material. The first material layer 220 is the material layer closest to the substrate 200 in the stack 205 and may therefore also be referred to as a lower material layer. In contrast, the second material layer 230 is located above the first material layer 220, which may also be referred to as an upper material layer. Although fig. 2A only shows a stack 205 of three support layers and two material layers, the device 20 may include other numbers of stacks 205 of staggered support layers and material layers, such as four support layers and three material layers.

In some embodiments, ashable materials included in first material layer 220, such as carbon-based compounds, resins, polymeric materials, other suitable ashable materials, or combinations thereof, may be patterned or removed in a plasma ashing process. In some embodiments, second material layer 230 may comprise a dielectric material that is removable in a wet etch process, such as silicon oxide, silicate glass, doped borophosphosilicate glass, other oxide dielectric materials, or combinations thereof. In some embodiments, the thickness of the first material layer 220 may be between 50% and 60% of the thickness of the stack 205, and the thickness of the second material layer 230 may be between 40% and 50% of the thickness of the stack 205. For example, the first material layer 220 may be a resin with a thickness of 500nm to 600nm, and the second material layer 230 may be a silicon oxide with a thickness of 400nm to 500 nm.

In some embodiments, the materials forming the first support layer 210, the second support layer 212, and the third support layer 214 may include a dielectric material having an etch selectivity with the second material layer 230 in a wet etching process. For example, the second material layer 230 may be silicon oxide, and the first, second, or third support layers 210, 212, 214 may be silicon nitride. In some embodiments, the materials forming the first support layer 210, the second support layer 212, and the third support layer 214 may be the same material, for example, all three may be silicon nitride.

Please refer to fig. 1 and fig. 2B. Fig. 2B shows a cross-sectional view of the device 20 at step 1004 in fig. 1. As shown in fig. 2B, the stack 205 formed by the support layer and the material layer is patterned such that a first opening 245 is formed in the stack 205. Specifically, a patterned mask 240 having a plurality of holes aligned with the first openings 245 to be formed is formed over the stack 205. An anisotropic etch process (e.g., a dry etch process) is performed on the stack 205 using the mask 240, and the etch process stops on the upper surface of the substrate 200, thereby forming a first opening 245 in the stack 205. After forming the first opening 245, the mask 240 may be removed from the stack 205.

In some embodiments, forming the first opening 245 may include a multi-step etching process. For example, after forming an opening through the third support layer 214 and extending into the second material layer 230 in an etching process using the mask 240, the etching process may be halted to form a liner layer (not shown) conformal to the opening in the opening extending into the second material layer 230. The etching process is then continued such that the etchant penetrates the bottom of the pad layer and etches onto the upper surface of the substrate 200 to form the first support layer 210 and the second support layer 212. By using a multi-step etching process, the first opening 245 with a smooth sidewall can be formed in the stack 205, so that the device formed in the first opening 245 can be reliable.

Please refer to fig. 1 and fig. 2C. Fig. 2C shows a cross-sectional view of the device 20 at step 1006 in fig. 1. As shown in fig. 2C, the first electrode 250 including the second opening 255 is formed in the first opening 245. Specifically, a blanket electrode layer is formed over stack 205 and in first opening 245 (as shown in fig. 2B), and a portion of the blanket electrode layer over stack 205 is removed using, for example, a Chemical Mechanical Polishing (CMP) process, such that first electrode 250 is conformally formed in first opening 245. Since the first electrode 250 is conformal to the first opening 245, the first electrode 250 includes the second opening 255, thereby increasing the exposed surface area of the first electrode 250. Accordingly, the first electrode 250 has a relatively large surface area that may be in contact with other elements subsequently formed therein.

In some embodiments, the material forming the first electrode 250 may include a metal, a metal compound, an alloy compound, other conductive materials, or a combination thereof, such as titanium nitride or silicon-doped titanium nitride. For example, the conductive material may be deposited using a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or the like to form the first electrode 250. In some embodiments, the first electrode 250 has a high aspect ratio, so that the capacitor including the first electrode 250 can provide a larger voltage signal, for example, the aspect ratio of the first electrode 250 can be between 35 to 45.

Please refer to fig. 1 and fig. 2D. Fig. 2D shows a cross-sectional view of the device 20 at step 1008 in fig. 1. As shown in fig. 2D, a third opening 262 is formed in the top support layer of the stack 205. Specifically, a patterned mask 260 is formed over the stack 205, the mask 260 having apertures between the first electrodes 250 adjacent therebelow. An anisotropic etching process (e.g., a dry etching process) is performed on the exposed third support layer 214 using the mask 260, thereby forming a third opening 262 in the third support layer 214. Since the third support layer 214 is uppermost in the stack 205, the third support layer 214 may also be referred to as a top support layer. In contrast, the first support layer 210 on the substrate 200 may be referred to as a bottom support layer, and the second support layer 212 between the first support layer 210 and the third support layer 214 may be referred to as a middle support layer. After forming the third opening 262, the mask 260 may be removed from the stack 205.

In some embodiments, the etching process for forming the third opening 262 is stopped on the upper surface of the second material layer 230 to form the third opening 262 exposing the second material layer 230 in fig. 2D. In some other embodiments, the third opening 262 may extend into the second material layer 230 such that the bottom of the third opening 262 is below the upper surface of the second material layer 230.

The number and location of the third openings 262 may be designed differently according to the material of the second material layer 230 or the parameters of the subsequent etching process. In some embodiments, the third opening 262 may be disposed between the adjacent first electrodes 250 such that the second material layer 230 between the adjacent first electrodes 250 is exposed. In some embodiments, the third openings 262 may be spaced between adjacent first electrodes 250, as shown in fig. 2D. Fig. 2E and 2F depict top views of device 20 at step 1008 in fig. 1, according to some embodiments of the present disclosure. As shown in fig. 2E, the third opening 262 may be positioned in the middle of three first electrodes 250 adjacent to each other. Alternatively, as shown in fig. 2F, the third opening 262 may be located in the middle of four first electrodes 250 adjacent to each other, but the disclosure is not limited to these embodiments.

Please refer to fig. 1 and fig. 2G. Fig. 2G shows a cross-sectional view of the apparatus 20 at step 1010 in fig. 1. As shown in fig. 2G, the second material layer 230 of the stack 205 is removed. Specifically, the second material layer 230 between the second support layer 212 and the third support layer 214 is subjected to an etching process having selectivity (e.g., wet etching) through the third opening 262. Due to the selectivity of the etching process, the second material layer 230 may be removed and the second support layer 212, the third support layer 214, and the first electrode 250 may remain. For example, hydrofluoric acid may be used as an etchant to remove the second material layer 230 comprising silicon oxide. In some embodiments, the etchant for etching the second material layer 230 may include a surfactant, which increases the contact ability of the etchant to the second material layer 230. After removing the second material layer 230, an outer side surface of an upper portion of the first electrode 250 is exposed. In more detail, the outer side surface of the first electrode 250 between the second support layer 212 and the third support layer 214 is exposed to increase the surface area of the first electrode 250 in contact with other elements to be formed later.

Please refer to fig. 1 and 2H. Figure 2H illustrates a cross-sectional view of apparatus 20 at step 1012 of figure 1. As shown in fig. 2H, a fourth opening 264 is formed in the middle support layer of the stack 205. Specifically, the second support layer 212 is subjected to a punching process (punch) using a cutter or a die, thereby forming the fourth opening 264 in the second support layer 212. In some embodiments, the blanking process stops on the upper surface of the first material layer 220 to form a fourth opening 264 below the third opening 262 in fig. 2H. In some other embodiments, fourth opening 264 may extend into first material layer 220.

Please refer to fig. 1 and fig. 2I. Fig. 2I shows a cross-sectional view of the device 20 at step 1014 in fig. 1. As shown in fig. 2I, underlying material layers comprising ashable material in stack 205 are removed. Specifically, the first material layer 220 between the first and second support layers 210 and 212 is subjected to an ashing process through the third and fourth openings 262 and 264 to remove the first material layer 220 and leave the first and second support layers 210 and 212 and the first electrode 250. Removing the first material layer 220 may expose an outer side surface of a lower portion of the first electrode 250, i.e., an outer side surface of the first electrode 250 between the first support layer 210 and the second support layer 212, increasing a surface area of the first electrode 250 in contact with other elements to be formed later.

In some embodiments, the ashing process includes removing the first material layer 220 using a plasma, such as an oxygen-based plasma, a forming gas (a mixture of nitrogen and hydrogen), or a plasma with other suitable gases. After the ashing process, a wet chemical cleaning process (wet clean) may be used to remove residues of the ashing process in the stack 205 and prevent ions generated by the ashing process from attacking the first electrode 250. For example, an acid cleaning device 20 with oxidizing and dehydrating properties may be used to remove the carbon-containing residue of the first material layer 220. In embodiments where an oxygen-based plasma ashing process is used, the method may further include subjecting the stack 205 to an ammonia gas treatment (NH) ₃ A process) for improving defects that may be generated when the first electrode 250 receives the ashing process.

After removing the first material layer 220 and the second material layer 230, the first support layer 210, the second support layer 212, and the third support layer 214 serve as a support frame for supporting the plurality of first electrodes 250 such that the first electrodes 250 are not in contact with each other. Since the ashing process is used to remove the first material layer 220 between the first support layer 210 and the second support layer 212, the lower portion of the stack 205 can be prevented from being damaged due to chemical perturbation (chemical perturbation) caused by the etching process (e.g., wet etching), and thus the first electrodes 250 can be arranged in the stack 205 with reduced swing, thereby increasing the reliability of the device 20.

Please refer to fig. 1 and fig. 2J. Fig. 2J shows a cross-sectional view of device 20 at step 1016 in fig. 1. As shown in fig. 2J, a dielectric layer 270 and a second electrode 275 are formed in the stack 205 to form a capacitor 280. Specifically, a blanket dielectric layer and a blanket electrode layer are formed between the first support layer 210 and the third support layer 214, on the third support layer 214, and in the second openings 255 (shown in fig. 2I) of the first electrodes 250, and portions of the blanket dielectric layer and the blanket electrode layer on the third support layer 214 are removed using, for example, a chemical mechanical polishing process, such that the dielectric layer 270 and the second electrodes 275 are formed between the first support layer 210 and the third support layer 214 and in the second openings 255.

The first electrode 250, the dielectric layer 270 and the second electrode 275 together form a capacitor 280 that serves as other components in the memory connecting means 20. The portion of the first electrode 250 in contact with the dielectric layer 270 includes the inner surface and the outer surface of the first electrode 250, increasing the flow area of current between the first electrode 250 and the second electrode 275, and thus the capacitor 280 is also referred to as a double-sided capacitor. Since the first electrode 250 is aligned between the first support layer 210 and the third support layer 214, the dielectric layer 270 and the second electrode 275 may be formed flatly in the second opening 255 to form the capacitor 280 with high reliability.

Fig. 3A-3H illustrate cross-sectional views of the apparatus 30 at various intermediate stages in the method 1000, according to another embodiment of the present disclosure. The method 1000 of forming the apparatus 30 provided by the present disclosure may be best described when referring to fig. 1 and 3A-3H in combination. The steps of forming device 30 include similar operational steps as forming device 20, and thus the formation of device 30 can be accomplished using the details of method 1000 described above and the description below.

Please refer to fig. 1 and fig. 3A. Fig. 3A shows a cross-sectional view of the device 30 at step 1002 in fig. 1. As shown in fig. 3A, a stack 305 of staggered support layers and material layers is formed on a substrate 300. Specifically, a first support layer 310 is formed on the substrate 300, and a first material layer 320, a second support layer 312, a second material layer 330, and a third support layer 314 are sequentially formed on the first support layer 310, wherein the first material layer 320 and the second material layer 330 comprise ashable materials. In some embodiments, the first material layer 320 and the second material layer 330 may comprise the same ashable material. In some other embodiments, first material layer 320 and second material layer 330 may comprise different ashable materials, for example first material layer 320 may be a carbon-based compound and second material layer 330 may be a resin.

Please refer to fig. 1 and fig. 3B to fig. 3C. Fig. 3B shows a cross-sectional view of device 30 at step 1004 in fig. 1, and fig. 3C shows a cross-sectional view of device 30 at step 1006 in fig. 1. The stack 305 of support layers and material layers is patterned using a mask 340 such that a first opening 345 is formed in the substrate 300. The first electrode 350 is formed in the first opening 345 such that the first electrode 350 is conformal to the first opening 345 and has a second opening 355. Accordingly, the first electrode 350 has a relatively large surface area that can be in contact with other elements subsequently formed therein.

Please refer to fig. 1 and fig. 3D. Fig. 3D shows a cross-sectional view of device 30 at step 1008 in fig. 1. As shown in fig. 3D, a third opening 362 is formed in the top support layer of the stack 305. Specifically, a patterned mask 360 is formed over the stack 305 to expose the third support layer 314 between the adjacent first electrodes 350 thereunder. An anisotropic etching process (e.g., a dry etching process) is performed on the third support layer 314 and the second material layer 330 using the mask 360, thereby forming a third opening 362 on the upper surface of the second support layer 312. After forming the third opening 362, the mask 360 may be removed from the stack 305.

Please refer to fig. 1 and fig. 3E. Fig. 3E shows a cross-sectional view of the device 30 at step 1010 in fig. 1. As shown in fig. 3E, the second material layer 330 of the stack 305 is removed. Specifically, the second material layer 330 between the second support layer 312 and the third support layer 314 is subjected to an ashing process through the third opening 362 to remove the second material layer 330 and leave the second support layer 312, the third support layer 314, and the first electrode 350. Since the second material layer 330 includes an ashable material, the second material layer 330 may be removed using an oxygen or forming gas based plasma.

Please refer to fig. 1 and fig. 3F to fig. 3H. Fig. 3F shows a cross-sectional view of device 30 at step 1012 in fig. 1, fig. 3G shows a cross-sectional view of device 30 at step 1014 in fig. 1, and fig. 3H shows a cross-sectional view of device 30 at step 1016 in fig. 1. A fourth opening 364 is formed in the second support layer 312 of the stack 305 by a die cutting process, and the first material layer 320 of the stack 305 is removed through the third opening 362 and the fourth opening 364 by an ashing process. After the ashing process, a wet chemical cleaning and an ammonia gas treatment may be further included to remove residues of the ashing process and reduce defects of the first electrode 350. The ashing process is used to remove the first material layer 320 and the second material layer 330, so as to prevent the stack 305 from being damaged due to the chemical perturbation of the etching process (e.g., wet etching), thereby reducing the swing of the first electrode 350 in the stack 305, and preventing the first electrodes 350 from contacting each other. Since the first electrode 350 is aligned between the first support layer 310 and the third support layer 314, the dielectric layer 370 and the second electrode 375 may be formed flatly in the second opening 355 to form the capacitor 380 with high reliability.

In accordance with the above embodiments, the present disclosure provides a method of forming a capacitor comprising forming a stack of a support layer and a material layer, and an electrode in the stack, wherein at least a lower material layer comprises an ashable material such that the lower material layer of the stack can be removed using an ashing process and a lower outside surface of the electrode is exposed. Since the ashing process is used to remove the lower material layer, damage to the stacked structure is reduced, so that the exposed electrode can be prevented from wobbling in the support layer. Therefore, the method provided by the disclosure can form the electrodes which are arranged in order, and further form the capacitor with high reliability.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

[ notation ] to show

20,30 device

200 base plate

205 stacking

210 first support layer

212 second support layer

214 third support layer

220 first material layer

230 second material layer

240 mask

245 first opening

250 first electrode

255 second opening

260 mask

262 third opening

264 fourth opening

270 dielectric layer

275 second electrode

280 capacitor

300 base plate

305 stacking

310 first support layer

312 second support layer

314 third support layer

320 first material layer

330 second material layer

340 mask

345 first opening

350 first electrode

355 second opening

360: shade

362 third opening

364 fourth opening

370 dielectric layer

375 second electrode

380 capacitor

1000 method

1002,1004,1006,1008,1010,1012,1014,1016 step.

Claims (10)

1. A method of forming a capacitor, comprising:

forming a stack on a substrate, the stack comprising a first support layer, a first material layer on the first support layer, and a second material layer over the first material layer, wherein at least the first material layer comprises an ashable material;

patterning the stack to form a first opening in the stack;

forming a first electrode in the first opening, the first electrode including a second opening;

removing the second material layer to expose an upper portion of the outer side surface of the first electrode;

ashing the first material layer to expose a lower portion of the outer side surface of the first electrode; and

a dielectric layer and a second electrode are formed in the second opening of the first electrode and on the outer side surface of the first electrode.

2. The method of claim 1, wherein forming the stack on the substrate comprises forming the first material layer having a first thickness between 50% and 60% of a thickness of the stack.

3. The method of claim 1, wherein forming the stack on the substrate comprises forming the first material layer and the second material layer with the ashed material, and removing the second material layer comprises ashing the second material layer.

4. The method of claim 1, wherein forming the first electrode in the first opening comprises forming the first electrode with an aspect ratio in a range from 35 to 45.

5. The method of claim 1, wherein forming the stack on the substrate further comprises:

forming a second support layer between the first material layer and the second material layer; and

a third support layer is formed on the second material layer.

6. The method of claim 5, wherein removing the second material layer comprises selectively etching the second material layer using a wet etch process to leave the first electrode and the second support layer.

7. The method of claim 5, wherein removing the second material layer further comprises:

forming a third opening in the third support layer to expose the second material layer, the third opening being adjacent to the first electrode; and

and removing the second material layer through the third opening.

8. The method of claim 5, wherein ashing the first material layer further comprises:

forming a fourth opening in the second support layer to expose the first material layer, the fourth opening being adjacent to the first electrode; and

and ashing the first material layer through the fourth opening.

9. The method of claim 1, wherein ashing the first material layer further comprises:

removing the first material layer by using an ashing process;

cleaning the stack using a wet chemical cleaning process; and

the first electrode was subjected to ammonia gas treatment.

10. The method of claim 1, wherein patterning the stack to form the first opening further comprises:

forming an opening in the second material layer;

forming a liner layer on sidewalls of the opening; and

etching through the bottom of the liner layer and the first material layer to form the first opening.

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