CN118042833A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN118042833A CN118042833A CN202410184158.2A CN202410184158A CN118042833A CN 118042833 A CN118042833 A CN 118042833A CN 202410184158 A CN202410184158 A CN 202410184158A CN 118042833 A CN118042833 A CN 118042833A
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- layer
- support layer
- lower electrode
- semiconductor device
- sacrificial layer
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 207
- 239000000463 material Substances 0.000 claims description 21
- 239000003989 dielectric material Substances 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 11
- 239000007772 electrode material Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910002938 (Ba,Sr)TiO3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- -1 HfO 2 Chemical class 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate; forming a first sacrificial layer and a first support layer on the substrate; patterning the first support layer and the first sacrificial layer to form an opening, wherein the opening penetrates through the first support layer and the first sacrificial layer; providing a lower electrode formed on the side wall and the bottom surface of the opening and the surface of the first support layer; providing a cover layer formed on the lower electrode of the first support layer surface and forming a hanging part, wherein the hanging part fills the top of the opening; and performing a second etching process to remove the cover layer, part of the lower electrode, part of the first supporting layer and the first sacrificial layer. The invention can reduce the over etching of the lower electrode and the first supporting layer, so that the semiconductor device has better performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
A dynamic random access memory (dynamic random access memory, DRAM) is a volatile memory, which includes an array region composed of a plurality of memory cells and a peripheral region composed of a control circuit. Each memory unit is composed of a transistor and a capacitor electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the aim of storing data.
In order to obtain chips with higher concentration, the structure of the memory cell has been developed toward three dimensions, for example, using stacked capacitor technology. The stacked capacitor technology is to set the capacitor of the memory unit above the substrate, and to realize the electrical connection with the transistor in the substrate in the vertical direction through the plug structure and the connection pad structure, thereby saving the substrate area occupied by the capacitor, and conveniently obtaining larger capacitance by increasing the height of the electrode plate of the capacitor. However, there are still some technical problems to be further improved, such as over-etching during the manufacturing process.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a semiconductor device, which aims to solve the problem of overetching in the manufacturing process.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate; forming a first sacrificial layer and a first support layer on the substrate; patterning the first support layer and the first sacrificial layer to form an opening, wherein the opening penetrates through the first support layer and the first sacrificial layer; providing a lower electrode formed on the side wall and the bottom surface of the opening and the surface of the first support layer; providing a cover layer formed on the lower electrode of the first support layer surface and forming a hanging part, wherein the hanging part fills the top of the opening; and performing a second etching process to remove the cover layer, part of the lower electrode, part of the first supporting layer and the first sacrificial layer.
In an embodiment, the performing a second etching process to remove the cover layer, a portion of the bottom electrode, a portion of the first support layer, and the first sacrificial layer includes: performing a first dry etching process to remove a portion of the cover layer, a portion of the lower electrode and a portion of the first support layer; and performing a first wet etching process to remove the remained covering layer and the first sacrificial layer.
In an embodiment, further comprising: forming a second sacrificial layer and a second support layer on the substrate, wherein the first sacrificial layer is positioned between the first support layer and the second support layer, and the second sacrificial layer is positioned between the second support layer and the substrate; wherein the opening also penetrates the second support layer and the second sacrificial layer; removing a portion of the second support layer; and removing the second sacrificial layer.
In an embodiment, the removing of the portion of the second support layer comprises: providing a protective layer which covers the surface of the lower electrode; a second dry etching process is provided to remove a portion of the second support layer.
In an embodiment, the removing the second sacrificial layer includes: and performing a second wet etching process to remove the second sacrificial layer and the protective layer.
In an embodiment, further comprising: the lower electrode is etched such that a height of the lower electrode in a vertical direction is lower than a height of the first support layer in the vertical direction.
In one embodiment, the material of the lower electrode includes: metal nitrides and/or metal silicides.
In an embodiment, further comprising: providing a high dielectric material layer formed on the surface of the rest lower electrode; providing an upper electrode formed on the surface of the high dielectric material layer; an electrode material is provided, the electrode material surrounds the first support layer and the upper electrode, and covers the top and the side walls of the upper electrode.
In one embodiment, the upper electrode and the lower electrode are the same material.
According to the manufacturing method of the semiconductor device, the covering layer is formed on the upper surface of the lower electrode, and the semiconductor device manufactured by the method has better performance.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a undue limitation on the application, wherein:
Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present application;
FIG. 2A is a schematic view of the first embodiment of section I-I of FIG. 1;
FIG. 2B is a schematic view of the first embodiment of section II-II of FIG. 1;
FIG. 3A is a schematic view of a second embodiment of section I-I of FIG. 1;
FIG. 3B is a schematic view of the second embodiment of section II-II of FIG. 1;
fig. 4 to 12 are schematic structural views of the semiconductor device shown in fig. 3A in section i-i during the fabrication process.
Wherein, the reference numerals are as follows:
100. Substrate and method for manufacturing the same
110. Insulating layer
120. Contact plug
200. Support layer
210. A first supporting layer
220. A second supporting layer
230. Third supporting layer
310. Lower electrode
320. High dielectric material layer
330. Upper electrode
340. Electrode material
400. Sacrificial layer
410. First sacrificial layer
420. Second sacrificial layer
430. Cover layer
431. Hanging part
432. Remaining cover layer
440. 441, 442 Protective layer
900. An opening
Detailed Description
In order that the present invention may be clearly understood by those skilled in the art, the following examples are given to illustrate the gist of the present invention and the technical effects achieved by the present invention with reference to the accompanying drawings. It should be noted that the embodiments of the present invention and the features of the embodiments may be replaced, rearranged, and mixed with each other to complete other embodiments without departing from the spirit of the present invention. The invention will be described in detail below with reference to the drawings in connection with embodiments.
For the sake of easy understanding by the reader and brevity of illustration, various drawings in the present invention depict only a portion of the structure of the semiconductor device and specific elements in the drawings are not necessarily drawn to scale. In addition, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the invention. The relative positions of the opposing elements in the figures described herein will be understood by those skilled in the art, and the resulting structure by inversion or the like is within the scope of the present invention.
The terms "forming" or "disposing" and the like herein generally refer to processing a substrate or material layer through a suitable semiconductor fabrication process to obtain a component of a semiconductor structure therein or thereon, wherein the semiconductor fabrication process may include, but is not limited to, a film forming process, an etching process, a chemical mechanical polishing process, an ion implantation process, a diffusion process, a cleaning process. For example, film forming processes may include, but are not limited to, heat generation, sputtering, evaporation, physical vapor deposition, chemical vapor deposition, electrochemical deposition, atomic layer deposition, epitaxial growth, electroplating. The etching process may include, but is not limited to, wet etching, dry etching.
Referring to fig. 1, 2A, 2B, 3A and 3B, a semiconductor device includes a substrate 100 and a capacitive structure over it.
A plurality of active structures, a plurality of word line structures, and a plurality of bit line structures (not shown) may be sequentially disposed in the substrate 100, wherein an extending direction of the word line structures may be orthogonal to an extending direction of the bit line structures, and the extending direction of the active structures is different from both the word line structures and the bit line structures.
Referring to fig. 2A, 2B, 3A and 3B, the capacitive structure may include a lower electrode 310, an upper electrode 330, and a high dielectric material layer 320 disposed between the lower electrode 310 and the upper electrode 330. In addition, the semiconductor device of the present embodiment may further include a support layer disposed around each of the capacitor structures and an electrode material 340 disposed over the upper electrode 330. The supporting layer 200 may include only the first supporting layer 210, and may further include the second supporting layer 220 and the third supporting layer 230, so long as the supporting layer can effectively support the capacitor structure, and the number of layers of the supporting layer is not specifically limited in the present application.
In some embodiments, the semiconductor device may further include an insulating layer 110 disposed between the substrate 100 and the capacitor structure, and a contact plug 120 penetrating the insulating layer 110 is disposed in the insulating layer 110, where one end of the contact plug 120 is connected to the capacitor structure and the other end is connected to the substrate 100, so as to electrically contact the capacitor structure with the substrate 100.
The method of fabricating the semiconductor device of the present invention will be described with reference to fig. 4 to 12 by taking a semiconductor device having a support layer including a first support layer 210, a second support layer 220, and a third support layer 230 as an example.
Referring to fig. 4, a substrate 100 is provided, an insulating layer 110 is formed on the substrate 100, and a plurality of contact plugs 120 are formed in the insulating layer 110. The insulating layer 110 may have a single-layer structure or a composite-layer structure, and the contact plug 120 may include a conductive material, such as tungsten. The sacrificial layer 400 and the support layer 200 may be formed on the insulating layer 110 and the contact plug 120, only one sacrificial layer 400 and one support layer 200 may be formed (for example, fig. 2A and 2B), or a plurality of sacrificial layers 400 and support layers 200 may be formed alternately in sequence (for example, fig. 3A and 3B). The sacrificial layer 400 and the support layer 200 may be formed by a deposition process, such as a chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. The material of the support layer 200 may include silicon nitride (SiN), silicon carbonitride (SiCN), tantalum oxide (TaO), titanium oxide (TiO), or a combination thereof, and the material of the sacrificial layer 400 may include borophospho-silicate-glass (BPSG), silicon oxide, or the like, which is not particularly limited in the present application. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate (e.g., siC, siGe), a silicon-on-insulator substrate, or a substrate made of other suitable material, which is not particularly limited in the present application.
With continued reference to fig. 4, in some embodiments, the support layer 200 includes a first support layer 210, a second support layer 220; the sacrificial layer 400 includes a first sacrificial layer 410 and a second sacrificial layer 420. Wherein the first sacrificial layer 410 is located between the first support layer 210 and the second support layer 220, and the second sacrificial layer 420 is located between the second support layer 220 and the substrate 100.
The first sacrificial layer 410 may be silicon oxide, the second sacrificial layer 420 may be borophospho-silicate-glass (BPSG), or the like. The material of the first support layer and the second support layer may be silicon carbonitride (SiCN). Through setting up a plurality of supporting layers, be favorable to realizing more firm supporting role to the bottom electrode.
With continued reference to fig. 4, in some embodiments, the support layer 200 further includes a third support layer 230, the third support layer 230 being sandwiched between the second sacrificial layer 420 and the insulating layer 110, and the material of the third support layer 230 may be silicon nitride. The third support layer 230 may function together with the first and second support layers to support the capacitor structure.
The first, second, and third support layers and the first and second sacrificial layers may have a single-layer structure or a composite-layer structure, respectively. The materials of the first, second, and third support layers may be the same or different, and the materials of the first and second sacrificial layers may be the same or different, and are not particularly limited herein.
With continued reference to fig. 4, a mask layer is formed on the first support layer 210, a first etching process is performed using the mask layer as a mask, and the first support layer 210, the first sacrificial layer 410, the second support layer 220, the second sacrificial layer 420, and the third support layer 230 are patterned to form an opening 900, where the opening 900 penetrates through the first support layer 210, the first sacrificial layer 410, the second support layer 220, the second sacrificial layer 420, and the third support layer 230, and exposes the surface of the contact plug 120.
With continued reference to fig. 4, a lower electrode 310 is formed on the sidewalls and bottom of the opening 900 and the surface of the first support layer 210. The lower electrode 310 may be formed by a deposition process, such as a chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the lower electrode 310 may also completely fill the opening 900 or partially fill the opening 900, which is not particularly limited in the present application. The material of the lower electrode 310 may include a metal, a metal silicide, a metal nitride, or a combination thereof, and the metal may include tungsten, titanium, or the like.
Referring to fig. 5, a capping layer 430 is formed on the lower electrode 310 on the surface of the first support layer 210, the capping layer 430 having a plurality of hanging parts (431), the hanging parts (431) filling the top of the opening 900. The capping layer 430 may include a material having a large etching selectivity to the lower electrode 310, the material of the capping layer 430 may include tetraethoxysilane (TETRAETHYL ORTHOSILICATE, TEOS), and the material of the capping layer 430 may be the same as or different from the material of the first sacrificial layer 410. A patterned layer, which may be a photoresist material, and a mask layer (not shown), may be formed on the cover layer 430, and a bottom anti-reflection coating (BARC) layer may be optionally included under the patterned layer. The mask layer may be made of various materials suitable for hard mask, such as silicon nitride, silicon oxynitride, silicon carbide or carbon-containing organic material, and may have a single-layer structure or a composite-layer structure.
Referring to fig. 6 and 7, a second etching process is performed to remove the cover layer 430, a portion of the lower electrode 310, a portion of the first support layer 210, and the first sacrificial layer 410. Specifically, a first dry etching process is performed, a mask layer and a patterned layer (not shown) are sequentially formed on the surface of the cover layer 430, the pattern of the patterned layer is transferred to the mask layer, then the patterned layer is removed, and then the pattern of the mask layer is transferred to the cover layer 430, and the cover layer 430, a portion of the lower electrode 310, and a portion of the first support layer 210 are removed. Then, a first wet etching process is performed to remove the remaining capping layer 432 and the first sacrificial layer 410.
Referring to fig. 7 and 8, in some embodiments, a protective layer 440 is formed on the surface of the lower electrode 310 and/or the surface of the second support layer 220. The material of the protective layer 440 may include silicon oxide, and the process of forming the protective layer 440 may include atomic layer deposition or the like. A second dry etching process is performed to remove a portion of the second supporting layer 220 and the protective layer 440 located on a portion of the surface of the second supporting layer 220, thereby leaving a protective layer 441. By depositing the protective layer 440 on the surface of the lower electrode 310, damage to the lower electrode 310 can be avoided, thereby avoiding overetching of the lower electrode 310.
Referring to fig. 9, the lower electrode 310 is etched such that the height of the lower electrode 310 in the vertical direction is lower than the height of the first support layer 210 in the vertical direction. Wherein, when etching the bottom electrode 310, the passivation layer on the surface of the removed bottom electrode 310 is removed at the same time, leaving the passivation layer 442. By etching such that the height of the lower electrode 310 in the vertical direction is lower than that of the first support layer 210, it is possible to avoid a phenomenon in which the lower electrodes 310, which are closer to each other, are subjected to a point discharge due to the proximity to each other, affecting the electrical performance of the semiconductor device.
Referring to fig. 10, in some embodiments, a second wet etching process is performed to remove the second sacrificial layer 420 and the protection layer 442.
Referring to fig. 3A, 11 and 12, in some embodiments, a high dielectric material layer 320 is formed on the remaining surface of the lower electrode 310; forming an upper electrode 330 on the surface of the high dielectric material layer 320; an electrode material 340 is formed on the surface of the upper electrode 330, the electrode material 340 surrounding the first support layer 210 and the upper electrode 330 and covering the top and sidewalls of the upper electrode 330. The high dielectric material layer 320 and the upper electrode 330 may be formed by a deposition process, such as a chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. Materials for the high dielectric material layer may include metal oxides such as HfO 2、ZrO2、Al2O3、La2O3、Ta2O3 and TiO 2) and perovskite dielectric materials (e.g., srTiO 3、(Ba,Sr)TiO3、BaTiO3, PZT).
According to the manufacturing method of the semiconductor device, the covering layer is formed on the upper surface of the lower electrode, and the semiconductor device manufactured by the method has better performance.
It is noted that the terms used herein are used merely to describe particular embodiments and are not intended to limit exemplary embodiments in accordance with the present application, when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It should be noted that the terms "first," "second," and the like in the description and the claims and drawings of the present application are used for distinguishing between similar objects and not for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
It should be understood that the exemplary embodiments in this specification may be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art, and should not be construed as limiting the application.
While the spirit and principles of the present invention have been described with reference to several particular embodiments, it is to be understood that the invention is not limited to the disclosed embodiments nor does it imply that features of the various aspects are not useful in combination, nor are they useful in any combination, such as for convenience of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (9)
1. A method of fabricating a semiconductor device, comprising:
Providing a substrate;
Forming a first sacrificial layer and a first support layer on the substrate;
Patterning the first support layer and the first sacrificial layer to form an opening, wherein the opening penetrates through the first support layer and the first sacrificial layer;
Providing a lower electrode formed on the side wall and the bottom surface of the opening and the surface of the first support layer;
Providing a cover layer formed on the lower electrode of the first support layer surface and forming a hanging part, wherein the hanging part fills the top of the opening;
And performing a second etching process to remove the cover layer, part of the lower electrode, part of the first supporting layer and the first sacrificial layer.
2. The method of claim 1, wherein performing a second etching process to remove the cap layer, a portion of the bottom electrode, a portion of the first support layer, and the first sacrificial layer comprises:
Performing a first dry etching process to remove a portion of the cover layer, a portion of the lower electrode and a portion of the first support layer;
and performing a first wet etching process to remove the remained covering layer and the first sacrificial layer.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a second sacrificial layer and a second support layer on the substrate, wherein the first sacrificial layer is positioned between the first support layer and the second support layer, and the second sacrificial layer is positioned between the second support layer and the substrate;
Wherein the opening also penetrates the second support layer and the second sacrificial layer;
removing a portion of the second support layer;
And removing the second sacrificial layer.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the removing the portion of the second support layer comprises:
Providing a protective layer which covers the surface of the lower electrode;
a second dry etching process is provided to remove a portion of the second support layer.
5. The method of manufacturing a semiconductor device according to claim 3, wherein the removing the second sacrificial layer comprises:
and performing a second wet etching process to remove the second sacrificial layer and the protective layer.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising:
The lower electrode is etched such that a height of the lower electrode in a vertical direction is lower than a height of the first support layer in the vertical direction.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the lower electrode comprises: metal nitrides and/or metal silicides.
8. The method for manufacturing a semiconductor device according to claim 1, further comprising:
providing a high dielectric material layer formed on the surface of the rest lower electrode;
Providing an upper electrode formed on the surface of the high dielectric material layer;
An electrode material is provided, the electrode material surrounds the first support layer and the upper electrode, and covers the top and the side walls of the upper electrode.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the upper electrode and the lower electrode are made of the same material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410184158.2A CN118042833A (en) | 2024-02-19 | 2024-02-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410184158.2A CN118042833A (en) | 2024-02-19 | 2024-02-19 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN118042833A true CN118042833A (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410184158.2A Pending CN118042833A (en) | 2024-02-19 | 2024-02-19 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| CN (1) | CN118042833A (en) |
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- 2024-02-19 CN CN202410184158.2A patent/CN118042833A/en active Pending
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