CN115413142A - Circuit board manufacturing method and circuit board - Google Patents

Abstract

The application relates to the technical field of circuit board manufacturing, and provides a circuit board manufacturing method and a circuit board, wherein the circuit board manufacturing method comprises the following steps: providing a substrate; carrying out primary exposure and primary development on the substrate; carrying out primary electroplating on the substrate; removing the first photoresist covering the second area; disposing a second photoresist on the substrate; removing the first photoresist and the second photoresist on the substrate; and etching and removing the first copper layer in the first area to be etched and the first copper layer in the second area to be etched. The circuit board manufacturing method can solve the problem that the thin circuit manufactured by the traditional thin circuit manufacturing method is difficult to meet the requirements of thinness and thickness.

Description

Circuit board manufacturing method and circuit board

Technical Field

The application relates to the technical field of circuit board manufacturing, in particular to a circuit board manufacturing method and a circuit board.

Background

In the process of manufacturing the circuit board, in order to make the circuit board meet certain functional requirements, besides the conventional circuit is manufactured on the circuit board, a thin circuit is often required to be manufactured on a part of the circuit board, and part of circuit board products also have a limit on the copper thickness of the thin circuit, so that the thin circuit is required to be thin and thick.

In a traditional method for manufacturing a local thin circuit, a copper layer is often required to be subjected to multiple times of pattern plating and thinning, and then the thinned first copper layer is etched to obtain the thin circuit.

Disclosure of Invention

The application provides a circuit board manufacturing method and a circuit board, and aims to solve the problem that a thin circuit manufactured by a traditional thin circuit manufacturing method is difficult to meet the requirements of thinness and thickness.

An embodiment of a first aspect of the present application provides a method for manufacturing a circuit board, including:

providing a substrate, wherein the substrate is provided with a first copper layer, one side of the first copper layer, which is far away from the substrate, is provided with a first area and a second area, the first area comprises thin line areas and first areas to be etched which are alternately arranged, the second area comprises normal line areas and second areas to be etched which are alternately arranged, and the first area and the second area are both covered with a first photoresist;

carrying out primary exposure and primary development on the substrate, so that the first region to be etched and the second region are covered by the cured first photoresist, and the fine circuit region is exposed;

performing primary electroplating on the substrate to thicken the first copper layer in the fine circuit area;

removing the first photoresist covering the second area and reserving the first photoresist covering the first area to be etched;

arranging a second photoresist on the substrate, and carrying out secondary exposure and secondary development on the substrate, so that the second region to be etched is covered by the cured second photoresist, and the conventional circuit region, the first region and the first photoresist are all exposed;

performing secondary electroplating on the substrate to thicken the first copper layer in the fine circuit region and thicken the first copper layer in the conventional circuit region;

removing the first photoresist and the second photoresist on the substrate;

etching to remove the first copper layer in the first region to be etched and the first copper layer in the second region to be etched, the first copper layer in the fine wiring region forming a fine wiring, the first copper layer in the conventional wiring region forming a conventional wiring.

In some embodiments, removing the first photoresist covering the second region and leaving the first photoresist covering the first region to be etched includes: firstly, attaching a protective film on the first photoresist of the first area to be etched, and then removing the first photoresist covering the second area by using a film removing liquid medicine; removing the protective film before disposing a second photoresist on the substrate.

In some of these embodiments, the first copper layer also has a complimentary plated region adjacent to and spaced from the fine line region; when the substrate is subjected to primary electroplating, the first copper layer in the fine circuit region and the first copper layer in the plating accompanying region are thickened at the same time.

In some embodiments, when the first copper layer in the first region to be etched and the first copper layer in the second region to be etched are etched and removed, the first copper layer in the plating accompanying region is etched and removed simultaneously.

In some of these embodiments, after the second electroplating of the substrate and before the removal of the first and second photoresists on the substrate, a protective layer is provided on both the first copper layer in the fine line region and the first copper layer in the conventional line region.

In some of these embodiments, the thickness of the first photoresist is greater than the thickness of the second photoresist.

In some embodiments, a blind hole is formed in the substrate, the blind hole penetrates through the first copper layer, a third area is further formed on the surface, away from the substrate, of the first copper layer, and the blind hole is located in the third area; and when the substrate is subjected to primary electroplating, filling the blind hole with a first plating layer.

In some embodiments, a through hole is formed in the substrate, a second copper layer is formed on one surface of the substrate, which faces away from the first copper layer, the through hole penetrates through the first copper layer and the second copper layer, a fourth area is further formed on one surface of the first copper layer, which faces away from the substrate, and the through hole is located in the fourth area; and when the substrate is subjected to primary electroplating, covering a second plating layer on the hole wall of the through hole.

An embodiment of a second aspect of the present application provides a method for manufacturing a circuit board, including:

providing a substrate, wherein the substrate is provided with a first copper layer, one side of the first copper layer, which is far away from the substrate, is provided with a first area and a second area, the first area comprises thin line areas and first areas to be etched which are alternately arranged, the second area comprises normal line areas and second areas to be etched which are alternately arranged, and the first area and the second area are both covered with a first photoresist;

carrying out primary exposure and primary development on the substrate, so that the first region to be etched and the second region are covered with the cured first photoresist;

performing primary electroplating on the substrate to thicken the first copper layer in the fine circuit area;

removing the first photoresist covering the second area and the first photoresist covering the first area to be etched;

arranging a second photoresist on the substrate, and carrying out secondary exposure and secondary development on the substrate, so that the first region to be etched and the second region to be etched are both covered by the cured second photoresist, and the conventional circuit region and the fine circuit region are both exposed;

performing secondary electroplating on the substrate to thicken the first copper layer in the fine circuit region and thicken the first copper layer in the conventional circuit region;

removing the second photoresist on the substrate;

etching to remove the first copper layer in the first region to be etched and the first copper layer in the second region to be etched, the first copper layer in the fine wiring region forming a fine wiring, the first copper layer in the conventional wiring region forming a conventional wiring.

Embodiments of the third aspect of the present application provide a circuit board processed by the circuit board manufacturing method according to the first aspect or the second aspect.

The circuit board manufacturing method provided by the embodiment of the application has the beneficial effects that: because carry out the electroplating once to the base plate for first copper layer in the thin circuit region is thickened, then carry out the secondary electroplating to the base plate, make the first copper layer in the thin circuit region thickening, and make the first copper layer in the conventional circuit region thickening, the first copper layer in the first region of waiting to etch and the first copper layer in the second region of waiting to etch of first copper layer in the first region of waiting to etch of etching again at last, alright make the first copper layer in the thin circuit region form the thin circuit, the first copper layer in the conventional circuit region forms conventional circuit, and the first copper layer in the thin circuit region is owing to pass through twice thickening, the thin circuit that forms also can satisfy not only thin but also thick requirement.

Compared with the beneficial effects of the prior art, the circuit board provided by the application has the beneficial effects compared with the prior art, and the manufacturing method of the circuit board provided by the application has no need of repeated description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a flow chart of a method for fabricating a circuit board according to one embodiment of the present application;

FIG. 2 is a schematic view of a substrate according to one embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of the substrate shown in FIG. 2 after the first photoresist covering the second region is removed and the first photoresist covering the first region to be etched is remained;

FIG. 4 is a schematic structural view of the substrate shown in FIG. 3 after the secondary plating;

FIG. 5 is a schematic view of the structure of the substrate shown in FIG. 4 after a protective layer is provided over both the first copper layer in the fine line region and the first copper layer in the conventional line region on the substrate;

fig. 6 is a schematic structural diagram of the substrate after removing the first photoresist and the second photoresist on the substrate shown in fig. 5, and etching to remove the first copper layer in the first region to be etched and the first copper layer in the first region to be etched;

FIG. 7 is a top view of a substrate in one embodiment of the present application.

The designations in the figures mean:

10. a substrate; 11. a first copper layer; 11a, a first region; 11b, a plating accompanying area; 11c, a third region; 11d, a fourth region; 111. a fine line region; 111a, thin lines; 112. a first region to be etched; 12. a dielectric layer; 13. a second copper layer; 14. a first photoresist; 15. a protective layer; 16. blind holes; 17. a first plating layer; 18. a through hole; 19. and (5) second plating.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Reference throughout this specification to "one embodiment," "some embodiments," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In order to explain the technical solution of the present application, the following description is made with reference to the specific drawings and examples.

Referring to fig. 1, fig. 2 and fig. 3, an embodiment of the present application provides a method for manufacturing a circuit board, including:

s101: providing a substrate 10, wherein the substrate 10 is provided with a first copper layer 11, the side, facing away from the substrate 10, of the first copper layer 11 is provided with a first area 11a and a second area, the first area 11a comprises thin line areas 111 and first areas to be etched 112 which are alternately arranged, the second area comprises regular line areas and second areas to be etched which are alternately arranged, and the first area 11a and the second area are both covered with a first photoresist 14.

Specifically, the substrate 10 may be the substrate 10 after the cutting, inner layer circuit, AOI and pressing processes, the number of layers of the substrate 10 may be greater than or equal to 4, the substrate 10 has a dielectric layer 12, the first copper layer 11 is disposed on one side of the dielectric layer 12, the fine circuit region 111 is used to form a fine circuit 111a, a region between any two adjacent fine circuits 111a is a first region to be etched 112, the conventional circuit region is used to form a conventional circuit, the first photoresist 14 is a dry film or a wet film, and the like, the first region 11a and the second region may be adjacent or non-adjacent, the first region 11a is a local region of a side of the first copper layer 11 facing away from the substrate 10, and the second region is a majority region of a side of the first copper layer 11 facing away from the substrate 10.

It is understood that the normal line is a line conventionally required in both line width and line thickness, and the fine line 111a is a line having a smaller line width and a larger line thickness than the normal line.

S102: the substrate 10 is subjected to one exposure and one development, so that the first region to be etched 112 and the second region are both covered with the cured first photoresist 14 and the fine line region 111 is exposed.

Specifically, when the substrate 10 is exposed once, the first photoresist 14 corresponding to the first region to be etched 112 and the second region is exposed to cure the first photoresist 14 corresponding to the first region to be etched 112 and the second region, and then the first photoresist 14 corresponding to the thin line region 111 is removed by using a developing solution, usually a weak alkaline solution, so that the thin line region 111 is not covered by the first photoresist 14.

S103: the substrate 10 is subjected to primary electroplating so that the first copper layer 11 in the fine line region 111 is thickened.

Specifically, referring to fig. 3, the substrate 10 is subjected to an electro-coppering process, such that the first copper layer 11 in the fine line region 111 is thickened for the first time.

Alternatively, to ensure uniformity of the copper thickness of the first copper layer 11 in the fine line region 111, the electroplating may be performed with a small current for a long time, such as a plating parameter of 15asf 90min.

S104: the first photoresist 14 covering the second region is removed, leaving the first photoresist 14 covering the first region to be etched 112.

Specifically, the photoresist on the surface of the substrate 10 covering the second region and cured may be removed by using a stripping solution, and at the same time, the first photoresist 14 covering the first region to be etched 112 is remained to prepare for the subsequent secondary electroplating.

S105: a second photoresist is disposed on the substrate 10, and the substrate 10 is subjected to a second exposure and a second development, so that the second region to be etched is covered by the cured second photoresist and the fine line region 111, the normal line region, and the first photoresist 14 are all exposed.

Specifically, when the substrate 10 is exposed for the second time, the second photoresist on the first photoresist 14 covering the first to-be-etched area 112 and the normal circuit area are exposed to cure all the second photoresist corresponding to the second to-be-etched area, and then the second photoresist on the first photoresist 14, the second photoresist corresponding to the normal circuit area, the second photoresist corresponding to the thin circuit area 111, and the second photoresist on the first photoresist 14 are removed by using a developing solution, usually a weak alkaline solution, but at this time, the first to-be-etched area 112 is still covered with the cured first photoresist 14.

It can be understood that, since the first copper layer 11 in the fine circuit region 111 is already electroplated and thickened during the first electroplating, if the first region to be etched 112 is covered with the cured second photoresist again, due to the precision of the apparatus itself and the expansion and contraction of the substrate 10, when the substrate 10 is subjected to the second exposure and the second development, an alignment error inevitably occurs, which further causes poor precision during the second electroplating of the substrate 10, and affects the precision of the final fine circuit 111a, and the first copper layer 11 in the fine circuit region 111 is already thickened during the first electroplating, and has a height difference with a surface of the first copper layer 11 away from the substrate 10, and if the second photoresist is covered again on the first region to be etched 112, an untight condition is easily generated, and a subsequent etching process is performed, which also affects the precision of the fine circuit 111 a.

S106: the substrate 10 is subjected to secondary plating so that the first copper layer 11 in the fine wiring region 111 is thickened and the first copper layer 11 in the conventional wiring region is thickened.

Specifically, referring to fig. 5, the substrate 10 is subjected to an electro-coppering process, such that the first copper layer 11 in the fine line region 111 is thickened for the second time, and the first copper layer 11 in the conventional line region is thickened for the first time.

To ensure uniformity of the copper thickness of the first copper layer 11 in the fine line region 111 and uniformity of the copper thickness of the first copper layer 11 in the normal line region, the electroplating may be performed with a small current for a long time, for example, with an electroplating parameter of 10asf × 90min.

S107: the first photoresist 14 and the second photoresist on the substrate 10 are removed.

Specifically, referring to fig. 6, a stripping solution may be used to strip all of the first photoresist 14 and all of the second photoresist on the substrate 10.

S108: the first copper layer 11 in the first region to be etched 112 and the first copper layer 11 in the second region to be etched are etched away, the first copper layer 11 in the fine wiring region 111 forms a fine wiring 111a, and the first copper layer 11 in the conventional wiring region forms a conventional wiring.

Specifically, since the thickness of the first copper layer 11 is generally thin, for example, less than 8 μm, the substrate 10 may be directly subjected to etching (flash etching), after the etching is completed, the first copper layer 11 in the first region to be etched 112 and the first copper layer 11 in the second region to be etched are both removed, the first copper layer 11 in the remaining fine wiring region 111 forms a fine wiring 111a, and the first copper layer 11 in the remaining conventional wiring region forms a conventional wiring.

It can be understood that since the first region to be etched 112 is not thickened and reduced by multiple electroplating, and the uniformity is maintained, the etching time and the etching amount are controlled better, so as to avoid the abnormal problem of non-uniform etching caused by the thickness difference of the first copper layer 11, and the thickness of the first copper layer in the first region to be etched 112 is not changed greatly, and the uniformity is better.

In the method for manufacturing a circuit board provided in the embodiment of the application, the substrate 10 is subjected to primary electroplating to thicken the first copper layer 11 in the fine circuit region 111, then the substrate 10 is subjected to secondary electroplating to thicken the first copper layer 11 in the fine circuit region 111 and thicken the first copper layer 11 in the conventional circuit region, and finally the first copper layer 11 in the first region 112 to be etched and the first copper layer 11 in the second region to be etched are etched and removed, so that the first copper layer 11 in the fine circuit region 111 forms the fine circuit 111a, the first copper layer 11 in the conventional circuit region forms the conventional circuit, and the first copper layer 11 in the fine circuit region 111 is thickened twice, so that the formed fine circuit 111a can also meet the requirements of thinness and thinness.

Optionally, after the first copper layer 11 in the first region to be etched 112 and the first copper layer 11 in the second region to be etched are removed by etching, the protective layer 15 is removed, and the processes of solder mask, ni-pd-au, molding, testing, FQC, and the like are performed on the substrate 10.

As another embodiment of the present application, when the first photoresist 14 covering the second region is removed, the first photoresist 14 covering the first region to be etched 112 is simultaneously removed, then the second photoresist is disposed on the substrate 10, and the substrate 10 is subjected to the second exposure and the second development, so that the first etched region and the second region to be etched are both covered by the cured second photoresist and the normal line region and the fine line region are both exposed; after the secondary plating is performed on the substrate 10, only the second photoresist on the substrate 10 is removed. In this way, the first copper layer 11 in the fine line region 111 may be formed into the fine line 111a, the first copper layer 11 in the normal line region may be formed into the normal line, and the first copper layer 11 in the fine line region 111 may be thickened twice to form the fine line 111a which satisfies the requirement of being both thin and thick.

Referring to fig. 2 and 3, in some embodiments, removing the first photoresist 14 covering the second region and leaving the first photoresist 14 covering the first region to be etched 112 includes: firstly, a protective film is attached to the first photoresist 14 of the first area to be etched 112, and then a film removing liquid medicine is used for removing the first photoresist 14 covering the second area; before the second photoresist is provided on the substrate 10, the protective film is removed.

By adopting the above scheme, the first photoresist 14 of the first region to be etched 112 can be protected from being removed by the stripping chemical by using the protective film.

It is to be understood that the protective film may also directly cover the first region 11a, i.e., directly cover both the fine line region 111 and the first region to be etched 112. Therefore, the protective film can be conveniently attached.

Optionally, the protective film is an acid-base-resistant removable film, such as PI (Polyimide, polyimide film, blue glue film, etc.).

Alternatively, after the substrate 10 is pretreated, that is, after the area of the substrate 10 to which the second photoresist needs to be attached is cleaned and roughened, the protective film is removed. Thus, damage to the first photoresist 14 in the first region to be etched 112 caused by the pretreatment process can be avoided.

Referring to fig. 5 and 6, in some embodiments, after the second electroplating of the substrate 10 and before the removal of the first photoresist 14 and the second photoresist on the substrate 10, a protective layer 15 is disposed on the first copper layer 11 in the fine circuit region 111 and the first copper layer 11 in the normal circuit region.

By adopting the above scheme, when the first copper layer 11 has a large thickness, the protective layer 15 can be used to protect the first copper layer 11 in the fine circuit region 111 and the first copper layer 11 in the normal circuit region from being corroded by the etching solution in the following, and the protective layer 15 can be plated with tin or the like.

Referring to fig. 3, 6 and 7, in some embodiments, the first copper layer 11 further has a plating assistant region 11b adjacent to and spaced apart from the fine line region 111; when the substrate 10 is subjected to the primary plating, the first copper layer 11 in the fine line region 111 and the first copper layer 11 in the plating accompanying region 11b are simultaneously thickened.

By adopting the above scheme, when the substrate 10 is subjected to primary electroplating, the current of the fine line region 111 can be dispersed, so that the increased thickness of the first copper layer 11 in the fine line region 111 is more uniform, and the situation that the subsequent first photoresist 14 is not easily removed due to the excessive increase of the thickness of the first copper layer 11 is avoided.

It can be understood that the plating accompanying region 11b is a base material region on the substrate 10 where no circuit needs to be fabricated, the plated area thereof should be equivalent to the area of the fine circuit region 111, the shape thereof is flexibly set according to the size of the base material region, for example, the base material region is larger, the plating accompanying region may also be designed into the same shape as the fine circuit region 111, for example, the base material region is smaller, or may be designed into a copper block, a grid or other forms, without limitation, and the number of the plating accompanying regions 11b may be one or more.

It is understood that the first photoresist 14 on the plating-accompanied region 11b should be removed after one exposure and one development of the substrate 10.

Alternatively, when the first copper layer 11 in the first region to be etched 112 and the first copper layer 11 in the second region to be etched are etched and removed, the first copper layer 11 in the plating accompanying region 11b is etched and removed at the same time.

It can be understood that the first copper layer 11 in the plating accompanying region 11b is covered with the cured second photoresist, so as to avoid that the first copper layer 11 in the subsequent plating accompanying region 11b is plated with tin and cannot be etched away.

In some of these embodiments, the thickness of the first photoresist 14 is greater than the thickness of the second photoresist. Therefore, the phenomenon that the first photoresist 14 is clamped in the middle by the first copper layer 11 in the thin circuit region 111 and cannot be washed off completely to cause incomplete subsequent etching due to the fact that the difference between the copper thickness of the first copper layer 11 in the thin circuit region 111 and the thickness of the first photoresist 14 is too large after the first copper layer 11 in the thin circuit region 111 is thickened twice can be avoided.

Referring to fig. 2, fig. 3 and fig. 4, in some embodiments, a blind hole 16 is disposed on the substrate 10, the blind hole 16 penetrates through the first copper layer 11, a third region 11c is further disposed on a surface of the first copper layer 11 facing away from the substrate 10, and the blind hole 16 is located in the third region 11 c; when the substrate 10 is subjected to primary plating, the blind via 16 is filled with the first plating layer 17, that is, the blind via 16 is filled with the first plating layer 17.

By adopting the above scheme, the hole metallization process of the blind hole 16 can be completed while the conventional circuit and the fine circuit 111a are manufactured on the substrate 10, that is, the first plating layer 17 is filled in the hole of the blind hole 16, and the production efficiency is improved.

Alternatively, if the first plating layer 17 is to be further thickened, the first plating layer 17 in the blind via 16 is thickened when the substrate 10 is subjected to secondary plating. When the protective layer 15 is provided on both the first copper layer 11 in the fine wiring region 111 and the first copper layer 11 in the normal wiring region, the protective layer 15 is provided on the thickened first plating layer 17 at the same time.

Optionally, in order to ensure the conductivity of the blind hole 16, the concavity of the blind hole 16 after hole filling needs to be less than or equal to 15um.

Optionally, a through hole 18 is formed in the substrate 10, a second copper layer 13 is disposed on a surface of the substrate 10 away from the first copper layer 11, the through hole 18 penetrates through the first copper layer 11 and the second copper layer 13, a fourth region 11d is further formed on a surface of the first copper layer 11 away from the substrate 10, and the through hole 18 is located in the fourth region 11 d; the substrate 10 is subjected to a first plating process so that the walls of the through holes 18 are covered with the second plating layer 19.

By adopting the above scheme, the hole metallization process of the through hole 18 can be completed while the conventional circuit and the fine circuit 111a are manufactured on the substrate 10, that is, the second plating layer 19 on the hole wall of the through hole 18 reaches the preset thickness, and the production efficiency is improved. And the copper surfaces of the first copper layer 11 and the second copper layer 13 are kept good in uniformity without being subjected to multiple times of copper plate deposition.

Alternatively, if the second plating layer 19 is to be further thickened, the second plating layer 19 is thickened when the substrate 10 is subjected to secondary plating. When the protective layer 15 is provided on both the first copper layer 11 in the fine wiring region 111 and the first copper layer 11 in the normal wiring region, the protective layer 15 is provided simultaneously on both the thickened second plating layer 19 and the second copper layer 13.

It will be appreciated that the second copper layer 13 is disposed on a side of the dielectric layer 12 facing away from the first copper layer 11, and that the blind holes 16 and the through holes 18 may be disposed in plurality at intervals, and that the blind holes 16 may be disposed on both the first copper layer 11 and the second copper layer 13.

Alternatively, the machining of the blind holes 16 and the through holes 18 may be accomplished in particular by means of laser ablation, mechanical milling or a combination of both.

Optionally, before the substrate 10 is subjected to primary electroplating, copper deposition and board electroplating are performed on the substrate 10, so that copper layers with a certain thickness are deposited in the blind holes 16 and the through holes 18, and the hole walls of the blind holes 16 and the through holes 18 are electrically connected with the board surface (i.e., the first copper layer 11) of the substrate 10, which is convenient for subsequent electroplating thickening, so that the thickness of the first copper layer 11 increased by the secondary copper deposition and electroplating is small, and the influence on the uniformity of the copper thickness of the first copper layer 11 is also small.

In another aspect, embodiments of the present application provide a circuit board, which is processed by the circuit board manufacturing method as described above.

According to the circuit board provided by the embodiment of the application, since the substrate 10 is firstly electroplated once during manufacturing, the first copper layer 11 in the thin circuit region 111 is thickened, then the substrate 10 is electroplated twice, the first copper layer 11 in the thin circuit region 111 is thickened, the first copper layer 11 in the conventional circuit region is thickened, and finally the first copper layer 11 in the first region 112 to be etched and the first copper layer 11 in the second region to be etched are etched and removed, so that the first copper layer 11 in the thin circuit region 111 can form the thin circuit 111a, the first copper layer 11 in the conventional circuit region forms the conventional circuit, and the first copper layer 11 in the thin circuit region 111 can meet the requirements of thinness and thinness due to twice thickening.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A circuit board manufacturing method is characterized by comprising the following steps:

providing a substrate, wherein the substrate is provided with a first copper layer, one side of the first copper layer, which faces away from the substrate, is provided with a first area and a second area, the first area comprises thin line areas and first areas to be etched which are alternately arranged, the second area comprises regular line areas and second areas to be etched which are alternately arranged, and the first area and the second area are both covered with a first photoresist;

carrying out primary exposure and primary development on the substrate, so that the first region to be etched and the second region are covered by the cured first photoresist, and the fine circuit region is exposed;

performing primary electroplating on the substrate to thicken the first copper layer in the fine circuit area;

removing the first photoresist covering the second area, and remaining the first photoresist covering the first area to be etched;

arranging a second photoresist on the substrate, and carrying out secondary exposure and secondary development on the substrate, so that the second region to be etched is covered by the cured second photoresist, and the conventional circuit region, the fine circuit region and the first photoresist are all exposed;

performing secondary electroplating on the substrate to thicken the first copper layer in the fine circuit region and thicken the first copper layer in the conventional circuit region;

removing the first photoresist and the second photoresist on the substrate;

etching to remove the first copper layer in the first region to be etched and the first copper layer in the second region to be etched, wherein the first copper layer in the fine line region forms a fine line, and the first copper layer in the conventional line region forms a conventional line.

2. The method for manufacturing a circuit board according to claim 1, wherein removing the first photoresist covering the second region and leaving the first photoresist covering the first region to be etched comprises: firstly, attaching a protective film on the first photoresist of the first area to be etched, and then removing the first photoresist covering the second area by using a film removing liquid medicine; removing the protective film before disposing a second photoresist on the substrate.

3. The method of claim 1, wherein the first copper layer further has plating areas adjacent to and spaced from the fine circuit areas; when the substrate is subjected to primary electroplating, the first copper layer in the fine circuit region and the first copper layer in the plating accompanying region are thickened at the same time.

4. The method for manufacturing a circuit board according to claim 3, wherein the first copper layer in the plating accompanying region is etched and removed simultaneously when the first copper layer in the first region to be etched and the first copper layer in the second region to be etched are etched and removed.

5. The method of manufacturing a wiring board according to claim 1, wherein after the substrate is subjected to the secondary plating and before the first photoresist and the second photoresist on the substrate are removed, a protective layer is provided on both the first copper layer in the fine wiring region and the first copper layer in the conventional wiring region.

6. The method for manufacturing a circuit board according to claim 1, wherein the thickness of the first photoresist is greater than that of the second photoresist.

7. The manufacturing method of the circuit board according to any one of claims 1 to 6, wherein a blind hole is formed in the substrate, the blind hole penetrates through the first copper layer, a third area is further formed on one surface, away from the substrate, of the first copper layer, and the blind hole is located in the third area; and when the substrate is subjected to primary electroplating, filling the blind hole with a first plating layer.

8. The manufacturing method of the circuit board according to any one of claims 1 to 6, wherein a through hole is formed in the substrate, a second copper layer is formed on one surface of the substrate, which is away from the first copper layer, the through hole penetrates through the first copper layer and the second copper layer, a fourth area is further formed on one surface of the first copper layer, which is away from the substrate, and the through hole is located in the fourth area; and when the substrate is subjected to primary electroplating, covering a second plating layer on the hole wall of the through hole.

9. A circuit board manufacturing method is characterized by comprising the following steps:

providing a substrate, wherein the substrate is provided with a first copper layer, one side of the first copper layer, which faces away from the substrate, is provided with a first area and a second area, the first area comprises thin line areas and first areas to be etched which are alternately arranged, the second area comprises regular line areas and second areas to be etched which are alternately arranged, and the first area and the second area are both covered with a first photoresist;

carrying out primary exposure and primary development on the substrate, so that the first region to be etched and the second region are covered with the cured first photoresist;

performing primary electroplating on the substrate to thicken the first copper layer in the fine circuit area;

removing the first photoresist covering the second region and the first photoresist covering the first region to be etched;

arranging a second photoresist on the substrate, and carrying out secondary exposure and secondary development on the substrate, so that the first region to be etched and the second region to be etched are both covered by the cured second photoresist, and the conventional circuit region and the fine circuit region are both exposed;

performing secondary electroplating on the substrate to thicken the first copper layer in the fine circuit region and thicken the first copper layer in the conventional circuit region;

removing the second photoresist on the substrate;

etching to remove the first copper layer in the first region to be etched and the first copper layer in the second region to be etched, the first copper layer in the fine wiring region forming a fine wiring, the first copper layer in the conventional wiring region forming a conventional wiring.

10. A wiring board processed by the wiring board manufacturing method according to any one of claims 1 to 9.

Images