CN115413109A - Circuit board and manufacturing method thereof - Google Patents

Circuit board and manufacturing method thereof Download PDF

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Publication number
CN115413109A
CN115413109A CN202110594647.1A CN202110594647A CN115413109A CN 115413109 A CN115413109 A CN 115413109A CN 202110594647 A CN202110594647 A CN 202110594647A CN 115413109 A CN115413109 A CN 115413109A
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CN
China
Prior art keywords
layer
groove
conductor
circuit
insulating
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110594647.1A
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Chinese (zh)
Inventor
李成佳
杨梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
Original Assignee
Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongqisheng Precision Electronics Qinhuangdao Co Ltd, Avary Holding Shenzhen Co Ltd filed Critical Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Priority to CN202110594647.1A priority Critical patent/CN115413109A/en
Priority to TW110119908A priority patent/TWI819313B/en
Publication of CN115413109A publication Critical patent/CN115413109A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

The application provides a circuit board, which comprises a circuit substrate. The circuit substrate comprises a substrate layer, a first conductive circuit layer, a second conductive circuit layer, a first conductor layer, a first insulating layer and a second conductor layer. The first conducting circuit layer and the second conducting circuit layer are arranged on two opposite surfaces of the base material layer, the circuit substrate is provided with a first groove which penetrates through the base material layer and the first conducting circuit layer, the second conducting circuit layer is exposed from the first groove, the first conductor layer is arranged in the first groove and connected with the first conducting circuit layer and the second conducting circuit layer, the second groove is formed in the first conductor layer, the first insulating layer is arranged in the second groove and provided with a third groove, and the second conductor layer is arranged in the third groove. The application also provides a manufacturing method of the circuit board.

Description

Circuit board and manufacturing method thereof
Technical Field
The present disclosure relates to circuit electronics, and particularly to a circuit board and a method for manufacturing the same.
Background
In order to meet the development requirements of high integration and miniaturization of electronic products, circuit boards are also developed towards the trend of light weight, thinness and miniaturization. One existing solution is to design a multilayer circuit board. However, as the conductor layer increases, the thickness of the circuit board increases.
Disclosure of Invention
Accordingly, it is desirable to provide a circuit board and a method for manufacturing the same that can solve the above problems.
The application provides a circuit board, which comprises a circuit substrate. The circuit substrate comprises a base material layer, a first conductive circuit layer, a second conductive circuit layer, a first conductor layer, a first insulating layer and a second conductor layer. The first conducting circuit layer and the second conducting circuit layer are arranged on two opposite surfaces of the base material layer, the circuit substrate is provided with a first groove which penetrates through the base material layer and the first conducting circuit layer, the second conducting circuit layer is exposed from the first groove, the first conductor layer is arranged in the first groove and connected with the first conducting circuit layer and the second conducting circuit layer, the second groove is formed in the first conductor layer, the first insulating layer is arranged in the second groove and provided with a third groove, and the second conductor layer is arranged in the third groove.
The application also provides a manufacturing method of the circuit board, which comprises the following steps:
providing a double-sided copper-clad plate, wherein the double-sided copper-clad plate comprises a substrate layer, and a first copper foil layer and a second copper foil layer which are arranged on two opposite surfaces of the substrate layer;
a first groove is formed on the double-sided covering board. The first groove penetrates through the substrate layer and the first copper foil layer, and part of the second copper foil layer is exposed out of the first groove;
filling a first conductive material in the first groove, and removing part of the first conductive material to form a second groove so as to obtain a first conductor layer;
filling a first insulating material in the second groove, and removing part of the first insulating material to form a third groove to obtain a first insulating layer;
filling a second conductive material in the third groove, and removing part of the second conductive material to form a fourth groove to obtain a second conductor layer;
filling a second insulating material in the fourth groove, and removing part of the second insulating material to form a fifth groove to obtain a second insulating layer;
filling a third conductive material in the fifth groove to obtain a third conductor layer;
and carrying out circuit manufacturing on the first copper foil layer and the second copper foil layer to form a first conductive circuit layer and a second conductive circuit layer, so as to obtain the circuit substrate.
According to the circuit board and the manufacturing method thereof, the first groove is formed in the double-sided circuit substrate, and the plurality of conductor layers are arranged in the first groove, so that the double-sided circuit substrate has the effects of a plurality of layers of circuit substrates, the thickness of the circuit substrate is reduced, and thinning is facilitated.
Drawings
Fig. 1 is a cross-sectional view of a double-sided copper-clad plate provided in an embodiment of the present application.
Fig. 2 is a cross-sectional view of the double-sided copper-clad plate shown in fig. 1 after grooves are formed.
Fig. 3 is a cross-sectional view after forming a first conductive material in the recess shown in fig. 2.
Fig. 4 is a cross-sectional view of the first conductive layer formed by removing a portion of the first conductive material shown in fig. 3.
Fig. 5 is a cross-sectional view of the first conductor layer of fig. 4 after forming a first insulating material thereon.
Fig. 6 is a cross-sectional view of the portion of the insulating material shown in fig. 5 after the first insulating layer is removed.
Fig. 7 is a cross-sectional view after forming a first conductive material on the first insulating layer shown in fig. 6.
Fig. 8 is a cross-sectional view of the second conductor layer formed by removing a portion of the first conductive material shown in fig. 7.
Fig. 9 is a cross-sectional view after forming a first insulating material on a second conductor layer.
Fig. 10 is a cross-sectional view of the second insulating layer formed by removing a portion of the first insulating material shown in fig. 9.
Fig. 11 is a cross-sectional view of the second insulating layer shown in fig. 10 after a third conductive layer is formed thereon.
Fig. 12 is a schematic cross-sectional view of the structure of fig. 11 after circuit fabrication.
Fig. 13a is a schematic cross-sectional view of a circuit substrate according to an embodiment of the present application.
Fig. 13b is a schematic cross-sectional view of a circuit substrate according to another embodiment of the present application.
Fig. 13c is a schematic cross-sectional view of a circuit substrate according to yet another embodiment of the present application.
Fig. 14 is a schematic cross-sectional view of the conductive layer shown in fig. 12 after a metal layer is formed on the surface thereof.
Fig. 15 is a schematic cross-sectional view after a third insulating layer and a capping film are provided on the structure shown in fig. 14.
Fig. 16 is a schematic cross-sectional view of a circuit board according to an embodiment of the present application.
Description of the main elements
Double-sided copper-clad plate 10
Substrate layer 11
First copper foil layer 13
Second copper foil layer 14
First groove 101
First conductive material 20
Second groove 21
First conductor layer 22
First insulating material 30
Third recess 31
First insulating layer 32
Second conductive material 40
Fourth groove 41
Second conductor layer 42
Second insulating material 50
Fifth groove 51
Second insulating layer 52
Third conductor layer 60
Exposed surfaces 221, 321, 421, 521, 61
First conductive trace layer 131
Second conductive trace layer 141
Conductive layer 110
Metal layer 70
Connection pad 71
Third insulating layer 80
Covering film 90
Laminated structure 200
Adhesive layer 91
Cover layer 92
Circuit board 300
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive effort based on the embodiments in the present application are within the scope of protection of the present application.
An embodiment of the present application provides a method for manufacturing a circuit board, which includes the following steps.
Step S1, please refer to fig. 1, providing a double-sided copper-clad plate 10. The double-sided copper-clad plate 10 comprises a substrate layer 11, and a first copper foil layer 13 and a second copper foil layer 14 which are arranged on two opposite surfaces of the substrate layer 11.
In some embodiments, the material of the substrate layer 11 is selected from at least one of Polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and Polyethylene (PE).
Step S2, referring to fig. 2, a first groove 101 is formed on the double-sided copper-clad plate 10. The first groove 101 penetrates the substrate layer 11 and the first copper foil layer 13, and a part of the second copper foil layer 14 is exposed from the first groove 101. In this embodiment, a portion of the first copper foil layer 13 and a portion of the substrate layer 11 are removed by laser cutting to form the first groove 101. In other embodiments, part of the first copper foil layer 13 and part of the substrate layer 11 may also be removed by other means.
In some embodiments, the cross-sectional shape of the first groove 101 is U-shaped.
In step S3, referring to fig. 3, a first conductive material 20 is filled in the first groove 101. The first conductive material 20 completely fills the first recess 101. In this embodiment, the first conductive material 20 is filled in the first groove 101 by printing. In other embodiments, the first conductive material 20 may also be filled in the first groove 101 by other methods.
In step S4, referring to fig. 4, a portion of the first conductive material 20 is removed to form a second groove 21, so as to obtain a first conductive layer 22. The removed part of the first conductive material 20 serves as the first conductor layer 22, and the space where the removed part of the first conductive material 20 is located serves as the second groove 21. In this embodiment, a portion of the first conductive material 20 is removed by laser cutting. In other embodiments, other ways of removing portions of the first conductive material 20 may also be used.
In some embodiments, the cross-sectional shape of the second groove 21 is U-shaped, that is, the cross-sectional shape of the first conductor layer 22 is U-shaped.
In step S5, referring to fig. 5, the second groove 21 is filled with a first insulating material 30. The first insulating material 30 fills the second groove 21. In this embodiment, the first insulating material 30 is filled in the second groove 21 by printing.
In step S6, referring to fig. 6, a portion of the first insulating material 30 is removed to form a third groove 31, so as to obtain a first insulating layer 32. The removed portion of the first insulating material 30 serves as the first insulating layer 32, and the space where the removed portion of the first insulating material 30 is located serves as the third groove 31. In this embodiment, a portion of the first insulating material 30 is removed by laser cutting.
In some embodiments, the cross-sectional shape of the third groove 31 is U-shaped, that is, the cross-sectional shape of the first insulating layer 32 is U-shaped.
In step S7, referring to fig. 7, a second conductive material 40 is filled in the third groove 31. The second conductive material 40 fills the third groove 31. In this embodiment, the second conductive material 40 is filled in the third recess 31 by printing.
In step S8, referring to fig. 8, a portion of the second conductive material 40 is removed to form a fourth groove 41, so as to obtain a second conductive layer 42. The second conductive material 40 with the removed portion serves as the second conductor layer 42, and the space where the second conductive material 40 with the removed portion is located serves as the fourth groove 41. In this embodiment, a portion of the second conductive material 40 is removed by laser cutting.
In some embodiments, the cross-sectional shape of the fourth groove 41 is U-shaped, that is, the cross-sectional shape of the second conductor layer 42 is U-shaped.
In step S9, referring to fig. 9, a second insulating material 50 is filled in the fourth groove 41. The second insulating material 50 fills the fourth groove 41. In this embodiment, the second insulating material 50 is filled in the fourth recess 41 by printing.
In step S10, referring to fig. 10, a portion of the second insulating material 50 is removed to form a fifth groove 51, so as to obtain a second insulating layer 52. The second insulating layer 52 is formed by removing a portion of the second insulating material 50, and the space where the removed portion of the second insulating material 50 is located is the fifth groove 51. In this embodiment, a portion of the second insulating material 50 is removed by laser cutting.
In some embodiments, the cross-sectional shape of the fifth groove 51 is U-shaped, that is, the cross-sectional shape of the second insulating layer 52 is U-shaped.
In step S11, referring to fig. 11, a third conductive material is filled in the fifth groove 51 to obtain a third conductive layer 60. After the third conductive material filled in the fifth groove 51 is cured, the third conductor layer 60 is formed. In this embodiment, the fifth recess 51 is filled with the third conductive material by printing.
The third conductor layer 60 is located approximately at the center of the first groove 101. The cross-sectional shape of the third conductor layer 60 is substantially rectangular. Two side walls of the first conductor layer 22 are respectively connected to the first copper foil layer 13, and the bottom wall of the first conductor layer 22 is connected to the second copper foil layer 14.
The first conductor layer 22 has an exposed surface 221 exposed outside the double-sided copper-clad plate 10, the first insulation layer 32 has an exposed surface 321 exposed outside the double-sided copper-clad plate 10, the second conductor layer 42 has an exposed surface 421 exposed outside the double-sided copper-clad plate 10, the second insulation layer 52 has an exposed surface 521 exposed outside the double-sided copper-clad plate 10, and the third conductor layer 60 has an exposed surface 61 exposed outside the double-sided copper-clad plate 10, wherein each exposed surface is flush with the surface of the first copper foil layer 13 departing from the substrate layer 11.
In some embodiments, the first conductive material 20, the second conductive material 40, and the third conductive material are each selected from at least one of a conductive copper paste or a conductive silver paste.
In some embodiments, the first insulating material 30 and the second insulating material 50 are made of high frequency materials, such as Liquid Crystal Polymer (LCP), polytetrafluoroethylene (PTFE), polyetheretherketone (PEEK), polyphenylene oxide (PPO), and the like.
It is understood that the number of conductor layers in the first groove 101 can be set according to actual needs, and adjacent conductor layers are separated by an insulating layer.
Step S12, referring to fig. 12, performing circuit fabrication on the first copper foil layer 13 and the second copper foil layer 14 to form a first conductive circuit layer 131 and a second conductive circuit layer 141, so as to obtain the circuit substrate 100.
The first conductive trace layer 131 is connected to two sidewalls of the first conductor layer 22 in the first groove 101, and the second conductive trace layer 141 is connected to a bottom wall of the first conductor layer 22.
In this embodiment, the wiring is formed on the first copper foil layer 13 and the second copper foil layer 14 by an image transfer technique.
Referring to fig. 13a, in some embodiments, the circuit substrate 100 further includes a conductive layer 110 formed on exposed surfaces of at least two of the first conductive layer 22, the second conductive layer 42, and the third conductive layer 60 to connect the corresponding conductive layers. As shown in fig. 13a, the conductive layer 110 is formed on exposed surfaces of the first conductor layer 22, the first insulating layer 32, and the second conductor layer 42 to connect the first conductor layer 22 and the second conductor layer 42. As shown in fig. 13b, the conductive layer 110 is formed on the exposed surfaces of the second conductor layer 42, the second insulating layer 52, and the third conductor layer 60 to connect the second conductor layer 42 and the third conductor layer 60. As shown in fig. 13c, the conductive layer 110 is formed on exposed surfaces of the first conductor layer 22, the first insulating layer 32, the second conductor layer 42, the second insulating layer 52, and the third conductor layer 60 to connect the first conductor layer 22, the second conductor layer 42, and the third conductor layer 60.
In step S13, referring to fig. 14, a patterned metal layer 70 is formed on the surfaces of the first conductive trace layer 131, the first conductor layer 22, the second conductor layer 42, and the third conductor layer 60 away from the second conductive trace layer 141.
The patterned metal layer 70 includes a plurality of connection pads 71 disposed at intervals, and each connection pad 71 is disposed on the corresponding first conductive trace layer 131, the first conductive layer 22, the second conductive layer 42, and the third conductive layer 60. In this embodiment, the material of the metal layer 70 is tin.
In step S14, referring to fig. 15, an insulating material is filled in the line gap of the first conductive trace layer 131 and the gap between the adjacent connection pads 71 to form a third insulating layer 80, and a cover film 90 is covered on a side of the second conductive trace layer 141 away from the first conductive trace layer 131 to obtain a stacked structure 200. In this embodiment, the insulating material is filled in the line gap of the first conductive line layer 131 and the gap of the patterned metal layer 70 by a printing method.
The material of the third insulating layer 80 is selected from at least one of LCP, PTFE, PEEK, and PPO.
The cover film 90 includes an adhesive layer 91 and a cover layer 92 stacked together. The adhesive layer 91 covers the second conductive trace layer 141. The adhesive layer 91 is made of a common adhesive, and the covering layer is made of PET.
Step S15, please refer to fig. 16, providing another laminated structure 200, and butting the other laminated structure 200 to a side of the metal layer 70 away from the substrate layer 11 to obtain the circuit board 300. Two cover films 90 are located on the outside of the circuit board 100.
In the two stacked structures 200, the two first conductor layers 22 are located correspondingly and connected through the corresponding connection pads 71, the two second conductor layers 42 are located correspondingly and connected through the corresponding connection pads 71, and the two third conductor layers 60 are located correspondingly and connected through the corresponding connection pads 71, so as to form a "loop" type transmission line.
In some embodiments, the first conductor layer 22, the second conductor layer 42, and the third conductor layer 60 are coaxially disposed, the third conductor layer 60 is a high frequency transmission line, the second conductor layer 42 is a shielding layer, and the first conductor layer 22 is a transmission line or a power line. The two connected second conductor layers 42 are disposed around the two connected third conductor layers 60 to form a fully wrapped shield.
In other embodiments, the second conductor layer 42 is a transmission line, and the first conductor layer 22 is a shielding layer, so that two independent transmission lines are provided in the circuit board 300 without interfering with each other.
Referring to fig. 16 again, an embodiment of the present invention provides a circuit board 300, which includes two circuit substrates 100, and a metal layer 70 and a third insulating layer 80 disposed between the two circuit substrates 100.
Each circuit substrate 100 includes a base material layer 11, a first conductive line layer 131, a second conductive line layer 141, a first conductor layer 22, a first insulating layer 32, a second conductor layer 42, a second insulating layer 52, and a third conductor layer 60. The first conductive circuit layer 131 and the second conductive circuit layer 141 are respectively disposed on two opposite surfaces of the substrate layer 11. The circuit board 100 is provided with a first groove 101, the first groove 101 penetrates through the base material layer 11 and the first conductive circuit layer 131, and the second conductive circuit layer 141 is exposed from the first groove 101.
The first conductor layer 22 is disposed in the first groove 101 and connected to the first conductive trace layer 131 and the second conductive trace layer 141. The first conductive layer 22 has a second groove 21, and the first insulating layer 32 is disposed in the second groove 21. The first insulating layer 32 is formed with a third groove 31, and the second conductive layer 42 is disposed in the third groove 31. The second conductive layer 42 defines a fourth groove 41, and the second insulating layer 52 is disposed in the fourth groove 41. The second insulating layer 52 is formed with a fifth groove 51, and the third conductive layer 60 is disposed in the fifth groove 51.
In some embodiments, the first groove 101, the first conductor layer 22, the second groove 21, the first insulating layer 32, the third groove 31, the second conductor layer 42, the fourth groove 41, the second insulating layer 52, and the fifth groove 51 have a U-shaped cross section, and the third conductor layer 60 has a rectangular cross section.
The first conductor layer 22 has an exposed surface 221 exposed outside the circuit substrate 100, the first insulating layer 32 has an exposed surface 321 exposed outside the circuit substrate 100, the second conductor layer 42 has an exposed surface 421 exposed outside the circuit substrate 100, the second insulating layer 52 has an exposed surface 521 exposed outside the circuit substrate 100, and the third conductor layer 60 has an exposed surface 61 exposed outside the circuit substrate 100, wherein each exposed surface is flush with a surface of the first conductive trace layer 131 facing away from the base material layer 11.
The metal layer 70 includes a plurality of connection pads 71 disposed at intervals, and each connection pad 71 is disposed on exposed surfaces of the corresponding first conductive trace layer 131, the first conductor layer 22, the second conductor layer 42, and the third conductor layer 60.
The third insulating layer 80 is filled in the line gap of the first conductive line layer 131 and the gap between the adjacent connection pads 71.
In the two circuit substrates 100, the two first conductor layers 22 are correspondingly positioned and connected through the corresponding connection pads 71, the two second conductor layers 42 are correspondingly positioned and connected through the corresponding connection pads 71, and the two third conductor layers 60 are correspondingly positioned and connected through the corresponding connection pads 71, so that a loop-shaped transmission line is formed.
The opposite surfaces of the circuit board 300 are provided with cover films 90. The cover film 90 includes an adhesive layer 91 and a cover layer 92 stacked together. The adhesive layer 91 covers the second conductive trace layer 141. The adhesive layer 91 is made of a common adhesive, and the covering layer is made of PET.
According to the circuit board 300 and the manufacturing method thereof provided by the application, the first groove 101 is formed in the double-sided circuit substrate, and the plurality of conductor layers are arranged in the first groove 101, so that the double-sided circuit substrate has the effects of a plurality of layers of circuit substrates, the thickness of the circuit substrate is reduced, and thinning is facilitated.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention.

Claims (10)

1. The utility model provides a circuit board, its characterized in that, includes circuit substrate, circuit substrate includes substrate layer, first conducting wire layer, second conducting wire layer, first conductor layer, first insulating layer and second conductor layer, first conducting wire layer with second conducting wire layer set up in the two surfaces that the substrate layer is relative, circuit substrate is equipped with and link up the substrate layer with the first recess on first conducting wire layer, second conducting wire layer is followed first recess exposes, first conductor layer set up in the first recess and with first conducting wire layer with second conducting wire layer is connected, the second recess has been seted up to first conductor layer, first insulating layer set up in the second recess and seted up the third recess, the second conductor layer set up in the third recess.
2. The circuit board of claim 1, further comprising a second insulating layer and a third conductor layer, wherein the second conductor layer defines a fourth groove, the second insulating layer is disposed in the fourth groove and defines a fifth groove, and the third conductor layer is disposed in the fifth groove.
3. The circuit board according to claim 2, wherein the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, and the third conductor layer each have an exposed surface exposed outside the circuit substrate, and each exposed surface is flush with a surface of the first conductive line layer facing away from the base material layer.
4. The circuit board of claim 2, wherein the first conductor layer and the second conductor layer are both U-shaped in cross-section, and the third conductor layer is rectangular in cross-section.
5. The circuit board of claim 2, wherein exposed surfaces of at least two of the first conductor layer, the second conductor layer, and the third conductor layer are provided with a conductive layer.
6. The circuit board according to claim 2, wherein the circuit board comprises two circuit substrates arranged in a stacked manner, and two first conductor layers, two second conductor layers and two third conductor layers of the two circuit substrates are respectively connected.
7. The circuit board of claim 6, further comprising a metal layer disposed between the two circuit substrates, the two first conductor layers, the two second conductor layers, and the two third conductor layers each being connected by the metal layer.
8. The circuit board of claim 1, wherein a surface of the second conductive trace layer facing away from the substrate layer is provided with a coverlay.
9. A method of manufacturing a circuit board according to any one of claims 1 to 8, comprising the steps of:
providing a double-sided copper-clad plate, wherein the double-sided copper-clad plate comprises a base material layer, and a first copper foil layer and a second copper foil layer which are arranged on two opposite surfaces of the base material layer;
forming a first groove on the double-sided copper-clad plate, wherein the first groove penetrates through the substrate layer and the first copper foil layer, and part of the second copper foil layer is exposed out of the first groove;
filling a first conductive material in the first groove, and removing part of the first conductive material to form a second groove to obtain a first conductor layer;
filling a first insulating material in the second groove, and removing part of the first insulating material to form a third groove to obtain a first insulating layer;
filling a second conductive material in the third groove, and removing part of the second conductive material to form a fourth groove to obtain a second conductor layer;
filling a second insulating material in the fourth groove, and removing part of the second insulating material to form a fifth groove to obtain a second insulating layer;
filling a third conductive material in the fifth groove to obtain a third conductor layer;
and carrying out circuit manufacturing on the first copper foil layer and the second copper foil layer to form a first conductive circuit layer and a second conductive circuit layer, so as to obtain the circuit substrate.
10. The method of manufacturing of claim 9, further comprising the steps of:
and butting the two circuit substrates together, wherein the two first conductor layers, the two first insulating layers, the two second conductor layers, the two second insulating layers and the two third conductor layers are respectively connected.
CN202110594647.1A 2021-05-28 2021-05-28 Circuit board and manufacturing method thereof Pending CN115413109A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110594647.1A CN115413109A (en) 2021-05-28 2021-05-28 Circuit board and manufacturing method thereof
TW110119908A TWI819313B (en) 2021-05-28 2021-06-01 Circuit board and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110594647.1A CN115413109A (en) 2021-05-28 2021-05-28 Circuit board and manufacturing method thereof

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Publication Number Publication Date
CN115413109A true CN115413109A (en) 2022-11-29

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Application Number Title Priority Date Filing Date
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TW (1) TWI819313B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5724468B2 (en) * 2011-03-07 2015-05-27 宇部興産株式会社 Method for producing polyimide metal laminate
JP7448309B2 (en) * 2018-11-27 2024-03-12 日東電工株式会社 Wired circuit board and its manufacturing method

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TW202247731A (en) 2022-12-01

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