CN113747655B

CN113747655B - Circuit board and manufacturing method thereof

Info

Publication number: CN113747655B
Application number: CN202010470380.0A
Authority: CN
Inventors: 彭满芝
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2023-05-23
Anticipated expiration: 2040-05-28
Also published as: CN113747655A

Abstract

The application provides a circuit board, include: the middle layer comprises a through hole and a conductive block, wherein the through hole penetrates through the middle layer, and the conductive block is arranged in the through hole; a first circuit layer including a first conductive line including a plurality of first etched pillars protruding toward the same side; a second circuit layer, wherein the first circuit layer comprises a second conductive circuit, and the second conductive circuit comprises a plurality of second etched columns protruding towards the same side; the first circuit layer and the second circuit layer are respectively arranged on two opposite sides of the middle layer, and the first etching column and the second etching column are electrically connected with the conductive block. The application also provides a manufacturing method of the circuit board.

Description

Circuit board and manufacturing method thereof

Technical Field

The application relates to the technical field of circuit boards, in particular to a circuit board and a manufacturing method thereof.

Background

In recent years, electronic products are widely used in daily work and life, and light, thin, and small electronic products are becoming popular. The wiring board as a main component of the electronic product is a popular direction of research by those skilled in the art.

In the existing circuit board, especially in the multilayer circuit board, the conduction between different circuit layers needs to be realized through conducting holes, and the conducting holes are often manufactured through mechanical drilling and laser etching, and then the conducting holes are manufactured through electroplating in the conducting holes. In the process of plating copper on the plated holes, a new conducting medium is needed, and the quality problems of many plated holes, such as hole size, hollowness, broken holes, uneven plating and the like, can not be solved, and the problems of poor conduction and the like and the reliability can be solved. And when the number of the circuit board layers is large, the difficulty of manufacturing the via holes is large, the process is complex, and the transverse-longitudinal ratio of the product is limited.

How to solve the above problems is considered by those skilled in the art.

Disclosure of Invention

In view of this, the present application provides a circuit board, including:

the middle layer comprises a through hole and a conductive block, wherein the through hole penetrates through the middle layer, and the conductive block is arranged in the through hole;

a first circuit layer including a first conductive line including a plurality of first etched pillars protruding toward the same side, a thickness of the first medium being smaller than a height of the first etched pillars;

the first circuit layer comprises a second conductive circuit, the second conductive circuit comprises a plurality of second etched columns protruding towards the same side, and the thickness of the second medium is smaller than the height of the second etched columns; and

the first circuit layer and the second circuit layer are respectively arranged on two opposite sides of the middle layer, the first etching column and the second etching column are electrically connected with the conductive block, the width of the end part of the first etching column, which is contacted with the conductive block, is smaller than that of the conductive block, and the width of the end part of the second etching column, which is contacted with the conductive block, is smaller than that of the conductive block.

In an embodiment, the first circuit layer includes a first surface and a second surface opposite to each other, the first etching columns extend convexly in a direction away from the second surface, and the number of the first etching columns is a plurality of first etching columns;

the second circuit layer comprises a third surface and a fourth surface which are opposite to each other, the second etched columns extend convexly in a direction away from the fourth surface, and the number of the second etched columns is a plurality of second etched columns; and

the middle layer comprises a fifth surface and a sixth surface which are opposite to each other, the first surface is opposite to the fifth surface, and the third surface is opposite to the sixth surface.

In one embodiment, the first medium encapsulates at least a portion of the first etched pillars, the first medium being in contact with the intermediate layer; and

the second medium encapsulates at least a portion of the second etched pillars, the second medium in contact with the intermediate layer.

In an embodiment, the first etching column comprises a first end and a second end which are opposite to each other, the first end is far away from the second surface, the second end is close to the second surface, and the width of the first end is smaller than that of the second end;

the second etching column comprises a third end part and a fourth end part which are opposite, the third end part is far away from the fourth surface, the fourth end part is close to the fourth surface, and the width of the third end part is smaller than that of the fourth end part; and

the conductive block comprises a fifth end and a sixth end which are opposite, wherein the fifth end is adjacent to the fifth surface, the sixth end is adjacent to the sixth surface, the fifth end is in contact with the first end, the width of the fifth end is larger than that of the first end, the sixth end is in contact with the third end, and the width of the sixth end is larger than that of the third end.

In an embodiment, the circuit board further includes a protection layer, the protection layer is disposed on an outermost side of the circuit board, at least a portion of the first medium and the second medium is covered by the protection layer, and at least a portion of the first conductive circuit and the second conductive circuit is covered by the protection layer.

The application also provides a manufacturing method of the circuit board, which comprises the following steps:

providing a first copper layer, and processing the first copper layer by using an image transfer process to obtain a first conductive circuit, wherein the first conductive circuit comprises a plurality of first etching columns protruding towards the same side;

a first medium is arranged on one side of the first conductive circuit, on which the first etching column is arranged, so that the thickness of the first medium is smaller than the height of the first etching column, and a first circuit layer is obtained;

providing a second copper layer, and processing the second copper layer by using an image transfer process to obtain a second conductive circuit, wherein the second conductive circuit comprises a plurality of second etching columns protruding towards the same side;

setting a second medium on one side of the second conductive circuit, on which the second etching column is arranged, so that the thickness of the second medium is smaller than the height of the second etching column, and obtaining a second circuit layer;

providing an intermediate layer, and forming a plurality of through holes penetrating through the intermediate layer on the intermediate layer;

filling conductive paste into the through holes to form conductive blocks; and

and sequentially laminating and pressing the first circuit layer, the middle layer and the second circuit layer, so that the first etching column and the second etching column are electrically connected with the conductive block, the width of the end part of the first etching column, which is in contact with the conductive block, is smaller than that of the conductive block, and the width of the end part of the second etching column, which is in contact with the conductive block, is smaller than that of the conductive block.

In one embodiment, the first copper layer includes a first surface and a second surface opposite to each other, and the first surface is etched by an image transfer process to obtain the first etched pillars;

the second copper layer comprises a third surface and a fourth surface which are opposite to each other, and the third surface is etched through an image transfer process to obtain the second etched column;

the middle layer comprises a fifth surface and a sixth surface which are opposite to each other, and before lamination, the first surface and the fifth surface are opposite to each other, and the third surface and the sixth surface are opposite to each other; and

and pressing the first circuit layer, the middle layer and the second circuit layer to enable at least one first etching column and at least one second etching column to be electrically connected through at least one conductive block.

In an embodiment, the thickness of the first medium is smaller than the height of the first etched pillars in a direction perpendicular to the second surface; and

the thickness of the second medium is smaller than the height of the second etched pillars in a direction perpendicular to the fourth surface.

In an embodiment, the first etching column comprises a first end and a second end which are opposite, the first end is far away from the second surface, and the width of the first end is smaller than that of the second end;

the second etching column comprises a third end part and a fourth end part which are opposite, the third end part is far away from the fourth surface, and the width of the third end part is smaller than that of the fourth end part;

In one embodiment, the method further comprises the following steps:

patterning the second surface by using an image transfer process to expose at least part of the first medium;

patterning the fourth surface by using an image transfer process to expose at least part of the second medium; and

and carrying out surface treatment to obtain a protective layer, wherein at least part of the first medium and the second medium is covered by the protective layer, and at least part of the first conductive circuit and the second conductive circuit is covered by the protective layer.

Compared with the prior art, the circuit board has the advantages that the conductive block is formed by the etching process and the conductive paste hole plugging process, so that the copper plating process is reduced, and the problems of hollowness, hole breakage, uneven electroplating and the like are avoided; the height between the whole conducting holes of the circuit board is increased in a conducting paste hole plugging mode, so that a product with a high aspect ratio is achieved; the conductive paste plug hole layer is arranged on the middle layer to serve as a transition structure, so that partial circuits can be formed, and the complexity of interlayer conduction of the circuit board is reduced.

Drawings

Fig. 1 is a schematic cross-sectional view of a circuit board according to a first embodiment of the present application.

Fig. 2 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 3 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 4 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 5 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 6 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 7 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 8 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 9 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 10 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 11 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 12 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 13 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 14 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 15 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 16 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 17 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 18 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 19 is a schematic view of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 20 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 21 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Fig. 22 is a schematic diagram of a preparation flow of a circuit board according to a first embodiment of the present application.

Description of the main reference signs

Circuit board 1

Intermediate layer 10

Base layer 101

Through hole 102

Conductive block 103

Fifth end 1035

Sixth end 1036

Fifth surface 105

Sixth surface 106

First circuit layer 11

First conductive line 110

First etched column 1100

First end 1101

Second end 1102

First surface 111

Second surface 112

First medium 115

Second circuit layer 12

Second conductive line 120

Second etched column 1200

Third end 1203

Fourth end 1204

Third surface 123

Fourth surface 124

Second medium 125

Protective layer 13

First copper layer 21

Second copper layer 22

First photoresist 231

Second photoresist 232

Third Photoresist 233

Fourth photoresist 234

Fifth photoresist 235

Sixth photoresist 236

The following detailed description will further illustrate the application in conjunction with the above-described figures.

Detailed Description

The following description will refer to the accompanying drawings in order to more fully describe the present application. Exemplary embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals designate identical or similar components.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, "comprises" and/or "comprising" or "includes" and/or "including" or "having" and/or "has", integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless the context clearly defines otherwise, terms such as those defined in a general dictionary should be construed to have meanings consistent with their meanings in the relevant art and the present application, and should not be construed as idealized or overly formal meanings.

The following description of exemplary embodiments will be provided with reference to the accompanying drawings. It is noted that the components depicted in the referenced figures are not necessarily shown to scale; and the same or similar components will be given the same or similar reference numerals or similar technical terms.

The following detailed description of specific embodiments of the present application refers to the accompanying drawings.

As shown in fig. 1, the present application provides a circuit board 1, where the circuit board 1 includes an intermediate layer 10, a first circuit layer 11, a second circuit layer 12, and a protective layer 13. The first circuit layer 11 and the second circuit layer 12 are disposed on two opposite sides of the intermediate layer 10, at least a portion of the protection layer 13 is disposed on a surface of the first circuit layer 11 away from the intermediate layer 10, and at least a portion of the protection layer 13 is disposed on a surface of the second circuit layer 12 away from the intermediate layer 10.

The intermediate layer 10 includes a base layer 101, a through hole 102, and a conductive block 103. The number of the through holes 102 penetrating the base layer 101 of the intermediate layer 10 may be plural, and the plural through holes 102 may be arranged at intervals. The conductive block 103 is disposed in the through hole 102, and in one embodiment, the conductive block 103 is formed by a conductive paste filled in the through hole 102, and the conductive paste may be copper paste, silver paste or tin paste.

In one embodiment, the intermediate layer 10 includes a fifth surface 105 and a sixth surface 106 opposite to each other, the conductive block 103 includes a fifth end 1035 and a sixth end 1036 opposite to each other, the fifth end 1035 is adjacent to the fifth surface 105, and the sixth end 1036 is adjacent to the sixth surface 106. The thickness of the conductive block 103 is greater than the thickness of the base layer 101, i.e., the fifth end 1035 is higher than the fifth surface 105 and the sixth end 1036 is higher than the sixth surface 106.

In one embodiment, the intermediate layer 10 may include a plurality of circuit layers stacked together, i.e., the base layer 101 may be a multi-layer circuit substrate. In this embodiment, the base layer 101 may be a single layer of organic material, for example, epoxy, polyimide, or polyethylene, and the through holes 102 penetrate the single layer of base layer 101. In one embodiment, the material of the base layer 101 may be at least one of epoxy or polypropylene (PP).

The first circuit layer 11 includes a first conductive circuit 110, where the first conductive circuit 110 includes a plurality of first etched columns 1100 protruding toward the same side, and the first etched columns 1100 are electrically connected to the conductive blocks 103. The first circuit layer 11 includes a first surface 111 and a second surface 112 opposite to each other, and the first surface 111 is disposed opposite to the fifth surface 105.

In an embodiment, the first etching columns 1100 extend convexly away from the second surface 112, and the number of the first etching columns 1100 may be plural. The first etched column 1100 includes a first end 1101 and a second end 1102 opposite to each other, the first end 1101 being distant from the second surface 112, the second end 1102 being close to the second surface 112, the width of the first end 1101 being smaller than the width of the second end 1102. In one embodiment, the fifth end 1035 is in contact with and electrically connected to the first end 1101, and the width of the fifth end 1035 is greater than the width of the first end 1101.

The first circuit layer 11 further includes a first dielectric 115, the first dielectric 115 surrounding at least a portion of the first etched pillars 1100, the first dielectric 115 being in contact with the intermediate layer 10, the thickness of the first dielectric 115 being less than the height of the first etched pillars 1100. In an embodiment, the material of the first medium 115 may be at least one of ABF (Ajinomoto Build-up Film), liquid crystal polymer (Liquid Crystal Polymer, LCP), polyimide (PI), polypropylene (PP).

The second circuit layer 12 includes a second conductive circuit 120, where the second conductive circuit 120 includes a plurality of second etched pillars 1200 protruding toward the same side, and the second etched pillars 1200 are electrically connected to the conductive blocks 103. The second circuit layer 12 includes a third surface 123 and a fourth surface 124 opposite to each other, and the third surface 123 is disposed opposite to the sixth surface 116.

In one embodiment, the second etching pillars 1200 extend convexly away from the fourth surface 124, and the number of the second etching pillars 1200 is plural. The second etching pillar 1200 includes a third end 1203 and a fourth end 1204 opposite to each other, the third end 1203 being disposed away from the fourth surface 124, the fourth end 1204 being close to the fourth surface 124, the third end 1203 having a width smaller than the fourth end 1204. In one embodiment, the sixth end 1036 is in contact with and electrically connected to the third end 1203, and the width of the sixth end 1036 is greater than the width of the third end 1203.

The second circuit layer 12 further includes a second dielectric 125, the second dielectric 125 surrounding at least a portion of the second etched pillars 1200, the second dielectric 125 in contact with the intermediate layer 10, the second dielectric 125 having a thickness less than the height of the second etched pillars 1200. In an embodiment, the material of the second medium 125 may be at least one of ABF (Ajinomoto Build-up Film), liquid crystal polymer (Liquid Crystal Polymer, LCP), polyimide (PI), polypropylene (PP).

In one embodiment, two ends of the conductive block 103 are respectively and simultaneously electrically connected to a first etching pillar 1100 and a second etching pillar 1200.

The circuit board 1 further includes a protective layer 13, where the protective layer 13 is disposed on the outermost side of the circuit board 1, at least portions of the first medium 115 and the second medium 125 are covered by the protective layer 13, and at least portions of the first conductive trace 110 and the second conductive trace 120 are covered by the protective layer 13.

The application also provides a manufacturing method of the circuit board 1, which comprises the following steps:

step S1: as shown in fig. 2 to 7, a first copper layer 21 is provided, and the first copper layer 21 is processed by an image transfer process to obtain a first conductive circuit 110, such that the first conductive circuit 110 includes a plurality of first etched pillars 1100 protruding toward the same side; a first dielectric 115 is disposed on the side of the first conductive trace 110 where the first etched pillar 1100 is disposed, resulting in a first trace layer 11.

In one embodiment, the method specifically includes the following steps:

step S11: as shown in fig. 2, a first copper layer 21 is provided, and the first copper layer 21 includes a first surface 111 and a second surface 112 opposite to each other; in other embodiments, the first copper layer 21 may be made of other conductive materials.

Step S12: as shown in fig. 3, a first photoresist 231 and a second photoresist 232 are respectively disposed on two opposite surfaces of the first copper layer 21.

Step S13: as shown in fig. 4 and 5, the first photoresist 231 is exposed to light, and the first conductive traces 110 and the first etched pillars 1100 are obtained by developing, transferring images, and etching. The first etched column 1100 is made to include a first end 1101 and a second end 1102 opposite to each other, the first end 1101 being disposed away from the second surface 112, the first end 1101 having a width smaller than the second end 1102.

Step S14: as shown in fig. 6 and 7, the first photoresist 231 and the second photoresist 232 are removed, and the first dielectric 115 is pressed on the side of the first conductive trace 110 where the first etched pillar 1100 is disposed, so as to obtain the first trace layer 11. In one embodiment, the thickness of the first medium 115 is less than the height of the first etched pillars 1100 in a direction perpendicular to the second surface 112.

Step S2: as shown in fig. 8 to 13, a second copper layer 22 is provided, and the second copper layer 22 is processed by using an image transfer process to obtain a second conductive circuit 120, so that the second conductive circuit 120 includes a plurality of second etched pillars 1200 protruding towards the same side; the second dielectric 125 is disposed on the side of the second conductive trace 120 where the second etched pillar 1200 is disposed, resulting in the second trace layer 12.

In one embodiment, the method specifically includes the following steps:

step S21: as shown in fig. 8, a second copper layer 22 is provided, and the second copper layer 22 includes a third surface 123 and a fourth surface 124 opposite to each other; in other embodiments, the second copper layer 22 may be made of other conductive materials.

Step S22: as shown in fig. 9, a third photoresist 233 and a fourth photoresist 234 are respectively disposed on the opposite surfaces of the first copper layer 21.

Step S23: as shown in fig. 10 and 11, the first photoresist 231 is exposed to light, and the second conductive line 120 and the second etched pillar 1200 are obtained by developing, imaging and etching. The second etched pillar 1200 includes a third end 1203 and a fourth end 1204 opposite to each other, the third end 1203 being disposed away from the fourth surface 124, the third end 1203 having a width smaller than the fourth end 1204.

Step S24: as shown in fig. 12 and 13, the third photoresist 233 and the fourth photoresist 234 are removed, and the second medium 125 is pressed on the side of the second conductive trace 120 where the second etching pillar 1200 is provided, thereby obtaining the second trace layer 12. In one embodiment, the thickness of the second medium 125 is less than the height of the second etched pillars 1200 in a direction perpendicular to the fourth surface 124.

Step S3: as shown in fig. 14 to 16, an intermediate layer 10 is provided, a plurality of through holes 102 penetrating the intermediate layer 10 are formed in the intermediate layer 10, and conductive blocks 103 are formed by filling conductive paste in the through holes 102. The intermediate layer 10 includes a fifth surface 105 and a sixth surface 106 that are opposite such that the conductive block 103 includes a fifth end 1035 and a sixth end 1036 that are opposite, the fifth end 1035 being adjacent to the fifth surface 105 and the sixth end 1036 being adjacent to the sixth surface 106.

In one embodiment, the method specifically includes the following steps:

step S31: as shown in fig. 14 and 15, an intermediate layer 10 is provided, the intermediate layer 10 includes a fifth surface 105 and a sixth surface 106 opposite to each other, and a plurality of through holes 102 penetrating the intermediate layer 10 are formed in the intermediate layer 10.

Step S32: as shown in fig. 16, the conductive paste is filled in the through hole 102 to form the conductive block 103, and the conductive block 103 includes a fifth end portion 1035 and a sixth end portion 1036 which are opposite to each other, the fifth end portion 1035 being adjacent to the fifth surface 105, and the sixth end portion 1036 being adjacent to the sixth surface 106. In one embodiment, the conductive paste may be copper paste, silver paste or tin paste.

Step S4: as shown in fig. 17 to 18, the first wiring layer 11, the intermediate layer 10, and the second wiring layer 12 are laminated in this order, and the first etching columns 1100 and the second etching columns 1200 are electrically connected to the conductive block 103.

In one embodiment, before lamination, the first surface 111 is disposed opposite to the fifth surface 105, the third surface 123 is disposed opposite to the sixth surface 106, and then the first circuit layer 11, the intermediate layer 10 and the second circuit layer 12 are laminated, so that the at least one first etching pillar 1100 and the at least one second etching pillar 1200 are electrically connected through the at least one conductive bump 103.

In one embodiment, the fifth end 1035 contacts the first end 1101, the width of the fifth end 1035 is greater than the width of the first end 1101, the sixth end 1036 contacts the third end 1203, and the width of the sixth end 1036 is greater than the width of the third end 1203.

Step S5: as shown in fig. 19 to 22, the second surface 112 is patterned by using an image transfer process, so that at least a portion of the first medium 115 is exposed; patterning the fourth surface 124 using an image transfer process to expose at least a portion of the second medium 125; the surface treatment is performed to obtain the protective layer 13, so that at least part of the first medium 115 and the second medium 125 is covered by the protective layer 13, and at least part of the first conductive line 110 and the second conductive line 120 is covered by the protective layer 13.

In one embodiment, the method specifically includes the following steps:

step S51: as shown in fig. 19, a fifth photoresist 235 and a sixth photoresist 236 are respectively provided on the opposite surfaces of the intermediate layer 10.

Step S52: as shown in fig. 20 and 21, the fifth photoresist 235 is exposed and patterned by an image transfer process to obtain a patterned conductive line, and at least a portion of the first medium 115 is exposed; exposing the sixth photoresist 236 and patterning the sixth photoresist using an image transfer process to form a patterned conductive trace and expose at least a portion of the second medium 125; and the fifth photoresist 235 and the sixth photoresist 236 are removed.

Step S53: as shown in fig. 22, the surface treatment is performed to obtain the protective layer 13, so that at least part of the first medium 115 and the second medium 125 is covered with the protective layer 13, and at least part of the first conductive trace 110 and the second conductive trace 120 is covered with the protective layer 13.

Hereinabove, the specific embodiments of the present application are described with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that various changes and substitutions can be made in the specific embodiments of the present application without departing from the spirit and scope of the present application. Such modifications and substitutions are intended to be within the scope of the present application.

Claims

1. A wiring board, comprising:

the middle layer comprises a through hole and a conductive block, the through hole penetrates through the middle layer, the conductive block is arranged in the through hole, and the middle layer comprises a fifth surface and a sixth surface which are opposite;

the first circuit layer comprises a first conductive circuit and a first medium, the first conductive circuit comprises a plurality of first etched columns protruding towards the same side, the thickness of the first medium is smaller than the height of the first etched columns, the first circuit layer comprises a first surface and a second surface which are opposite, the first surface and the fifth surface are opposite, the first etched columns protrude towards a direction away from the second surface and extend, and the number of the first etched columns is multiple;

the first circuit layer comprises a second conductive circuit and a second medium, the second conductive circuit comprises a plurality of second etching columns protruding towards the same side, the thickness of the second medium is smaller than the height of the second etching columns, the second circuit layer comprises a third surface and a fourth surface which are opposite, the third surface and the sixth surface are opposite, the second etching columns protrude towards a direction away from the fourth surface and extend, and the number of the second etching columns is multiple; and

2. The circuit board of claim 1, wherein:

the first medium wraps at least part of the first etching column, and the first medium is in contact with the intermediate layer; and

3. The circuit board of claim 1, wherein:

the first etching column comprises a first end part and a second end part which are opposite, the first end part is far away from the second surface, the second end part is close to the second surface, and the width of the first end part is smaller than that of the second end part;

4. The circuit board of claim 2, further comprising a protective layer disposed outermost of the circuit board, at least a portion of the first medium and the second medium being covered by the protective layer, at least a portion of the first conductive trace and the second conductive trace being covered by the protective layer.

5. The manufacturing method of the circuit board is characterized by comprising the following steps:

providing a first copper layer, processing the first copper layer by using an image transfer process to obtain a first conductive circuit, enabling the first conductive circuit to comprise a plurality of first etching columns protruding towards the same side, enabling the first copper layer to comprise a first surface and a second surface which are opposite, and etching the first surface by using the image transfer process to obtain the first etching columns;

providing a second copper layer, processing the second copper layer by using an image transfer process to obtain a second conductive circuit, enabling the second conductive circuit to comprise a plurality of second etching columns protruding towards the same side, enabling the second copper layer to comprise a third surface and a fourth surface which are opposite, and etching the third surface by using the image transfer process to obtain the second etching columns;

providing an intermediate layer, forming a plurality of through holes penetrating through the intermediate layer on the intermediate layer, wherein the intermediate layer comprises a fifth surface and a sixth surface which are opposite;

filling conductive paste into the through holes to form conductive blocks; and

before lamination, the first surface and the fifth surface are arranged opposite to each other, the third surface and the sixth surface are arranged opposite to each other, the first circuit layer, the middle layer and the second circuit layer are laminated and laminated in sequence, the first etching column and the second etching column are electrically connected with the conductive block, the width of the end part of the first etching column, which is in contact with the conductive block, is smaller than that of the conductive block, and the width of the end part of the second etching column, which is in contact with the conductive block, is smaller than that of the conductive block.

6. The method for manufacturing a circuit board according to claim 5, wherein,

the thickness of the first medium is smaller than the height of the first etched column in the direction perpendicular to the second surface; and

7. The method for manufacturing a circuit board according to claim 5, wherein,

the first etching column comprises a first end and a second end which are opposite to each other, the first end is arranged far away from the second surface, and the width of the first end is smaller than that of the second end;

8. The method of manufacturing a circuit board according to claim 5, further comprising the steps of: