CN115407821B - Circuit with strong anti-interference capability - Google Patents

Circuit with strong anti-interference capability Download PDF

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CN115407821B
CN115407821B CN202211352918.3A CN202211352918A CN115407821B CN 115407821 B CN115407821 B CN 115407821B CN 202211352918 A CN202211352918 A CN 202211352918A CN 115407821 B CN115407821 B CN 115407821B
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triode
circuit
transistor
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CN115407821A (en
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Suzhou Baker Microelectronics Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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Abstract

This application includes the strong circuit of an interference killing feature, concretely relates to battery powered technology field. In the circuit, a power supply voltage end is grounded through a first branch of a first current mirror and a first branch of a second current mirror in sequence; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage end is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor in sequence; the emitter of the first triode is grounded; the collector of the first triode is connected with the base of at least one output triode; the application circuit in the circuit comprises at least one output terminal; the output end is grounded through the output triode and the target resistor in sequence. The circuit provides stable current which is not influenced by external interference for other application circuits in the integrated circuit control chip in the battery power supply circuit, and improves the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit.

Description

Circuit with strong anti-interference capability
Technical Field
The invention relates to the technical field of battery power supply, in particular to a circuit with strong anti-interference capability.
Background
The battery charging circuit is typically comprised of a power loop and a control loop.
In a battery-powered circuit, the control loop usually includes an integrated circuit control chip, and the interference rejection capability of the prior art integrated circuit control chip, especially the interference rejection capability of the current source in the chip, is poor. Therefore, when the battery power supply circuit suffers from external interference, a current error output by a current source inside the integrated circuit control chip is usually large, so that the control accuracy of the integrated circuit control chip is affected, and the output accuracy of the battery power supply circuit is reduced.
Disclosure of Invention
The embodiment of the application provides a circuit with strong anti-interference capability, which improves the control precision of an integrated circuit control chip and the output precision of a battery power supply circuit, and the circuit comprises an application circuit and a current source circuit;
in the current source circuit, a power supply voltage terminal VCC is grounded through a first branch of a first current mirror and a first branch of a second current mirror in sequence;
the power supply voltage end VCC is grounded through a second branch of the first current mirror, a second branch of the second current mirror and a second resistor R2 in sequence;
the power supply voltage end VCC is also connected to a collector electrode of the first triode through a third branch of the first current mirror and the first resistor R1 in sequence; the emitting electrode of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through the first resistor R1;
the collector electrode of the first triode Q1 is connected with the base electrode of at least one output triode;
the application circuit comprises at least one output terminal; the output end is grounded through the output triode and the target resistor in sequence.
In a possible implementation manner, the first branch of the first current mirror includes a fifth triode Q5, and the first branch of the second current mirror includes an eighth triode Q8;
and the power supply voltage terminal VCC is grounded through a fifth triode Q5 and an eighth triode Q8 in sequence.
In a possible implementation manner, the second branch of the first current mirror includes a sixth transistor Q6, and the second branch of the second current mirror includes a ninth transistor Q9;
and the power supply voltage end VCC is grounded through a sixth triode Q6, a ninth triode Q9 and a second resistor R2 in sequence.
In one possible implementation manner, the third branch of the first current mirror includes a seventh transistor Q7;
and the power supply voltage end VCC is connected to the collector electrode of the first triode Q1 sequentially through a seventh triode Q7 and a first resistor R1.
In one possible implementation, the eighth transistor Q8 is formed by at least one target transistor; the ninth transistor Q9 is formed of at least one target transistor.
In one possible implementation manner, the ratio of the target transistor in the eighth transistor Q8 to the target transistor in the ninth transistor Q9 is N, and N > 1.
In one possible implementation, the target transistor is an NPN transistor; the fifth triode Q5, the sixth triode Q6 and the seventh triode Q7 are respectively composed of at least one PNP triode; the first triode Q1 is composed of at least one NPN triode;
the number of PNP triodes respectively included in the fifth triode Q5, the sixth triode Q6, and the seventh triode Q7 is equal to the number of target triodes included in the eighth triode Q8;
the number of the NPN triodes contained in the first triode Q1 is equal to the number of the target triodes contained in the eighth triode Q8.
In one possible implementation, the parameters of the output transistor are the same as the parameters of the ninth transistor Q9.
In one possible implementation, the output terminal of the application circuit includes a first output terminal and a second output terminal;
in the application circuit, the power supply voltage terminal VCC is connected to the first output terminal through a first branch of a third current mirror and a thirteenth polar tube Q10 in sequence; the power supply voltage terminal VCC is connected to the first output terminal through a second branch of the third current mirror and an eleventh triode Q11 in sequence;
the power supply voltage end VCC is further connected to a base electrode of a fourteenth triode Q14 through a second branch of the third current mirror in sequence;
the power supply voltage terminal VCC is further connected to the second output terminal of the application circuit through the fourteenth triode Q14.
In a possible implementation manner, the application circuit is a comparator circuit, and the base of the thirteenth triode Q10 and the base of the eleventh triode Q11 are respectively connected to voltage signals to be compared.
In one possible implementation, the output transistor includes a second transistor Q2 and a third transistor Q3; the target resistor comprises a third resistor R3 and a fourth resistor R4;
the first output end is grounded through the second triode Q2 and the third resistor R3 in sequence;
the second output end is grounded through the third triode Q3 and the fourth resistor R4 in sequence.
In a possible implementation manner, the first branch of the third current mirror includes a twelfth triode Q12; the second branch of the third current mirror comprises a thirteenth triode Q13;
the power supply voltage terminal VCC is connected to the first output terminal through the twelfth triode Q12 and the thirteenth triode Q10 in sequence;
the power supply voltage terminal VCC is connected to the first output terminal through the thirteenth triode Q13 and the eleventh triode Q11 in sequence.
In one possible implementation, the thirteenth diode Q10 and the eleventh diode Q11 are respectively formed by at least one NPN transistor; and the number of NPN triodes included in the thirteenth triode Q10 and the eleventh triode Q11 is equal to the number of target triodes included in the eighth triode Q8.
In one possible implementation manner, the twelfth transistor Q12 and the thirteenth transistor Q13 are respectively formed by at least one PNP transistor; and the number of PNP triodes respectively included in the twelfth triode Q12 and the thirteenth triode Q13 is equal to the number of target triodes included in the eighth triode Q8.
In a possible implementation manner, the fourteenth transistor Q14 is formed by connecting at least two PNP transistors in parallel; and the number of PNP triodes included in the fourteenth triode Q14 is twice the number of target triodes included in the eighth triode Q8.
In one possible implementation, the output of the application circuit comprises a third output;
in the application circuit, a power supply voltage end is connected to the third output end through a first branch of a fourth current mirror;
the power supply voltage end is connected to the voltage output end of the application circuit through a second branch of the fourth current mirror;
the voltage output end is grounded through a sixth resistor R6 and a seventeenth triode Q17 in sequence.
In one possible implementation, the first branch of the fourth current mirror includes a fifteenth transistor Q15; the second branch of the fourth current mirror comprises a sixteenth triode Q16;
the power supply voltage terminal VCC is connected to the third output terminal through the fifteenth triode Q15;
and the power supply voltage terminal VCC is connected to the voltage output terminal of the application circuit through a sixteenth triode Q16.
In a possible implementation manner, the fifteenth transistor Q15, the sixteenth transistor Q16, and the seventeenth transistor Q17 are respectively composed of at least one PNP transistor;
the number of PNP triodes included in the fifteenth triode Q15, the sixteenth triode Q16, and the seventeenth triode Q17 is equal to the number of target triodes included in the eighth triode Q8.
In one possible implementation, the output of the application circuit comprises a fourth output;
the power supply voltage terminal VCC is connected to the fourth output terminal through an eighteenth triode Q18 and a seventh resistor R7;
the fourth output end is an output voltage end of the application circuit.
In one possible implementation, the eighteenth triode Q18 is formed by at least one PNP triode; the number of PNP triodes included in the eighteenth triode Q18 is equal to the number of target triodes included in the eighth triode Q8.
The technical scheme provided by the application can comprise the following beneficial effects:
in the circuit related to the application, the circuit is divided into an application circuit and a current source circuit, wherein the current source circuit is used for providing stable current which is not influenced by external interference for the application circuit, and in the current source circuit, a power supply voltage end is grounded through a first branch of a first current mirror and a first branch of a second current mirror in sequence; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor R in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through a first resistor; the collector of the first triode is connected with the base of at least one output triode. By the circuit structure, the bias voltage VBIAS on the collector electrode of the first triode can not be influenced by external interference, so that the current output by the output end is not influenced by the external interference, the circuit with strong anti-interference capability is ensured to provide stable current which is not influenced by the external interference for other application circuits in the integrated circuit control chip in the battery power supply circuit, and the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved;
on the basis of the circuit structure, the comparator circuit and the reference power supply circuit are both circuits with strong anti-interference capability, so that the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram illustrating a circuit with high interference rejection capability according to an exemplary embodiment of the present application.
Fig. 2 shows a bias voltage generation circuit according to an embodiment of the present application.
Fig. 3 shows a schematic diagram of a disturbed bias voltage generation circuit according to an embodiment of the present application.
Fig. 4 shows an equivalent small-signal model diagram of a disturbed bias voltage generation circuit according to an embodiment of the present application.
Fig. 5 is a schematic diagram illustrating a robust comparator circuit according to an exemplary embodiment of the present application.
Fig. 6 is a schematic diagram illustrating a reference power circuit with high interference rejection capability according to an exemplary embodiment of the present application.
Fig. 7 is a schematic diagram of a reference power supply circuit with high interference rejection capability according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram illustrating a circuit with high interference rejection capability according to an exemplary embodiment of the present application.
The circuit comprises an application circuit and a current source circuit;
in the current source circuit, a power supply voltage terminal VCC is grounded through a first branch of a first current mirror and a first branch of a second current mirror in sequence;
the power supply voltage end VCC is grounded through a second branch of the first current mirror, a second branch of the second current mirror and a second resistor R2 in sequence;
the power supply voltage end VCC is also connected to a collector electrode of the first triode through a third branch of the first current mirror and the first resistor R1 in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through the first resistor R1;
the collector electrode of the first triode Q1 is connected with the base electrode of at least one output triode;
the application circuit comprises at least one output terminal; the output end is grounded through the output triode and the target resistor in sequence.
In a possible implementation manner, the first branch of the first current mirror includes a fifth triode Q5, and the first branch of the second current mirror includes an eighth triode Q8;
the power supply voltage terminal VCC is grounded through a fifth triode Q5 and an eighth triode Q8 in sequence.
In one possible implementation, the second branch of the first current mirror includes a sixth transistor Q6, and the second branch of the second current mirror includes a ninth transistor Q9;
the power supply voltage terminal VCC is grounded through a sixth triode Q6, a ninth triode Q9 and a second resistor R2 in sequence.
In one possible implementation, the third branch of the first current mirror includes a seventh transistor Q7;
the power supply voltage terminal VCC is connected to the collector of the first triode Q1 sequentially through the seventh triode Q7 and the first resistor R1.
In one possible implementation, the eighth transistor Q8 is formed by at least one target transistor connected in parallel; the ninth triode Q9 is formed by connecting at least one target triode in parallel;
further, the ratio of the target transistor in the eighth transistor Q8 to the target transistor in the ninth transistor Q9 is N, where N is greater than 1.
Preferably, the ratio N may be 8.
Or, the ratio N of the eighth transistor Q8 to the target transistor in the ninth transistor Q9 is equal to 1, that is, the number of the eighth transistor Q8 and the target transistor in the ninth transistor Q9 is the same.
Optionally, when the eighth triode Q8 is composed of a target triode, the eighth triode Q8 is the target triode; when the eighth triode Q8 is composed of at least two target triodes, the at least two target triodes are connected in parallel, that is, the eighth triode Q8 is composed of at least two target triodes in parallel; and the base electrodes of the triodes connected in parallel are connected, the collector electrodes are connected and the emitting electrodes are connected.
Similarly, optionally, when the ninth triode Q9 is composed of a target triode, the ninth triode Q9 is the target triode; when the ninth transistor Q9 is composed of at least two target transistors, the at least two target transistors are connected in parallel, that is, the ninth transistor Q9 is composed of at least two target transistors connected in parallel.
In one possible implementation, the target transistor is an NPN transistor; the fifth triode Q5, the sixth triode Q6 and the seventh triode Q7 are respectively composed of at least one PNP triode; the first triode Q1 is composed of at least one NPN triode;
the number of PNP triodes respectively included in the fifth triode Q5, the sixth triode Q6, and the seventh triode Q7 is equal to the number of target triodes included in the eighth triode Q8;
the number of NPN triodes included in the first triode Q1 is equal to the number of target triodes included in the eighth triode Q8.
Similarly, for any one of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7, when it is composed of at least two PNP transistors, the at least two PNP transistors are connected in parallel.
When the first triode Q1 is composed of at least two NPN triodes, the at least two NPN triodes are connected in parallel.
In one possible implementation, the parameters of the output transistor are the same as the parameters of the ninth transistor Q9.
Optionally, in this embodiment of the present application, each NPN transistor is an NPN transistor having the same parameter, that is, each NPN transistor has the same parameter as the target transistor; and each PNP triode is also a PNP triode with the same parameter.
In the circuit with high interference rejection capability shown in fig. 1, a plurality of output terminals are schematically included, and the output terminals are grounded sequentially through respective output transistors (i.e., the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 shown in fig. 1) and respective target resistors (i.e., the third resistor R3, the fourth resistor R4, and the fifth resistor R5 shown in fig. 1).
That is to say, when the circuit with strong anti-interference capability needs to have multiple outputs, the output end can be designed to be grounded through multiple branches composed of output triodes and target resistors, wherein the number of the branches is equal to the number of the branches required to be output, at this moment, the output triodes of each branch form a current mirror circuit, and the number of the NPN triodes included in the output triodes of each branch is equal.
The operation principle of the circuit with strong interference rejection shown in fig. 1 is as follows:
upon power-up of the circuit, the fifth triode Q5 andthe base voltage of the sixth transistor Q6 is at a low level with respect to the source voltage, at which time the fifth transistor Q5 and the sixth transistor Q6 are turned on, the base voltages of the eighth transistor Q8 and the ninth transistor Q9 are pulled high, the eighth transistor Q8 and the ninth transistor Q9 are turned on, and a current is generated in the fifth transistor Q5, the sixth transistor Q6, the eighth transistor Q8 and the ninth transistor Q9
Figure 352902DEST_PATH_IMAGE001
(ii) a Meanwhile, the collector current formula of the triode is->
Figure 535621DEST_PATH_IMAGE002
In which>
Figure 580938DEST_PATH_IMAGE003
For the voltage between base and emitter of a triode>
Figure 992459DEST_PATH_IMAGE004
For the reverse saturation current of the emitter junction>
Figure 72410DEST_PATH_IMAGE005
Is the voltage equivalent of the temperature, therefore, the voltage between the base and the emitter of the eighth triode
Figure 160452DEST_PATH_IMAGE006
Therefore, is present in>
Figure 958643DEST_PATH_IMAGE007
Can be obtained>
Figure 423123DEST_PATH_IMAGE008
；
Figure 357581DEST_PATH_IMAGE009
Is the resistance value of the second resistor R2; preferably, the resistance of the second resistor R2 may be 54K.
At the same time, the base voltage of the seventh transistor Q7 is at a low level with respect to the source voltage, at which time, the seventh transistor Q7 is turned on,the base voltage of the first triode Q1 is pulled high, the first triode Q1 is conducted, and since the fifth triode Q5, the sixth triode Q6 and the seventh triode Q7 constitute a first current mirror circuit, the current flowing through the branch circuit formed by the seventh triode Q7, the first resistor R1 and the first triode Q1 is also the current flowing through the branch circuit
Figure 616524DEST_PATH_IMAGE001
。
Referring to fig. 2, a bias voltage generating circuit according to an embodiment of the present application is shown. As shown in fig. 2, the bias voltage generating circuit is a circuit portion formed by the first transistor Q1 and the first resistor R1 in fig. 1, and at this time, if the circuit with strong interference immunity shown in fig. 1 is interfered by the outside, the current output by the collector of the seventh transistor Q7 in the circuit with strong interference immunity is the current output by the collector of the seventh transistor Q7
Figure 885700DEST_PATH_IMAGE010
Wherein->
Figure 888291DEST_PATH_IMAGE001
Is the normal current output by the collector of the seventh triode Q7>
Figure 677256DEST_PATH_IMAGE011
In order to disturb the current, the base voltage of the first transistor Q1 in the bias voltage generating circuit is equal to VB + vin, where VB is the normal current
Figure 372679DEST_PATH_IMAGE001
The generated base voltage vin is a small signal due to a small voltage change generated by the interference current ic, and then the interfered bias voltage generating circuit can be obtained.
As shown in fig. 3, a schematic diagram of the disturbed bias voltage generation circuit according to the embodiment of the present application is shown, where vin is a small signal input and vout is a small signal output. From the disturbed bias voltage generation circuit in fig. 3, an equivalent small signal model of the circuit can be obtained to perform small signal analysis on the disturbed bias voltage generation circuit. Fig. 4 is a schematic diagram showing an equivalent small-signal model of the disturbed bias voltage generation circuit according to the embodiment of the present application.
From the small signal model of FIG. 4
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And vbe = vin, thus
Figure 420587DEST_PATH_IMAGE013
，
Figure 329637DEST_PATH_IMAGE014
，
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Is the transconductance of the first triode Q1, thereby obtaining
Figure 941195DEST_PATH_IMAGE016
Therefore, at this time, the gain of the small signal model is:
Figure 285589DEST_PATH_IMAGE017
；
Figure 49145DEST_PATH_IMAGE018
Is the resistance value of the first resistor R1;
and transconductance of the triode
Figure 86371DEST_PATH_IMAGE015
Is calculated as>
Figure 302589DEST_PATH_IMAGE019
Wherein is present>
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Is the normal current received by the collector of the transistor Q1 and, based on the previous analysis, is known to be present>
Figure 68737DEST_PATH_IMAGE008
Therefore, at this time, can be->
Figure 531991DEST_PATH_IMAGE020
Thus, gain
Figure 235505DEST_PATH_IMAGE021
；
It can be seen that, in order to ensure that the bias voltage VBIAS generated by the bias voltage generating circuit is not affected by external interference, it is necessary to use the gain of the equivalent small signal model of the interfered bias voltage generating circuit
Figure 921701DEST_PATH_IMAGE022
Is designed to be 0, i.e. at this time, will
Figure 659850DEST_PATH_IMAGE023
It is only necessary to design the resistance value of the first resistor R1 equal to 0, so that the resistance value of the first resistor R1 is designed to be equal to ^ greater or greater than>
Figure 38879DEST_PATH_IMAGE024
After, gain
Figure 229689DEST_PATH_IMAGE025
The small signal output vout is not interfered by the small signal input vin, that is, the node where the small signal output vout is located is a node where the small signal voltage is equal to 0, and the node has strong anti-interference capability, so that in fig. 1, the interference generated by the node where the VB voltage is located does not affect the node voltage of VBIAS, that is, the bias voltage VBIAS generated by the bias voltage generating circuit is not affected by external interference;
meanwhile, since the collector current flowing through the first transistor Q1 is equal to the collector current flowing through the eighth transistor Q8, the voltage between the base and emitter in the first transistor is increased
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And the emitter of the first triode Q1 and the emitter of the eighth triode Q8 are both grounded, so that the timing for switching on and off the switch is set>
Figure 46652DEST_PATH_IMAGE027
；
At this time, the process of the present invention,
Figure 347314DEST_PATH_IMAGE028
accordingly, the base voltages of the output transistors (i.e., the second to fourth transistors Q2 to Q4 shown in fig. 1) are at a high level, the second to fourth transistors Q2 to Q4 are turned on, and the output current circuit generates the output current->
Figure 25420DEST_PATH_IMAGE029
(ii) a And the resistance values of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are all designed to be greater or less than the preset value>
Figure 318999DEST_PATH_IMAGE030
；
Suppose that this time
Figure 766160DEST_PATH_IMAGE031
Since the parameters of the second transistor Q2 (output transistor) and the ninth transistor Q9 are the same, the number of NPN transistors included in the second transistor Q2 is equal to the number of NPN transistors included in the ninth transistor Q9, and the transistors included in the second transistor Q2 and the ninth transistor Q9 are NPN transistors having the same parameter, the voltage | or |, between the base and the emitter of the second transistor Q2>
Figure 221413DEST_PATH_IMAGE032
Is greater than the voltage between the base electrode and the emitting electrode of the ninth triode Q9
Figure 386815DEST_PATH_IMAGE033
And the emitter voltage of the second triode Q2 +>
Figure 218504DEST_PATH_IMAGE034
，
Figure 785752DEST_PATH_IMAGE035
Is the value of the third resistor R3 and, therefore, is greater than or equal to>
Figure 661173DEST_PATH_IMAGE036
。
By
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Is ready to obtain
Figure 949252DEST_PATH_IMAGE038
It is clear that this conclusion is in accordance with the earlier assumption>
Figure 105427DEST_PATH_IMAGE039
Contradictory, so this assumption does not hold;
suppose that this time
Figure 168061DEST_PATH_IMAGE040
Since the parameters of the second transistor Q2 (output transistor) and the ninth transistor Q9 are the same, then->
Figure 308055DEST_PATH_IMAGE038
And &>
Figure 747127DEST_PATH_IMAGE041
And therefore, the first and second electrodes are,
Figure 774120DEST_PATH_IMAGE042
and is as follows from the above
Figure 7655DEST_PATH_IMAGE040
When it is->
Figure 369366DEST_PATH_IMAGE043
And due to->
Figure 346549DEST_PATH_IMAGE037
Can be obtained>
Figure 477316DEST_PATH_IMAGE039
It is clear that this conclusion is in accordance with the earlier assumption>
Figure 881753DEST_PATH_IMAGE038
Contradictory, so this assumption does not hold;
suppose that this time
Figure 730760DEST_PATH_IMAGE044
Since the parameters of the second transistor Q2 (output transistor) and the ninth transistor Q9 are the same, then->
Figure 246055DEST_PATH_IMAGE045
And &>
Figure 746175DEST_PATH_IMAGE046
And therefore, the first and second electrodes are,
Figure 321513DEST_PATH_IMAGE036
to is that
Figure 657817DEST_PATH_IMAGE047
。
Thus, it is possible to provide
Figure 976803DEST_PATH_IMAGE037
Is ready to obtain
Figure 82162DEST_PATH_IMAGE045
This conclusion is based on the assumption>
Figure 828401DEST_PATH_IMAGE045
So that the assumption holds, it can be obtained
Figure 386421DEST_PATH_IMAGE048
。
At this time, since the bias voltage VBIAS generated by the bias voltage generating circuit is not affected by the external disturbance, the current finally output by the output current circuit
Figure 509098DEST_PATH_IMAGE049
The circuit with strong anti-interference capability is ensured to be other application circuits in the control chip of the integrated circuit in the battery power supply circuitProviding a stable current that is not affected by external disturbances;
in summary, the circuit according to the present application is divided into an application circuit and a current source circuit, the current source circuit is configured to provide a stable current to the application circuit without being affected by external interference, and in the current source circuit, a power supply voltage end is grounded via a first branch of a first current mirror and a first branch of a second current mirror in sequence; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through a first resistor; the collector of the first triode is connected with the base of at least one output triode. Through the circuit structure, the bias voltage VBIAS on the collector electrode of the first triode is not influenced by external interference, and therefore the current output by the output end is not influenced by the external interference, so that the circuit with high anti-interference capability is ensured to provide stable current which is not influenced by the external interference for other application circuits inside an integrated circuit control chip in a battery power supply circuit, and the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved.
Fig. 5 is a schematic diagram illustrating a robust comparator circuit according to an exemplary embodiment of the present application. As shown in fig. 5, in addition to the circuit with strong interference rejection shown in fig. 1, the circuit with strong interference rejection can provide power supply for the comparison circuit, and the structure is as follows:
in the embodiment of the present application, on the basis of the structure of the circuit with strong interference rejection capability shown in fig. 1, the output terminal of the application circuit includes a first output terminal and a second output terminal;
in the application circuit, the power supply voltage terminal VCC is connected to the first output terminal through the first branch of the third current mirror and the thirteenth pole tube Q10 in sequence; the power supply voltage terminal VCC is connected to the first output terminal through the second branch of the third current mirror and the eleventh triode Q11 in sequence;
the power supply voltage end VCC is also connected to the base of the fourteenth triode Q14 through the second branch of the third current mirror in sequence;
the power supply voltage terminal VCC is also connected to the second output terminal of the application circuit through the fourteenth transistor Q14.
Further, the application circuit is a comparator circuit, and the base of the thirteenth triode Q10 and the base of the eleventh triode Q11 are respectively connected to the voltage signals to be compared.
Further, the output triode comprises a second triode Q2 and a third triode Q3; the target resistor comprises a third resistor R3 and a fourth resistor R4;
the first output end is grounded through the second triode Q2 and the third resistor R3 in sequence;
the second output terminal is grounded through the third triode Q3 and the fourth resistor R4 in sequence.
Further, the first branch of the third current mirror comprises a twelfth triode Q12; the second branch of the third current mirror comprises a thirteenth triode Q13;
the power supply voltage terminal VCC is connected to the first output terminal through the twelfth triode Q12 and the thirteenth triode Q10 in sequence;
the power supply voltage terminal VCC is connected to the first output terminal through the thirteenth triode Q13 and the eleventh triode Q11 in sequence.
Furthermore, the thirteenth polar tube Q10 and the eleventh polar tube Q11 are respectively composed of at least one NPN triode; and the number of NPN triodes included in the thirteenth triode Q10 and the eleventh triode Q11 is equal to the number of target triodes included in the eighth triode Q8.
When any one of the thirteenth and eleventh diodes Q10 and Q11 is composed of at least two NPN transistors, the at least two NPN transistors are connected in parallel.
Further, the twelfth triode Q12 and the thirteenth triode Q13 are respectively formed by at least one PNP triode; and the number of PNP triodes included in the twelfth triode Q12 and the thirteenth triode Q13 is equal to the number of target triodes included in the eighth triode Q8.
For any one of the twelfth transistor Q12 and the thirteenth transistor Q13, when it is composed of at least two PNP transistors, the at least two PNP transistors are connected in parallel.
Further, the fourteenth triode Q14 is formed by connecting at least two PNP triodes in parallel; and the fourteenth transistor Q14 includes two times as many PNP transistors as the eighth transistor Q8 includes.
At this moment, the application circuit can realize the function of the comparator, and the second output end in the application circuit is the voltage output end VOUT of the comparator.
The working principle of the comparator circuit with strong anti-interference capability is as follows: after voltage signals are input at two input ends in1 and in2 of the current mirror circuit, a thirteenth polar tube Q10 and an eleventh polar tube Q11 are conducted, at the moment, a branch circuit composed of the thirteenth polar tube Q10 and a twelfth polar tube Q12 and a branch circuit composed of the eleventh polar tube Q11 and a thirteenth polar tube Q13 share the current and overcurrent, and because the twelfth polar tube Q12 and the thirteenth polar tube Q13 form a current mirror circuit (namely a third current mirror), the currents flowing through the two branch circuits are equal and are both current mirror circuits
Figure 219696DEST_PATH_IMAGE050
(ii) a At this time, since the base of the fourteenth transistor Q14 is pulled low, the fourteenth transistor Q14 is turned on, and since the fourteenth transistor Q14 is connected in series with the third transistor Q3, the current flowing through the fourteenth transistor Q14 is->
Figure 136837DEST_PATH_IMAGE049
；/>
The ratio of the number of PNP triodes included in the fourteenth triode Q14 to the number of PNP triodes included in the twelfth triode Q12 and the thirteenth triode Q13 is 2:1, the PNP transistor included in the fourteenth transistor Q14 and the PNP transistors included in the twelfth transistor Q12 and the thirteenth transistor Q13 are transistors having the same parameter, and the transistors are not limited to the transistorsAccording to when
Figure 447732DEST_PATH_IMAGE002
Can tell>
Figure 108521DEST_PATH_IMAGE051
Therefore, the collector voltages of the twelfth transistor Q12 and the thirteenth transistor Q13 are also equal, thereby ensuring the matching degree of the currents flowing through the twelfth transistor Q12 and the thirteenth transistor Q13;
when in1>At in2, since the thirteenth diode Q10 is connected to the emitter of the eleventh triode Q11, the voltage between the base and the emitter of the thirteenth diode
Figure 188472DEST_PATH_IMAGE052
Is greater than the voltage between the base and the emitter of the eleventh triode>
Figure 542093DEST_PATH_IMAGE053
Therefore, the current flowing through the thirteenth pole tube>
Figure 74706DEST_PATH_IMAGE054
Greater than the current flowing through the eleventh triode>
Figure 788453DEST_PATH_IMAGE055
And the current flowing through the twelfth triode Q12 and the thirteenth triode Q13 is AND->
Figure 457331DEST_PATH_IMAGE054
So that the base voltage of the fourteenth transistor Q14 rises and the voltage between the base and emitter of the fourteenth transistor is greater or less>
Figure 981854DEST_PATH_IMAGE056
Decreases, the current flowing through the fourteenth triode Q14 decreases less than ≥>
Figure 1762DEST_PATH_IMAGE057
Therefore, the voltage of the voltage output terminal VOUT is lowered, and the output is performedA low level;
when in1<in2, since the emitters of the thirteenth and eleventh transistors Q10 and Q11 are connected, the voltage drop across the gate of the transistor,
Figure 4353DEST_PATH_IMAGE058
therefore is based on>
Figure 793318DEST_PATH_IMAGE059
And the current flowing through the twelfth transistor Q12 and the thirteenth transistor Q13
Figure 488741DEST_PATH_IMAGE054
Equal, therefore, the base voltage of the fourteenth transistor Q14 is lowered and->
Figure 730367DEST_PATH_IMAGE056
And increases the current flowing through the fourteenth triode Q14 to be greater than ≥>
Figure 287381DEST_PATH_IMAGE057
Therefore, the voltage of the voltage output terminal VOUT rises, outputting a high level;
at this time, due to the current
Figure 196431DEST_PATH_IMAGE057
The comparator circuit is a stable current with strong anti-interference capability, so that the comparator circuit with strong anti-interference capability is ensured.
In summary, the circuit according to the present application is divided into an application circuit and a current source circuit, the current source circuit is configured to provide a stable current to the application circuit without being affected by external interference, and in the current source circuit, a power supply voltage end is grounded via a first branch of a first current mirror and a first branch of a second current mirror in sequence; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor R in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through a first resistor; the collector of the first triode is connected with the base of at least one output triode. By the circuit structure, the bias voltage VBIAS on the collector electrode of the first triode can not be influenced by external interference, so that the current output by the output end is not influenced by the external interference, the circuit with strong anti-interference capability is ensured to provide stable current which is not influenced by the external interference for other application circuits in the integrated circuit control chip in the battery power supply circuit, and the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved;
on the basis of the circuit with strong anti-interference capability, the comparator circuit provided by the application is also the circuit with strong anti-interference capability, so that the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved.
Fig. 6 is a schematic diagram illustrating a structure of a reference power circuit with high interference rejection capability according to an exemplary embodiment of the present application. As shown in fig. 6, in addition to the circuit with high interference rejection shown in fig. 1, the reference power supply circuit can be supplied with power through the circuit with high interference rejection, and the structure is as follows:
in the embodiment of the present application, based on the structure of the circuit with strong interference rejection capability shown in fig. 1, the output terminal of the application circuit includes a third output terminal;
in the application circuit, a power supply voltage end is connected to the third output end through a first branch of a fourth current mirror;
the power supply voltage end is connected to the voltage output end of the application circuit through a second branch of the fourth current mirror;
the voltage output terminal is grounded via a sixth resistor R6 and a seventeenth transistor Q17 in this order.
Further, the first branch of the fourth current mirror includes a fifteenth transistor Q15; the second branch of the fourth current mirror comprises a sixteenth triode Q16;
the power supply voltage terminal VCC is connected to the third output terminal through the fifteenth triode Q15;
the power supply voltage terminal VCC is connected to the voltage output terminal of the application circuit through a sixteenth transistor Q16.
Further, the fifteenth triode Q15, the sixteenth triode Q16 and the seventeenth triode Q17 are respectively formed by at least one PNP triode;
the number of PNP triodes included in the fifteenth triode Q15, the sixteenth triode Q16, and the seventeenth triode Q17 is equal to the number of target triodes included in the eighth triode Q8.
As for any one of the fifteenth transistor Q15, the sixteenth transistor Q16 and the seventeenth transistor Q17, when it is composed of at least two PNP transistors, the at least two PNP transistors are connected in parallel.
The working principle of the comparator circuit with strong anti-interference capability is as follows: the fifteenth transistor Q15 and the sixteenth transistor Q16 constitute a current mirror circuit, and therefore, the currents flowing through the fifteenth transistor Q15 and the sixteenth transistor Q16 are both
Figure 797177DEST_PATH_IMAGE057
And, at the same time, the voltage between the base and emitter of the triode in the art @>
Figure 791678DEST_PATH_IMAGE060
And the voltage equivalent of the temperature>
Figure 136071DEST_PATH_IMAGE061
And K is the Kelvin temperature.
Therefore, the voltage output terminal VOUT of the reference power supply circuit of the embodiment of the present application satisfies
Figure 899628DEST_PATH_IMAGE062
；
And is
Figure 671275DEST_PATH_IMAGE063
，
Figure 153072DEST_PATH_IMAGE064
Is the resistance of the sixth resistor R6Value +>
Figure 544565DEST_PATH_IMAGE065
The voltage value between the base and the emitter of the seventeenth triode is determined, and the relation of various parameters is designed to be->
Figure 162628DEST_PATH_IMAGE066
Can obtain the->
Figure 370755DEST_PATH_IMAGE067
；
At this time, due to the current
Figure 339848DEST_PATH_IMAGE057
The reference power supply circuit is a stable current with strong anti-interference capability, so that the reference power supply circuit with strong anti-interference capability is ensured.
In summary, the circuit according to the present application is divided into an application circuit and a current source circuit, the current source circuit is configured to provide a stable current to the application circuit without being affected by external interference, and in the current source circuit, a power supply voltage end sequentially passes through a first branch of a first current mirror and a first branch of a second current mirror and is grounded; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor R in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through a first resistor; the collector of the first triode is connected with the base of at least one output triode. By the circuit structure, the bias voltage VBIAS on the collector electrode of the first triode can not be influenced by external interference, so that the current output by the output end is not influenced by the external interference, the circuit with strong anti-interference capability is ensured to provide stable current which is not influenced by the external interference for other application circuits in the integrated circuit control chip in the battery power supply circuit, and the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved;
on the basis of the circuit with strong anti-interference capability, the reference power supply circuit is also the circuit with strong anti-interference capability, so that the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved.
Fig. 7 is a schematic diagram illustrating a structure of a reference power circuit with high interference rejection capability according to an exemplary embodiment of the present application. As shown in fig. 7, in addition to the circuit with strong interference rejection shown in fig. 1, another reference power supply circuit can be supplied with power by the circuit with strong interference rejection, and the structure is as follows:
in the embodiment of the present application, based on the structure of the circuit with high interference rejection shown in fig. 1, the output terminal of the application circuit includes a fourth output terminal;
the power supply voltage terminal VCC is connected to the fourth output terminal through an eighteenth triode Q18 and a seventh resistor R7;
the fourth output terminal is an output voltage terminal of the application circuit.
Further, the eighteenth triode Q18 is formed by at least one PNP triode; the number of PNP transistors included in the eighteenth transistor Q18 is equal to the number of target transistors included in the eighth transistor Q8.
When the eighteenth transistor Q18 is formed of at least two PNP transistors, the at least two PNP transistors are connected in parallel.
The working principle of the comparator circuit with strong anti-interference capability is as follows: the eighteenth transistor Q18 is connected in series with the second transistor Q2 (i.e., the output transistor), and thus, the current flowing through the eighteenth transistor Q18 is also
Figure 26045DEST_PATH_IMAGE057
And, at the same time, the voltage between the base and emitter of the triode in the art @>
Figure 764193DEST_PATH_IMAGE060
And voltage equivalent of temperature
Figure 877643DEST_PATH_IMAGE061
K is Kelvin temperature->
Figure 819185DEST_PATH_IMAGE068
While
Figure 309072DEST_PATH_IMAGE069
By>
Figure 901728DEST_PATH_IMAGE070
It can be known that
Figure 451658DEST_PATH_IMAGE071
Thus, therefore, it is
Figure 129764DEST_PATH_IMAGE072
Wherein->
Figure 157763DEST_PATH_IMAGE073
Is the resistance value of the seventh resistor R7, is greater than or equal to>
Figure 604925DEST_PATH_IMAGE074
The voltage between the base electrode and the emitting electrode of the eighteenth triode; in this case, the relationship of the individual parameters is designed to ^ er>
Figure 325756DEST_PATH_IMAGE075
Can obtain the->
Figure 740426DEST_PATH_IMAGE076
；
At this time, due to the current
Figure 572115DEST_PATH_IMAGE057
The reference power supply circuit is a stable current with strong anti-interference capability, so that the reference power supply circuit with strong anti-interference capability is ensured. />
In summary, the circuit according to the present application is divided into an application circuit and a current source circuit, the current source circuit is configured to provide a stable current to the application circuit without being affected by external interference, and in the current source circuit, a power supply voltage end is grounded via a first branch of a first current mirror and a first branch of a second current mirror in sequence; the power supply voltage end is grounded through a second branch of the first current mirror, a second branch of the second current mirror and the second resistor in sequence; the power supply voltage is also connected to the collector electrode of the first triode through the third branch of the first current mirror and the first resistor R in sequence; the emitter of the first triode is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode through a first resistor; the collector of the first triode is connected with the base of at least one output triode. By the circuit structure, the bias voltage VBIAS on the collector electrode of the first triode can not be influenced by external interference, so that the current output by the output end is not influenced by the external interference, the circuit with strong anti-interference capability is ensured to provide stable current which is not influenced by the external interference for other application circuits in the integrated circuit control chip in the battery power supply circuit, and the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved;
on the basis of the circuit with strong anti-interference capability, the reference power supply circuit is also the circuit with strong anti-interference capability, so that the control precision of the integrated circuit control chip and the output precision of the battery power supply circuit are improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (18)

1. A circuit with strong anti-interference capability is characterized by comprising an application circuit and a current source circuit;
in the current source circuit, a power supply voltage terminal VCC sequentially passes through a first branch of a first current mirror and a first branch of a second current mirror to be grounded; the first branch of the second current mirror comprises an eighth triode Q8;
the power supply voltage end VCC is grounded through a second branch of the first current mirror, a second branch of the second current mirror and a second resistor R2 in sequence; the second branch of the second current mirror comprises a ninth triode Q9;
the eighth triode Q8 is composed of at least one target triode; the ninth triode Q9 is composed of at least one target triode; the ratio of the target triode in the eighth triode Q8 to the target triode in the ninth triode Q9 is N, and N is more than 1; the ratio of the resistance value of the second resistor R2 to the resistance value of the first resistor R1 is lnN;
the power supply voltage end VCC is also connected to a collector electrode of the first triode Q1 through a third branch of the first current mirror and the first resistor R1 in sequence; the emitting electrode of the first triode Q1 is grounded; the base electrode of the first triode is also connected to the collector electrode of the first triode Q1 through the first resistor R1;
the collector electrode of the first triode Q1 is connected with the base electrode of at least one output triode;
the application circuit comprises at least one output terminal; the output end is grounded through the output triode and the target resistor in sequence.
2. The circuit of claim 1, wherein the first branch of the first current mirror comprises a fifth transistor Q5;
and the power supply voltage terminal VCC is grounded through a fifth triode Q5 and an eighth triode Q8 in sequence.
3. The circuit of claim 2, wherein the second branch of the first current mirror comprises a sixth transistor Q6;
and the power supply voltage end VCC is grounded through a sixth triode Q6, a ninth triode Q9 and a second resistor R2 in sequence.
4. The circuit of claim 3, wherein the third branch of the first current mirror comprises a seventh transistor Q7;
and the power supply voltage end VCC is connected to the collector electrode of the first triode Q1 sequentially through a seventh triode Q7 and a first resistor R1.
5. The circuit of claim 4, wherein the target transistor is an NPN transistor; the fifth triode Q5, the sixth triode Q6 and the seventh triode Q7 are respectively composed of at least one PNP triode; the first triode Q1 is composed of at least one NPN triode;
the number of PNP triodes respectively included in the fifth triode Q5, the sixth triode Q6 and the seventh triode Q7 is equal to the number of target triodes included in the eighth triode Q8;
the number of the NPN triodes contained in the first triode Q1 is equal to the number of the target triodes contained in the eighth triode Q8.
6. The circuit of claim 4, wherein the parameters of the output transistor are the same as the parameters of the ninth transistor Q9.
7. The circuit of any of claims 1 to 6, wherein the output of the application circuit comprises a first output and a second output;
in the application circuit, the power supply voltage terminal VCC is connected to the first output terminal through a first branch of a third current mirror and a thirteenth polar tube Q10 in sequence; the power supply voltage terminal VCC is connected to the first output terminal through a second branch of the third current mirror and an eleventh triode Q11 in sequence;
the power supply voltage end VCC is also connected to the base electrode of a fourteenth triode Q14 through a second branch of the third current mirror in sequence;
the power supply voltage terminal VCC is further connected to the second output terminal of the application circuit through the fourteenth triode Q14.
8. The circuit of claim 7, wherein the application circuit is a comparator circuit, and the base of the thirteenth diode Q10 and the base of the eleventh diode Q11 are respectively connected to the voltage signals to be compared.
9. The circuit of claim 8, wherein the output transistor comprises a second transistor Q2 and a third transistor Q3; the target resistor comprises a third resistor R3 and a fourth resistor R4;
the first output end is grounded through the second triode Q2 and the third resistor R3 in sequence;
the second output end is grounded through the third triode Q3 and the fourth resistor R4 in sequence.
10. The circuit of claim 8, wherein the first branch of the third current mirror comprises a twelfth transistor Q12; the second branch of the third current mirror comprises a thirteenth triode Q13;
the power supply voltage terminal VCC is connected to the first output terminal through the twelfth triode Q12 and the thirteenth triode Q10 in sequence;
the power supply voltage terminal VCC is connected to the first output terminal through the thirteenth triode Q13 and the eleventh triode Q11 in sequence.
11. The circuit according to claim 10, wherein the thirteenth transistor Q10 and the eleventh transistor Q11 are respectively formed by at least one NPN transistor; the number of the NPN triodes included in the thirteenth triode Q10 and the eleventh triode Q11 is equal to the number of the target triodes included in the eighth triode Q8.
12. The circuit according to claim 11, wherein the twelfth transistor Q12 and the thirteenth transistor Q13 are respectively formed by at least one PNP transistor; and the number of PNP triodes respectively included in the twelfth triode Q12 and the thirteenth triode Q13 is equal to the number of target triodes included in the eighth triode Q8.
13. The circuit of claim 12, wherein the fourteenth transistor Q14 is formed by at least two PNP transistors connected in parallel; and the number of PNP triodes included in the fourteenth triode Q14 is twice the number of target triodes included in the eighth triode Q8.
14. The circuit of any of claims 1 to 6, wherein the output of the application circuit comprises a third output;
in the application circuit, a power supply voltage end is connected to the third output end through a first branch of a fourth current mirror;
the power supply voltage end is connected to the voltage output end of the application circuit through a second branch of the fourth current mirror;
the voltage output end is grounded through a sixth resistor R6 and a seventeenth triode Q17 in sequence.
15. The circuit of claim 14, wherein the first branch of the fourth current mirror comprises a fifteenth transistor Q15; the second branch of the fourth current mirror comprises a sixteenth triode Q16;
the power supply voltage terminal VCC is connected to the third output terminal through the fifteenth triode Q15;
and the power supply voltage terminal VCC is connected to the voltage output terminal of the application circuit through a sixteenth triode Q16.
16. The circuit according to claim 15, wherein the fifteenth transistor Q15, the sixteenth transistor Q16 and the seventeenth transistor Q17 are each formed by at least one PNP transistor;
the number of PNP triodes included in the fifteenth triode Q15, the sixteenth triode Q16, and the seventeenth triode Q17 is equal to the number of target triodes included in the eighth triode Q8.
17. The circuit of any of claims 1 to 6, wherein the output of the application circuit comprises a fourth output;
the power supply voltage terminal VCC is connected to the fourth output terminal through an eighteenth triode Q18 and a seventh resistor R7;
the fourth output end is an output voltage end of the application circuit.
18. The circuit of claim 17, wherein the eighteenth transistor Q18 is formed by at least one PNP transistor; the number of PNP triodes included in the eighteenth triode Q18 is equal to the number of target triodes included in the eighth triode Q8.
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