CN115395366A - Method for manufacturing laser chip - Google Patents
Method for manufacturing laser chip Download PDFInfo
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- CN115395366A CN115395366A CN202210997237.6A CN202210997237A CN115395366A CN 115395366 A CN115395366 A CN 115395366A CN 202210997237 A CN202210997237 A CN 202210997237A CN 115395366 A CN115395366 A CN 115395366A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000010521 absorption reaction Methods 0.000 claims abstract description 77
- 238000000137 annealing Methods 0.000 claims abstract description 60
- 230000008569 process Effects 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 110
- 238000000151 deposition Methods 0.000 claims description 23
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 238000010894 electron beam technology Methods 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 11
- 230000000670 limiting effect Effects 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000005253 cladding Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 238000005536 corrosion prevention Methods 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 9
- 230000002829 reductive effect Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 4
- 230000002401 inhibitory effect Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000001737 promoting effect Effects 0.000 abstract description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000007547 defect Effects 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 6
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000002318 adhesion promoter Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/1028—Coupling to elements in the cavity, e.g. coupling to waveguides adjacent the active region, e.g. forward coupled [DFC] structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2004—Confining in the direction perpendicular to the layer structure
- H01S5/2009—Confining in the direction perpendicular to the layer structure by using electron barrier layers
- H01S5/2013—MQW barrier reflection layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/3407—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers characterised by special barrier layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/3421—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers layer structure of quantum wells to influence the near/far field
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The embodiment of the invention discloses a method for manufacturing a laser chip, which comprises the following steps: preparing an epitaxial wafer; forming a first mask layer on a region outside the non-absorption region, and forming a second mask layer on the non-absorption region; annealing the epitaxial wafer; removing the first mask layer and the second mask layer; and carrying out subsequent wafer flowing process on the epitaxial wafer with the first mask layer and the second mask layer removed. The method can avoid the oxidation of the material of the laser containing Al, make the absorption coefficient of the non-absorption region smaller, and relieve the quality degradation of the quantum well of the light-emitting region, thereby further improving the stability and reliability of the laser chip. The process flow is simple, butt-joint growth is not needed, the cost is lower, the first mask layer and the second mask layer are used for respectively inhibiting and promoting the quantum well intermixing of the active region, the temperature and the time required during annealing can be reduced, the quality of the quantum well of the active region is protected, and the operability of the process is improved.
Description
Technical Field
The invention relates to the technical field of lasers, in particular to a manufacturing method of a laser chip.
Background
In the field of optical communication, semiconductor lasers are the most widely used light sources due to their advantages of small size, easy integration, excellent performance, and the like. When a semiconductor laser chip is manufactured, the InGaAlAs material system gradually replaces the conventional InGaAsP material system by virtue of better characteristics, such as higher differential gain and better limiting effect on carriers, and becomes the material of the optical communication laser chip. At present, most of communication light sources from an O waveband to an L waveband adopt an InGaAlAs material system to form a multi-quantum well structure to form an active layer of a laser chip.
However, because the InGaAlAs material system contains Al element, the Al element on the laser end surface is easily oxidized when contacting with air, which causes end surface defects, and the band gap of the defects is smaller than that of the normal crystal structure, so that the defects are more easily absorbed by light. When the optical power of the laser is high, the defects are easy to absorb photons on one hand, and are easy to capture carriers and generate non-radiative recombination on the other hand, so that heat is generated and the defects are enlarged, and the enlarged defects cause stronger light absorption and non-radiative recombination to form negative feedback to cause optical catastrophic damage, so that the end face of the laser is damaged, and the laser fails. And even under the condition that the laser does not generate optical catastrophe damage, the defects caused by cavity surface oxidation are still gradually enlarged, the performance of the laser is influenced, the risk of failure of the laser is increased, and the reliability and the stability of the laser are reduced.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method for manufacturing a laser chip to solve the above technical problems.
The embodiment of the invention provides a manufacturing method of a laser chip, which comprises the following steps:
preparing an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate, a buffer layer, a lower limiting layer, a quantum well active layer, an upper limiting layer, a waveguide layer, a corrosion prevention layer, an upper cladding layer and an ohmic contact layer from bottom to top in the vertical direction, two ends of the ohmic contact layer in the length direction are respectively provided with a non-absorption region, and a light emitting region is arranged between the two non-absorption regions;
forming a first mask layer on a region outside the non-absorption region, and forming a second mask layer on the non-absorption region;
annealing the epitaxial wafer;
removing the first mask layer and the second mask layer on the epitaxial wafer after the annealing treatment;
and carrying out subsequent wafer flowing process on the epitaxial wafer with the first mask layer and the second mask layer removed.
Optionally, forming a first mask layer on a region outside the non-absorption region, and forming a second mask layer on the non-absorption region, includes:
depositing a first mask layer with a first preset thickness on the ohmic contact layer;
coating photoresist on the first mask layer;
removing the photoresist on a first target area of the first mask layer to form a non-absorption area window, wherein the first target area is an area corresponding to the non-absorption area on the first mask layer;
removing the first mask layer corresponding to the non-absorption area window;
removing all the photoresist left on the first mask layer to form a first mask layer on a region outside the non-absorption region;
and depositing a second mask layer with a second preset thickness on the non-absorption region of the ohmic contact layer and the first mask layer.
Optionally, the removing the photoresist in a region corresponding to the non-absorption region on the first mask layer to form a non-absorption region window includes:
exposing the photoresist in the first target area of the first mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist in the first target area to form a non-absorption area window.
Optionally, the removing the photoresist in the region corresponding to the non-absorption region on the first mask layer to form a non-absorption region window includes:
exposing the photoresist of other areas of the first mask layer by using a stepping electron beam or a mask photoetching plate, wherein the other areas of the first mask layer are areas except the first target area on the first mask layer;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist in the first target area to form a non-absorption area window.
Optionally, depositing a second mask layer with a second predetermined thickness on the non-absorption region of the ohmic contact layer and the first mask layer includes:
and depositing a second mask layer with the thickness of 20 to 500 nanometers on the non-absorption region of the ohmic contact layer and the first mask layer by utilizing a PECVD (plasma enhanced chemical vapor deposition) process, introducing a mixed gas of pure silane and ammonia gas or a mixed gas of ammonia gas and nitrogen gas in the process of depositing the second mask layer, and ionizing under a nitrogen environment to deposit the second mask layer, wherein the refractive index of the second mask layer is 1.9-2.2, and the radio frequency power in the PECVD process is 10-60 watts.
Optionally, forming a first mask layer on a region outside the non-absorption region, and forming a second mask layer on the non-absorption region, includes:
depositing a second mask layer with a second preset thickness on the ohmic contact layer;
coating photoresist on the second mask layer;
removing the photoresist on other areas of the second mask layer to expose the second mask layer in other areas, wherein the other areas of the second mask layer are areas on the second mask layer except for a second target area, and the second target area is an area corresponding to the non-absorption area on the second mask layer;
removing the second mask layer on the other areas;
removing all the photoresist left on the second mask layer to form a second mask layer on the non-absorption region;
and depositing a first mask layer with a first preset thickness on the ohmic contact layer in a region except the non-absorption region and the second mask layer.
Optionally, the removing the photoresist on the other region of the second mask layer to expose the second mask layer of the other region includes:
exposing the photoresist in other areas of the second mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, removing the photoresist on the other areas, and exposing the second mask layer of the other areas.
Optionally, the removing the photoresist on the other region of the second mask layer to expose the second mask layer of the other region includes:
exposing the photoresist on the second target area of the second mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, removing the photoresist on the other areas, and exposing the second mask layer of the other areas.
Optionally, before the annealing is performed on the epitaxial wafer, the annealing includes:
and covering a cover plate on the second mask layer.
Optionally, the annealing treatment is performed on the epitaxial wafer, and includes:
placing the epitaxial wafer in an annealing furnace for annealing;
in the annealing process, the annealing temperature is increased from a first preset temperature to a second preset temperature within a first preset time period, wherein the duration of the first preset time period is less than or equal to 40 seconds;
maintaining the annealing temperature at the second preset temperature within a second preset time period, wherein the duration of the second preset time period is less than or equal to 200 seconds;
and reducing the annealing temperature from the second preset temperature to the first preset temperature within a third preset time period, wherein the duration of the third preset time period is less than or equal to 30 seconds.
Optionally, the annealing treatment is performed on the epitaxial wafer, and includes:
placing the epitaxial wafer in an annealing furnace for annealing;
in the annealing process, the annealing temperature is increased from the first preset temperature to the second preset temperature within a fourth preset time period;
maintaining the annealing temperature at the second preset temperature within a fifth preset time period, wherein the duration of the fifth preset time period is less than that of the second preset time period;
reducing the annealing temperature from the second preset temperature to the first preset temperature within a sixth preset time period;
and repeating the step of adjusting the temperature in the annealing process until the repeated times reach preset times, wherein the total duration of the annealing temperature maintained at the second preset temperature is greater than or equal to the duration of the second preset time period.
According to the manufacturing method of the laser chip provided by the embodiment of the invention, the light emitting area for emitting light and the non-absorption area for providing a protection effect are divided on the ohmic contact layer, the first mask layer is deposited on the light emitting area, the second mask layer is deposited on the non-absorption area, and then the annealing process is carried out, so that the material oxidation of an Al-containing laser can be avoided, the absorption coefficient of the non-absorption area is smaller, the degradation of the quality of a quantum well of the light emitting area is relieved, and the stability and the reliability of the laser chip are further improved. The process flow is simple, butt-joint growth is not needed, the cost is lower, the first mask layer and the second mask layer are used for respectively inhibiting and promoting the quantum well intermixing of the active region, the temperature and the time required during annealing can be reduced, the quality of the quantum well of the active region is protected, and the operability of the process is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention as a part of the examples. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a flow chart of a method of fabricating a laser chip according to an alternative embodiment of the invention;
FIG. 2 is a flowchart of step S102 according to an alternative embodiment of the present invention;
FIG. 3 is a flowchart of step S102 according to another alternative embodiment of the present invention;
FIG. 4 is a flowchart of step S103 according to an alternative embodiment of the present invention;
FIG. 5 is a flowchart of step S103 according to another alternative embodiment of the present invention;
fig. 6 is a front view of an epitaxial wafer according to an alternative embodiment of the invention;
FIG. 7 is a top view of FIG. 6;
FIG. 8 is a front view of an epitaxial wafer with a first mask layer deposited thereon in accordance with an alternative embodiment of the present invention;
FIG. 9 is a top view of FIG. 8;
fig. 10 is a front view of a positive photoresist coated epitaxial wafer in accordance with an alternative embodiment of the present invention;
FIG. 11 is a top view of FIG. 10;
fig. 12 is a front view of an exposed and developed epitaxial wafer in accordance with an alternative embodiment of the present invention;
FIG. 13 is a top view of FIG. 12;
fig. 14 is a front view of an epitaxial wafer with a first mask layer removed in accordance with an alternative embodiment of the invention;
FIG. 15 is a top view of FIG. 14;
fig. 16 is a front view of an epitaxial wafer coated with a second mask layer in accordance with an alternative embodiment of the present invention;
fig. 17 is a top view of fig. 16.
Fig. 18 is a front view of an epitaxial wafer with a second mask layer deposited thereon in accordance with an alternative embodiment of the present invention;
FIG. 19 is a top view of FIG. 18;
fig. 20 is a front view of a positive photoresist coated epitaxial wafer in accordance with another alternative embodiment of the present invention;
FIG. 21 is a top view of FIG. 22;
fig. 22 is a front view of an exposed and developed epitaxial wafer in accordance with another alternative embodiment of the invention;
FIG. 23 is a top view of FIG. 22;
fig. 24 is a front view of an epitaxial wafer with a second mask layer removed in accordance with an alternative embodiment of the present invention;
FIG. 25 is a top view of FIG. 24;
fig. 26 is a front view of an epitaxial wafer coated with a first mask layer in accordance with another alternative embodiment of the present invention;
fig. 27 is a top view of fig. 26.
Description of the reference numerals:
1-substrate, 2-buffer layer, 3-lower limiting layer, 4-quantum well active layer, 5-upper limiting layer, 6-waveguide layer, 7-corrosion preventing layer, 8-upper cladding layer, 9-ohmic contact layer, 10-first mask layer, 11-positive photoresist, 12-second mask layer, 13-non-absorption region window, 14-first mask layer corrosion window, 14-luminous region, 15-positive photoresist corresponding to second target region, and 16-second mask layer of second target region.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a laser chip, including:
step S101: preparing an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate 1, a buffer layer 2, a lower limiting layer 3, a quantum well active layer 4, an upper limiting layer 5, a waveguide layer 6, a corrosion prevention layer 7, an upper cladding layer 8 and an ohmic contact layer 9 from bottom to top in the vertical direction, non-absorption regions are respectively arranged at two ends of the ohmic contact layer 9 in the length direction, and a light emitting region 14 is arranged between the two non-absorption regions.
As shown in fig. 6 to 17, the X-axis direction in the drawings is the longitudinal direction of the epitaxial wafer, and is also the longitudinal direction of each layer; the Y-axis direction is the width direction of the epitaxial wafer and is also the width direction of each layer; the direction of the Z axis is a vertical direction, which is also a height direction of the epitaxial wafer.
As shown in fig. 6 and 7, the epitaxial wafer includes, from bottom to top in the vertical direction (i.e., Z direction), a substrate 1, a buffer layer 2, a lower confinement layer 3, a quantum well active layer 4, an upper confinement layer 5, a waveguide layer 6, an etch stop layer 7, an upper cladding layer 8, and an ohmic contact layer 9. Wherein the quantum well active layer 4 can be selected from InGaAlAs materials with different components to form the well region and the barrier region of the quantum well, and the peak gain wavelength of the quantum well active layer 4 is 1200 nm according to the requirementAdjusted within the range of meter-1600 nm. The upper cladding layer 8 may optionally be doped InP to provide the group V interstitial atoms required for quantum well intermixing, with a doping concentration of 0.5 x 10 18 ～5×10 18 Per cubic centimeter.
Step S102: a first mask layer 10 is formed on the region outside the non-absorbing region and a second mask layer 12 is formed on the non-absorbing region.
The first mask layer 10 is a silicon oxide mask layer, and the second mask layer 12 is a silicon nitride mask layer.
It can be understood that, the first mask layer 10 is formed on the region outside the non-absorption region, and the second mask layer 12 is formed on the non-absorption region in no sequence, that is, the first mask layer 10 may be formed on the region outside the non-absorption region first, and then the second mask layer 12 may be formed on the non-absorption region; it is also possible to first form the second mask layer 12 on the non-absorbing regions and then form the first mask layer 10 on the regions outside the non-absorbing regions.
Step S103: and annealing the epitaxial wafer.
The annealing process can preserve the quantum well intermixing level of the non-absorbing region.
Step S104: and removing the first mask layer 10 and the second mask layer 12 on the epitaxial wafer after the annealing treatment.
Step S105: and carrying out subsequent wafer flow process on the epitaxial wafer with the first mask layer 10 and the second mask layer 12 removed.
Specifically, when the first mask layer 10 is a silicon oxide mask layer and the second mask layer 12 is a silicon nitride mask layer, the silicon oxide mask layer and the silicon nitride mask layer may be removed by using hydrofluoric acid or BOE solution, and a subsequent tape-out process may be performed. The subsequent tape-out process is the same as the conventional tape-out process, and is not described herein again.
According to the manufacturing method of the laser chip provided by the embodiment, the light emitting region 14 for emitting light and the non-absorption region for providing a protection effect are divided on the ohmic contact layer 9, the first mask layer 10 is deposited on the light emitting region 14, the second mask layer 12 is deposited on the non-absorption region, and then the annealing process is performed, so that the material oxidation of an Al-containing laser can be avoided, the absorption coefficient of the non-absorption region is smaller, the degradation of the quantum well quality of the light emitting region 14 is relieved, and the stability and the reliability of the laser chip are further improved. The process flow is simple, butt growth is not needed, the cost is lower, the first mask layer 10 and the second mask layer 12 are used for respectively inhibiting and promoting quantum well mixing in the active region, the temperature and the time required during annealing can be reduced, the quality of the quantum well in the active region is protected, and the operability of the process is improved.
Further, in an embodiment, as shown in fig. 2, the step S102 specifically includes:
s201: a first mask layer 10 is deposited on the ohmic contact layer 9 to a first predetermined thickness.
Specifically, the method for depositing the first mask layer 10 may be a Plasma Enhanced Chemical Vapor Deposition (PECVD), or may be other existing deposition methods. The first predetermined thickness of the first mask layer 10 can be set by a worker according to actual requirements. In some implementations, the first predetermined thickness is 20 nm to 500 nm, as can be seen in fig. 8 and 9.
S202: a photoresist is coated on the first mask layer 10.
Before coating the photoresist, a layer of adhesion promoter can be spun on to increase the adhesion between the photoresist and the wafer. The photoresist can be positive photoresist 11 or negative photoresist, and fig. 10 and 11 are schematic structural diagrams of an epitaxial wafer coated with positive photoresist 11.
S203: the photoresist on the first target region of the first mask layer 10, which is a region on the first mask layer 10 corresponding to the non-absorbing region, is removed to form a non-absorbing region window 13.
Specifically, in the case where the photoresist is a positive photoresist 11, the step specifically includes:
s2031a: the photoresist of the first target region of the first mask layer 10 is exposed using a step-wise electron beam or a mask reticle.
S2032a: and putting the exposed epitaxial wafer into a developing solution, and removing the photoresist in the first target area to form a non-absorption area window 13.
After the positive photoresist 11 is exposed, the solubility of the positive photoresist in the developing solution is much higher than that of the unexposed photoresist, so that the photoresist on the non-absorption region can be removed by immersing the exposed wafer in the developing solution. The time for immersing the epitaxial wafer into the developing solution is between 5 seconds and 50 seconds.
In the case where the photoresist is a negative photoresist, removing the photoresist on the first mask layer 10 in a region corresponding to the non-absorbing region to form a non-absorbing region window 13, including:
s2031b: the photoresist of the other region of the first mask layer 10 is exposed by using a step-by-step electron beam or a mask reticle, and the other region of the first mask layer 10 is a region other than the first target region on the first mask layer 10.
S2032b: and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist of the first target area to form a non-absorption area window 13.
Negative tone photoresists have the opposite photosensitive character as positive tone photoresists 11, with exposed regions less soluble than unexposed regions. Therefore, when using a negative photoresist, it is necessary to expose the photoresist in areas other than the non-absorbing areas (and the first target area). The time for immersing the epitaxial wafer into the developing solution is between 5 seconds and 50 seconds.
After the epitaxial wafer is immersed in the developing solution and developed, the photoresist is patterned, as shown in fig. 12 and 13. The dotted line box of fig. 12 indicates the non-absorption region window 13 formed by dissolution of the developing solution. While the white dashed box of fig. 13 indicates where the light emitting region 14 is located. The light emitting region 14 is the primary region where optical gain is generated, and thus the degree of quantum well intermixing should be reduced in this region.
S204: the corresponding first mask layer 10 of the non-absorbing region windows 13 is removed.
In some implementations, after step S203, the epitaxial wafer is immersed in a hydrofluoric acid solution, so that the first mask layer 10 (i.e., the silicon oxide layer) corresponding to the non-absorption window can be in contact with the hydrofluoric acid solution to be etched; while the regions of the first mask layer 10 (i.e. the silicon oxide layer) outside the non-absorbing regions are protected by the photoresist. The time for immersing the epitaxial wafer into the hydrofluoric acid solution may be determined according to the concentration of the hydrofluoric acid solution.
In other implementations, the first mask layer 10 (i.e., the silicon Oxide layer) may be etched by using Buffered Oxide Etch (BOE) prepared from hydrofluoric acid, water and ammonium fluoride, and the immersion time is 30 seconds to 500 seconds.
S205: the photoresist remaining on the first mask layer 10 is entirely removed to form the first mask layer 10 on the region other than the non-absorption region.
In this step, the residual photoresist may be removed with a heated N-methylpyrrolidone solution. The temperature of the heated N-methylpyrrolidone solution is kept between 30 and 90 ℃. The wafer after the photoresist is removed is shown in fig. 14 and 15. The dashed box at the level of the first mask layer (silicon oxide mask) in fig. 13 represents the first mask layer etch window 14 formed after the first mask layer (silicon oxide mask) is etched on the non-absorbing region, corresponding to the ohmic contact layer 9 exposed in fig. 13.
S206: a second mask layer 12 of a second predetermined thickness is deposited on the non-absorbing region of the ohmic contact layer 9 and the first mask layer 10, and the structure can be seen in fig. 16 and 17.
Specifically, the method for depositing the second mask layer 12 may be a Plasma Enhanced Chemical Vapor Deposition (PECVD), or may be other existing deposition methods. The second predetermined thickness of the second mask layer 12 can be set by a worker according to actual requirements. The second mask layer 12 (i.e., the silicon nitride mask layer) is in contact with a region of the ohmic contact layer 9 other than the region covered by the first mask layer 10, that is, a region of the ohmic contact layer 9 corresponding to the non-absorption region window 13, so that the second mask layer 12 can be formed on the region of the ohmic contact layer 9 other than the non-absorption region, and the first mask layer 10 can be formed on the non-absorption region.
Under the condition of adopting a PECVD process, the method specifically comprises the following steps:
depositing a second mask layer 12 with a thickness of 20 nm to 500 nm on the non-absorption region of the ohmic contact layer 9 and the first mask layer 10 by using a PECVD process, introducing a mixed gas of pure silane and ammonia gas or a mixed gas of ammonia gas and nitrogen gas in the process of depositing the second mask layer 12, and ionizing in a nitrogen environment to deposit the second mask layer 12, wherein the refractive index of the second mask layer 12 is 1.9-2.2, and the radio frequency power in the PECVD process is 10W-60W.
In depositing the second mask layer 12 (i.e., the silicon nitride mask layer), in some implementations, a mixture of pure silane and ammonia gas may be introduced and ionized in a nitrogen environment to deposit silicon nitride. In other embodiments, a mixed gas of ammonia and nitrogen may also be introduced to avoid explosion of ammonia and increase safety.
The refractive index of the second mask layer 12 (i.e., the silicon nitride mask layer) is adjusted to 1.9-2.2 by adjusting the ratio of the gases.
The radio frequency power in the PECVD process is 10-60W, and the compactness of the second mask layer 12 (namely the silicon nitride mask layer) can be improved, so that the situation that when the compactness of the second mask layer 12 (namely the silicon nitride mask layer) is too low, oxygen atoms in air enter a non-absorption region to influence the mixing degree of a quantum well, the mixing degree of the quantum well is reduced, and the blue shift amount is reduced is avoided.
Further, in another embodiment, as shown in fig. 3, step S102 specifically includes:
s301: a second mask layer 12 with a second predetermined thickness is deposited on the ohmic contact layer 9, and the detailed structure is shown in fig. 18 and fig. 19.
The specific deposition process is the same as step S206 in the above embodiment, and is not described herein again.
S302: a photoresist is coated on the second mask layer 12.
Before coating the photoresist, a layer of adhesion promoter can be spun to increase the adhesion between the photoresist and the wafer. The photoresist can be a positive photoresist 11 or a negative photoresist, and fig. 20 and 21 are schematic structural diagrams of the positive photoresist coated on the second mask layer 12.
S303: the photoresist on the other region of the second mask layer 12 is removed to expose the second mask layer 12 in the other region, the other region of the second mask layer 12 is a region other than the second target region on the second mask layer 12, and the second target region is a region corresponding to the non-absorption region on the second mask layer 12.
Specifically, in the case where the photoresist is a positive photoresist 11, the step specifically includes:
s3021a: the photoresist on the other areas of the second mask layer 12 is exposed using a stepper electron beam or a mask reticle.
S3022a: and placing the exposed epitaxial wafer into a developing solution, removing the photoresist on other areas, and exposing the second mask layer 12 on other areas.
After the positive photoresist 11 is exposed, the solubility of the positive photoresist in the developing solution is much higher than that of the unexposed photoresist, so that the photoresist on other areas can be removed by immersing the exposed wafer in the developing solution. The time for immersing the epitaxial wafer into the developing solution is between 5 seconds and 50 seconds.
Specifically, in the case that the photoresist is a negative photoresist, the step specifically includes:
s3021b: the photoresist on the second target area of the second mask layer 12 is exposed using a stepper electron beam or a mask reticle.
S3022b: and putting the exposed epitaxial wafer into a developing solution, removing the photoresist on other areas, and exposing the second mask layer 12 in other areas.
Negative tone photoresists have the opposite photosensitive character as positive tone photoresists 11, with exposed regions less soluble than unexposed regions. When a negative photoresist is used, it is necessary to expose the photoresist of the second target area. The time for immersing the epitaxial wafer into the developing solution is between 5 seconds and 50 seconds.
After the epitaxial wafer is immersed in the developer solution to complete the development, the photoresist is patterned, as shown in fig. 22 and 23. In fig. 22, the top layer is the remained positive photoresist, that is, the photoresist 15 corresponding to the second target area is remained. The black dotted frame in the drawing in fig. 23 indicates the position where the light emitting region 14 is located.
S304: the second mask layer 12 on the other areas is removed.
After cleaning, the glass is immersed in hydrofluoric acid solution. At this time, the photoresist on the other areas on the second mask layer 12 (i.e., the silicon nitride mask layer) is removed, so that the second mask layer 12 (i.e., the silicon nitride mask layer) on the other areas is in contact with the hydrofluoric acid solution and is corroded; while the second mask layer 12 (i.e., the silicon nitride mask layer) of the second target area is protected by the photoresist. The wafer after the photoresist is removed is shown in fig. 24 and 25. As can be seen in fig. 24, only the second mask layer 16 (i.e., the silicon nitride mask layer) of the second target region is retained, the second mask layer 12 (i.e., the silicon nitride mask layer) of the other region is removed, and the underlying ohmic contact layer 9 is exposed.
S305: the photoresist remaining on the second mask layer 12 is completely removed to form a second mask layer 12 on the non-absorbing region.
In this step, the residual photoresist may be removed with a heated N-methylpyrrolidone solution. The temperature of the heated N-methyl pyrrolidone solution is kept between 30 and 90 ℃.
S306: a first mask layer 10 is deposited to a first predetermined thickness on the ohmic contact layer 9 except for the non-absorption region and the second mask layer 12, as shown in fig. 26 and 27.
Specifically, the method for depositing the first mask layer 10 may be a Plasma Enhanced Chemical Vapor Deposition (PECVD), or may be another conventional deposition method, and this embodiment is not limited thereto. The first predetermined thickness of the first mask layer 10 can be set by a worker according to actual requirements. In some implementations, the first predetermined thickness is between 20 nanometers and 500 nanometers.
The first mask layer 10 (i.e., the silicon oxide mask layer) is in contact with the ohmic contact layer 9 except for the area covered by the second mask layer 12, so that the second mask layer 12 can be formed on the ohmic contact layer 9 except for the non-absorption area, and the first mask layer 10 can be formed on the non-absorption area.
Further, in the above embodiment, as shown in fig. 4, before step S103, the method includes:
a cover slip is applied over the second mask layer 12.
The cover plate is made of GaAs, and the cover plate can prevent a large amount of As in the wafer from being separated out, so that the quality reduction of the light emitting region 14 of the wafer is relieved.
Further, in one implementation manner, the step S103 in the foregoing embodiment includes:
s401: and placing the epitaxial wafer into an annealing furnace for annealing.
S402: in the annealing process, the annealing temperature is increased from a first preset temperature to a second preset temperature within a first preset time period, and the duration of the first preset time period is less than or equal to 40 seconds.
S403: and maintaining the annealing temperature at a second preset temperature within a second preset time period, wherein the duration of the second preset time period is less than or equal to 200 seconds.
S404: and reducing the annealing temperature from the second preset temperature to the first preset temperature within a third preset time period, wherein the duration of the third preset time period is less than or equal to 30 seconds.
In this embodiment, the annealing process requires a sharp temperature rise and drop, i.e., a certain temperature is raised for a certain time, kept for a certain time, and then dropped to a certain temperature within a certain characteristic time. Generally, the time of the temperature rise process is limited within 40 seconds, and the temperature needs to rise to 700 to 1000 ℃; the time of the temperature reduction process is limited within 30 seconds, the temperature needs to be returned to the temperature before temperature rise, and the accuracy and the process quality of the annealing process can be ensured due to rapid temperature change. The time for maintaining the high temperature is determined according to the high temperature, and generally does not exceed 200 seconds. In addition, in the present application, the second mask layer 12 is formed on the light emitting region 14 of the ohmic contact layer 9, and the first mask layer 10 is formed in the non-absorption region, so that when the quantum well intermixing of the non-absorption region is promoted by using silicon nitride, the annealing temperature can be reduced to about 700 ℃, which is lower than that of other quantum well intermixing schemes without impurity induction, which is more favorable for alleviating the quantum well quality degradation of the light emitting region 14 in the annealing process, improving the yield and reliability of products, and also improving the operability of the process.
Further, in one implementation, as shown in fig. 5, step S103 in the above embodiment includes:
s501: and placing the epitaxial wafer in an annealing furnace for annealing.
S502: and in the annealing process, the annealing temperature is increased from the first preset temperature to the second preset temperature within a fourth preset time period.
S503: and maintaining the annealing temperature at the second preset temperature within a fifth preset time period, wherein the duration of the fifth preset time period is less than that of the second preset time period.
S504: and reducing the annealing temperature from the second preset temperature to the first preset temperature within a sixth preset time period.
S505: and repeating the steps S401-S405 until the repeated times reach the preset times, wherein the total time of the annealing temperature maintained at the second preset temperature is more than or equal to the time of the second preset time period.
In this embodiment, a cyclic annealing process, that is, one annealing process is divided into multiple heating-maintaining-cooling annealing processes, may be adopted. The high-temperature retention time after splitting is shorter than the high-temperature retention time before splitting, that is, the duration of the fifth preset time period is shorter than the duration of the second preset time period, but the sum of the high-temperature retention times after splitting may be longer than the high-temperature retention time before splitting. For example, an anneal at 800 degrees celsius for 60 seconds is broken down into 5 passes of an anneal at 800 degrees celsius for 15 seconds. The specific annealing temperature and time of each time can be controlled according to actual needs.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method for manufacturing a laser chip is characterized by comprising the following steps:
preparing an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate, a buffer layer, a lower limiting layer, a quantum well active layer, an upper limiting layer, a waveguide layer, a corrosion prevention layer, an upper cladding and an ohmic contact layer from bottom to top in the vertical direction, non-absorption regions are respectively arranged at two ends of the ohmic contact layer in the length direction, and a light emitting region is arranged between the two non-absorption regions;
forming a first mask layer on a region outside the non-absorption region, and forming a second mask layer on the non-absorption region;
annealing the epitaxial wafer;
removing the first mask layer and the second mask layer on the epitaxial wafer after the annealing treatment;
and carrying out subsequent wafer flowing process on the epitaxial wafer with the first mask layer and the second mask layer removed.
2. The method of claim 1, wherein forming a first mask layer on a region outside of the non-absorbing region and a second mask layer on the non-absorbing region comprises:
depositing a first mask layer with a first preset thickness on the ohmic contact layer;
coating photoresist on the first mask layer;
removing the photoresist on a first target area of the first mask layer to form a non-absorption area window, wherein the first target area is an area, corresponding to the non-absorption area, on the first mask layer;
removing the first mask layer corresponding to the non-absorption area window;
removing all the photoresist left on the first mask layer to form a first mask layer on the region outside the non-absorption region;
and depositing a second mask layer with a second preset thickness on the non-absorption region of the ohmic contact layer and the first mask layer.
3. The method of claim 2, wherein the photoresist is a positive photoresist, and the removing the photoresist from the first mask layer in a region corresponding to the non-absorbing region to form a non-absorbing region window comprises:
exposing the photoresist in the first target area of the first mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist of the first target area to form a non-absorption area window.
4. The method of claim 2, wherein the photoresist is a negative photoresist, and the removing the photoresist from the first mask layer in a region corresponding to the non-absorption region to form a non-absorption region window comprises:
exposing the photoresist of other areas of the first mask layer by using a stepping electron beam or a mask photoetching plate, wherein the other areas of the first mask layer are areas except the first target area on the first mask layer;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist of the first target area to form a non-absorption area window.
5. The method of claim 2, wherein depositing a second mask layer of a second predetermined thickness on the non-absorbing region of the ohmic contact layer and the first mask layer comprises:
and depositing a second mask layer with the thickness of 20-500 nanometers on the non-absorption region of the ohmic contact layer and the first mask layer by utilizing a PECVD (plasma enhanced chemical vapor deposition) process, introducing a mixed gas of pure silane and ammonia gas or a mixed gas of ammonia gas and nitrogen gas in the process of depositing the second mask layer, and ionizing in a nitrogen environment to deposit the second mask layer, wherein the refractive index of the second mask layer is 1.9-2.2, and the radio frequency power in the PECVD process is 10-60W.
6. The method of claim 1, wherein forming a first mask layer on a region outside the non-absorbing region and forming a second mask layer on the non-absorbing region comprises:
depositing a second mask layer with a second preset thickness on the ohmic contact layer;
coating photoresist on the second mask layer;
removing the photoresist on other areas of the second mask layer to expose the second mask layer in other areas, wherein the other areas of the second mask layer are areas on the second mask layer except for a second target area, and the second target area is an area corresponding to the non-absorption area on the second mask layer;
removing the second mask layer on the other areas;
removing all the photoresist left on the second mask layer to form a second mask layer on the non-absorption region;
and depositing a first mask layer with a first preset thickness on the ohmic contact layer in a region outside the non-absorption region and the second mask layer.
7. The method of claim 6, wherein the photoresist is a positive photoresist, and the removing the photoresist on the other region of the second mask layer to expose the second mask layer of the other region comprises:
exposing the photoresist in other areas of the second mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist on the other areas to expose the second mask layers of the other areas.
8. The method of claim 6, wherein the photoresist is a negative photoresist, and the removing the photoresist on the other regions of the second mask layer to expose the second mask layer of the other regions comprises:
exposing the photoresist on the second target area of the second mask layer by using a stepping electron beam or a mask photoetching plate;
and placing the exposed epitaxial wafer into a developing solution, and removing the photoresist on the other areas to expose the second mask layers of the other areas.
9. The method of claim 1, wherein prior to annealing the epitaxial wafer, comprising:
and covering a cover plate on the second mask layer.
10. The method of claim 1, wherein annealing the epitaxial wafer comprises:
placing the epitaxial wafer in an annealing furnace for annealing;
in the annealing process, the annealing temperature is increased from a first preset temperature to a second preset temperature within a first preset time period, wherein the duration of the first preset time period is less than or equal to 40 seconds;
maintaining the annealing temperature at the second preset temperature within a second preset time period, wherein the duration of the second preset time period is less than or equal to 200 seconds;
and reducing the annealing temperature from the second preset temperature to the first preset temperature within a third preset time period, wherein the duration of the third preset time period is less than or equal to 30 seconds.
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| CN104466671A (en) * | 2014-12-23 | 2015-03-25 | 中国科学院半导体研究所 | Semiconductor laser device and preparing method thereof |
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| Title |
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| 张亚非等编著: "《集成电路制造技术》", 上海交通大学出版社, pages: 268 - 269 * |
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