KR100422361B1 - Method for fabricating laser diode - Google Patents

Abstract

PURPOSE: A method for fabricating a laser diode is provided to prevent overhang at a lower side of a mask pattern in a mesa-etch process by improving a fabrication process. CONSTITUTION: A first type buffer layer(201), an active layer(202), and a second type buffer layer(203) are sequentially formed on a first type semiconductor substrate(200). An insulating layer is deposited on the second type clad layer. An insulating layer pattern is formed by etching the insulating layer. A resist pattern is formed on the insulating layer pattern and the second type clad layer. A mesa-etch process for the second type clad layer, the active layer, the first type buffer layer, and the first type semiconductor substrate is performed by using the resist pattern and the insulating layer pattern as etch masks.

Description

Manufacturing method of laser diode

The present invention relates to a method of manufacturing a laser diode, and more particularly, to a method of manufacturing a laser diode for reducing an overhang generated during a Mesa etching process.

In general, a laser diode using the principle of applying a current to a PN structure and causing in-phase photons to pass through a medium in the resonator and induce coherence and amplified light with coherence in a sufficiently inverted density region Is used as a compact disc, a laser printer, an optical disc memory, and a light source for optical communication.

Planar Buried Hetero-structure Laser Diode (PBH-LD) is a structure in which a planar active layer is buried between current blocking layers having a high band gap.

The PBH-LD can inject a current into the active layer to increase efficiency, increase the localization of light due to the difference in refractive index, and reduce the threshold current as well as obtain optical mode stability. However, in order to obtain these characteristics, growth of a good current blocking layer adjacent to the active layer is essential.

In order to grow such a current blocking layer, conventionally, as shown in FIG. 1A, the n-type InP buffer layer 101, the InGaAsP active layer 102, and the p-type InP clad layer 103 on the n-type substrate 100. In this stacked state, the mask pattern 104 is formed on the p-type InP cladding layer 103 so that the lower width is larger than the upper width, and then the p-type InP cladding layer is formed of an HBr-based non-selective etching solution. 103), the InGaAsP active layer 102, the n-type InP buffer layer 101, and the n-type substrate 100 are mesa-etched. Here, the mask pattern 104 is composed of a silicon oxide film formed by PECVD.

However, when the mesa etching is performed using an HBr-based solution in order to match the width of an appropriate active layer, as shown in FIG. 1B, the mask pattern 104 may be used in connection with a high lateral etching rate of the etching solution. Overhang occurs at the bottom. If the overhang is large, a smooth reaction of the reaction gases is inhibited at the subsequent growth of the current blocking layer as well as a defect occurs at the boundary (a) between the mask pattern and the p-type InP clad layer.

That is, as mentioned above, when etching based on the width of the active layer, an overhang occurs in the lower portion of the mask pattern, which consumes reactive gases during the subsequent growth of the current blocking layer, and the mask pattern and the p-type InP clad layer The reaction between the gases does not occur smoothly near the boundary, causing defects. These defects act as a path for leakage current, reducing product reliability and degrading the overall characteristics of the chip.

Accordingly, an object of the present invention is to provide a method of manufacturing a laser diode that can prevent the overhang from occurring under the mask pattern during the mesa etching process.

1A and 1B are cross-sectional views illustrating a conventional method for manufacturing a laser diode.

2A and 2C are cross-sectional views illustrating a method of manufacturing a laser diode according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100, 200: n-type substrate 101, 201: n-type InP buffer layer

102, 202: active layer 103, 203: p-type InP clad layer

104, 204: mask pattern 205: resist pattern

In order to achieve the above object, the present invention comprises the steps of: providing a first type semiconductor substrate in which a first type buffer layer, an active layer, and a second type clad layer are sequentially formed; Depositing an insulating film on the second type clad layer; Etching the insulating film to form an insulating film pattern having a lower width than the upper width; Forming a resist pattern having a predetermined size on the insulating layer pattern and the second type cladding layer to surround the insulating layer pattern; Mesa-etching a second type cladding layer, an active layer, a first type buffer layer, and a first type semiconductor substrate using the resist pattern and the insulating layer pattern as an etching mask; And it provides a method of manufacturing a laser diode comprising the step of removing the resist pattern.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2A and 2C are cross-sectional views illustrating a method of manufacturing a laser diode according to an embodiment of the present invention.

As shown in FIG. 2A, in the state where the n-type InP buffer layer 201, the InGaAsP active layer 202, and the p-type InP cladding layer 203 are sequentially formed on the n-type substrate 200, the p-type InP clad An insulating film made of a silicon oxide film or a silicon nitride film is deposited on the layer 203 by plasma enhanced CVD (PECVD). Then, the insulating film made of the silicon oxide film or the silicon nitride film is etched to form a tapered insulating film pattern, that is, a mask pattern 204 having a lower width than the upper width. In this case, the mask pattern 204 is formed to have a narrower width than the conventional mask pattern.

As shown in FIG. 2B, a resist pattern 205 having a predetermined size covering the mask pattern 204 is coated by applying a resist on the mask pattern 204 and the n-type InP clad layer 203 and exposing and developing the resist. To form. In this case, an accurate alignment is required for the symmetry of the resist pattern 205 during the exposure process. Then, the p-type InP cladding layer 203, the InGaAsP active layer 202, the n-type InP buffer layer 201, and the n-type substrate 200 are mesa-etched using the non-selective etching solution. In this case, while the mesa etching proceeds in the lateral direction, first, the resist pattern 205 serves as an etching mask, and after some etching is performed, the mask pattern 204 serves as an etching mask. Accordingly, the present invention can suppress or reduce the occurrence of overhangs under the mask pattern, compared to the conventional case in which mesa etching is performed using only the mask pattern.

As shown in FIG. 2C, the resist pattern is removed with an organic solvent, thereby obtaining a mesa structure. Then, the surface treatment is performed to form a current blocking layer.

The subsequent process is the same as before.

As described above, the present invention forms a resist pattern including a mask pattern formed of a conventional silicon oxide layer to implement mesa etching to implement a mesa shape of PBH-LD, thereby reducing an overhang under the mask pattern and providing a current. It is possible to improve the overall characteristics of the chip by suppressing defects that may occur when forming the barrier layer.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims (5)

Providing a first type semiconductor substrate in which a first type buffer layer, an active layer, and a second type clad layer are sequentially formed; Depositing an insulating film on the second type clad layer; Etching the insulating film to form an insulating film pattern having a lower width than the upper width; Forming a resist pattern having a predetermined size on the insulating layer pattern and the second type cladding layer to surround the insulating layer pattern; Mesa etching the second type cladding layer, the active layer, the first type buffer layer, and the first type semiconductor substrate using the resist pattern and the insulating layer pattern as an etching mask; And And removing the resist pattern. The method of claim 1, wherein the insulating film is a silicon oxide film or a silicon nitride film. The method of manufacturing a laser diode according to claim 1, wherein the resist pattern is removed with an organic solvent. The method of claim 1, wherein the buffer layer and the cladding layer are InP layers. The method of claim 1, wherein the active layer is an InGaAsP layer.

Images