KR19990003158A - Manufacturing method of laser diode - Google Patents

Abstract

The present invention is directed to a method of manufacturing a laser diode for reducing the overhang generated during the mesa etching process, the first type substrate; A first type InP buffer layer; InGaAsP active insects; And a wafer having a structure in which a second type InP cladding layer is sequentially stacked, wherein an insulating film is deposited on the second type InP cladding layer, and then a lower width thereof is greater than an upper width through a photolithography process. Forming an insulating film pattern having a predetermined size in a tapered shape; Applying a resist on the entire structure, and forming a resist pattern having a predetermined size including the insulating layer pattern through a photographic process; Mesa etching a lower wafer using the resist pattern; And removing the resist pattern.

Description

Manufacturing method of laser diode

The present invention relates to a method of manufacturing a laser diode, and more particularly, to a method of manufacturing a laser diode for reducing the overhang generated during the mesa etching process.

In general, a laser diode using the principle of applying a current to a PN structure and causing in-phase photons to pass through a medium in the resonator and have coherence and induced emission and amplified light in a sufficiently inverted density region Is used as a compact disc, a laser printer, an optical disc memory, and a light source for optical communication. Planar Buried Hetero-structure Laser Diode (PBH-LD) is a structure in which a planar active layer is buried between a current blocking layer having a high band gap. Injecting can increase efficiency, increase the localization of light due to the difference in refractive index, reduce the threshold current, and obtain optical mode stability. However, in order to obtain these characteristics, growth of a good current blocking layer adjacent to the active layer is essential.

In order to grow such a current blocking layer, a wafer having a structure in which an n-type substrate 100, an n-type InP buffer layer 101, an InGaAsP active layer 102, and a p-type InP lower clad layer 103 are sequentially stacked as shown in FIG. 1A. After forming a mask pattern 104 for mesa etching, and then etched with a non-selective etching solution of HBr system. At this time, the mask pattern 104 is composed of a silicon oxide film formed by PECVD. However, when etching using the HBr-based solution in order to match the width of the appropriate active layer, an overhang occurs under the mask pattern 104 because the lateral etching speed of the etching solution is high. If this overhang is large, a smooth reaction of the reaction gases at the lower portion thereof is inhibited at the time of subsequent growth of the current blocking layer, and in particular, defects are generated at the boundary a between the mask pattern and the lower wafer.

As mentioned above, when etching based on the width of the active layer, an overhang occurs in the lower portion of the mask pattern, which consumes reactant gases in the subsequent growth of the current blocking layer and between the gases near the boundary of the mask pattern and the wafer. The reaction does not occur smoothly, causing defects. These defects act as a path for leakage current, which lowers the reliability of the product and reduces the overall characteristics of the chip.

Accordingly, an object of the present invention is to provide a method of manufacturing a laser diode that can suppress a defect and improve chip characteristics by reducing an overhang by using a silicon oxide film and a resist as a mask pattern during mesa etching of a wafer.

1A and 1B are sectional views showing a process of forming a mesa shape of a conventional PBH-LD wafer.

2A and 2C are cross-sectional views illustrating a process of forming a mesa shape of a PBH-LD wafer according to the present invention.

* Explanation of symbols for the main parts of the drawings

100, 200: n-type substrate, 102, 202: active layer, 104, 204: mask pattern, 101, 201: n-type InP buffer layer, 103, 203: p-type InP clad layer, 205: resist pattern

In order to achieve the above object, the first type substrate according to the present invention; A first type InP buffer layer; InGaAsP active layer; And a wafer having a structure in which a second type InP cladding layer is sequentially stacked, wherein an insulating film is deposited on the second type InP cladding layer, and then a lower width thereof is greater than an upper width through a photolithography process. Forming an insulating film pattern having a predetermined size in a tapered shape; Applying a resist on the entire structure, and forming a resist pattern having a predetermined size including the insulating layer pattern through a photographic process; Mesa-etching a lower wafer using the resist pattern; And removing the resist pattern.

EXAMPLE

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

2A and 2C are cross-sectional views of forming a mesa structure of a laser diode according to an embodiment of the present invention. As shown in Fig. 2A, PECVD (Plasma) on a wafer having a structure in which an n-type substrate 200, an n-type InP buffer layer 201, an InGaAsP active layer 202, and a p-type InP clad layer 203 are sequentially stacked. A silicon oxide film or a silicon nitride film is deposited using an enhanced CVD method. Then, in order to mesa etch the wafer, a mask pattern 204 having a tapered shape with a lower width wider than an upper width is formed through a photolithography process on the silicon oxide film or silicon nitride film. At this time, the width of the formed mask pattern is formed to be narrower than before. Subsequently, a resist is applied on the entire structure, and the resist pattern 205 is broadly formed to include the mask pattern through a photographic process. Accurate alignment is required in the photographic process for the symmetry of this resist pattern. Then, mesa etching is performed with a non-selective etching solution. In this case, the mesa etching is performed laterally as shown in FIG. 2B, while the resist pattern 205 serves as an etching mask, and when the etching is performed to some extent, the mask pattern 204 serves as an etching mask. Subsequently, if the resist is removed with an organic solvent, a mesa shape as shown in Fig. 2C can be obtained. Then, surface treatment is performed to form a current blocking layer. The subsequent steps are the same as before.

As described above, the present invention forms a resist pattern including a mask pattern formed of a conventional silicon oxide film in order to realize the mesa shape of the PBH-LD, thereby reducing the overhang under the mask pattern and forming a current blocking layer. Suppress defects that may occur during formation to improve the overall characteristics of the chip.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims (5)

A first type substrate; Type l buffer layer: active layer; And a wafer having a structure in which a second type cladding layer is sequentially stacked. Depositing an insulating film on the second cladding layer, and then forming an insulating film pattern having a predetermined size in which a lower width is tapered so that a lower width is wider than an upper width through a photolithography process; Applying a resist on the entire structure, and forming a resist pattern having a predetermined size including the insulating layer pattern through a photographic process; Mesa etching a lower wafer using the resist pattern; And And removing the resist pattern. The method of claim 1, wherein the insulating film is a silicon oxide film or a silicon nitride film. The method of manufacturing a laser diode according to claim 1, wherein the resist pattern is removed with an organic solvent. The method of claim 1, wherein the buffer layer and the cladding layer are IrP layers. The method of claim 1, wherein the active layer is an InGaAsP layer.