CN115394721A - 集成电路的制造方法 - Google Patents

集成电路的制造方法 Download PDF

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Publication number
CN115394721A
CN115394721A CN202210705786.1A CN202210705786A CN115394721A CN 115394721 A CN115394721 A CN 115394721A CN 202210705786 A CN202210705786 A CN 202210705786A CN 115394721 A CN115394721 A CN 115394721A
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layer
metal gate
transistor
semiconductor
type
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黄懋霖
朱龙琨
徐崇威
余佳霓
江国诚
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路的制造方法，包括形成N型及P型全绕式栅极晶体管以及核心全绕式栅极晶体管。上述方法沉积用于P型晶体管的金属栅极层。上述方法与P型晶体管的金属栅极层一起原位形成钝化层。

Description

集成电路的制造方法
技术领域
本公开是关于半导体制造的领域。本公开特别是关于在集成电路中形成全绕式栅极晶体管。
背景技术
对于改善电子装置的运算能力有持续的需求，上述电子装置包括智能手机、平板、台式电脑、笔记本电脑及许多其他类型的电子装置。集成电路提供了用于这些电子装置的运算能力。改善集成电路中的运算能力的一种方式为：增加能够包含在半导体基板的一给定区域的晶体管及其他集成电路部件的数目。
集成电路可以包括N型晶体管及P型晶体管。N型及P型晶体管的栅极电极可以使用不同的材料及制程。对于全绕式栅极晶体管，在形成N型及P型晶体管的栅极金属时会出现问题。
发明内容
一种集成电路的制造方法，包括：形成对应P型全绕式栅极晶体管的多个通道区的多个半导体纳米片；在半导体纳米片上沉积界面介电层；在界面介电层上沉积高介电常数介电层；在高介电常数介电层上以及半导体纳米片之间沉积金属栅极层；沉积金属栅极层并在金属栅极层上原位沉积钝化层；以及在钝化层上沉积金属栅极填充材料。
一种集成电路的制造方法，包括：形成对应N型全绕式栅极晶体管的多个通道区的多个第一半导体纳米片；形成对应P型全绕式栅极晶体管的多个通道区的多个第二半导体纳米片；在第一及第二半导体纳米片上沉积界面介电层；在界面介电层上沉积高介电常数介电层；在第一及第二半导体纳米片的高介电常数介电层上沉积第一金属栅极层；从第二半导体纳米片上的高介电常数介电层移除第一金属栅极层；在第二半导体纳米片的高介电常数介电层上沉积第二金属栅极层；以及沉积第二金属栅极层并在第二金属栅极层上原位沉积钝化层。
一种集成电路，包括：N型全绕式栅极晶体管，包括：多个第一半导体纳米片，对应N型全绕式栅极晶体管的多个通道区；界面介电层，位于第一半导体纳米片上；高介电常数介电层，位于界面介电层上；第一金属栅极层，直接位于高介电常数介电层上；以及第二金属栅极层，位于第一金属栅极层上；以及P型全绕式栅极晶体管，包括多个第二半导体纳米片，对应P型全绕式栅极晶体管的多个通道区；界面介电层，位于第二半导体纳米片上；高介电常数介电层，位于界面介电层上；第二金属栅极层，直接位于高介电常数介电层上；以及原位钝化层，位于第二金属栅极层上。
附图说明
图1A～图1F是根据一个实施例，绘示出集成电路在制造的各种阶段的剖面图。
图2是根据一个实施例，绘示出集成电路的剖面图。
图3是根据一个实施例，绘示出集成电路的形成方法的流程图。
图4是根据一个实施例，绘示出集成电路的形成方法的流程图。
其中，附图标记说明如下：
100，200：集成电路
102：基板
104，106：晶体管
108：纳米片
110，132：界面介电层
112：高介电常数介电层
114：第一金属栅极层(第一栅极金属层)
116：光阻(光阻层)
118：第二金属栅极层(第二栅极金属层，金属栅极层)
120：钝化层
122：第三金属栅极层(第三栅极金属层，金属栅极层)
126：浅沟槽隔离
128：源极及漏极区
130：硅化物区
134：接触插塞
136：侧壁间隔物
138：间隔物
F：剖面线
具体实施方式
在以下的描述中，描述许多厚度及材料以用于集成电路晶粒内的各种膜层及结构。借由用于各种实施例的范例的方式给出特定的尺寸及材料。技术领域中具有通常知识者将理解，关于本公开，可以在许多情况中使用其他的尺寸及材料且不偏离本公开的范围。
以下公开提供了许多的实施例或范例，用于实施所提供的标的物的不同元件。各元件和其配置的具体范例描述如下，以简化本发明实施例的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明实施例可能在各种范例中重复参考数值以及/或字母。如此重复是为了简明和清楚的目的，而非用以表示所讨论的不同实施例及/或配置之间的关系。
再者，其中可能用到与空间相对用词，例如“在……之下”、“下方”、“较低的”、“上方”、“较高的”等类似用词，是为了便于描述图式中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。
在以下描述中，记载某些特定的细节以提供本公开的各种实施例的透彻理解。然而，技术领域中具有通常知识者将理解，可以在不具有这些特定的细节的情况下实施本公开。在其他范例中，与电子组件及制造技术相关的现有结构并未详细描述以避免不必要地混淆本公开的实施例的描述。
除非本文另有需要，在以下的说明书及权利要求书中，“包括”一词及其变体，例如“包含”及“含有”，是以开放、包容的意义解释，即“包括，但不限于”。
例如第一、第二及第三等序数的使用并不一定意味着排序的顺序感，而是可以仅区分行为或结构的多个实例。
在整个说明书中对“一些实施例”或“一个实施例”的引用意味着结合实施例描述的特定特征、结构或特性被包括在至少一些实施例中。因此，在这整个说明书的各种地方的短语“在一些实施例中”、“在一个实施例中”、或“在一些实施例中”不一定都是指相同的实施例。此外，特定特征、结构、或特性可以在一或多个实施例中以任何适合的方式组合。
如在本说明书及所附的权利要求书中所使用的，单数形式“一”、“一个”、及“该”包括复数指示物(referents)，除非内容另有明确规定。也应注意的是，除非内容另有明确规定，用语“或”通常以其包括“及/或”的含义使用。
本公开的实施例提供包括P型及N型晶体管的集成电路。P型晶体管包括薄金属栅极层上的钝化层。钝化层是与薄金属栅极层原位形成，借此防止薄金属栅极层的氧化。其结果为，P型晶体管在栅极中具有高功函数、低临界电压、及低整体电阻。这带来了运行较佳的集成电路、较高的晶圆产率、以及报废率较低的晶圆或晶粒。
图1A～图1F是根据一个实施例，绘示出集成电路100在制造的连续的中间阶段的剖面图。图1A～图1F绘示出用于制造包括N型及P型纳米片晶体管的集成电路的例示性制程。图1A～图1F是根据本公开的原理，绘示出这些类型的晶体管可以如何在简单且有效的制程中形成。可以使用其他的制程步骤以及制程步骤的组合且不偏离本公开的范围。
图1A是根据一个实施例，绘示出集成电路100在制造的中间阶段的剖面图。图1A的视图绘示出晶体管104及晶体管106。晶体管104及106形成于同一集成电路100中，尽管它们可以位于集成电路100的不同区域。在一个范例中，晶体管104为N型晶体管且晶体管106为P型晶体管。
集成电路100可以包括以复杂的排列耦合在一起的大量的N型晶体管104及P型晶体管106。N型晶体管104及P型晶体管106协作处理数据、将数据写入存储器、从存储器读取数据、以及执行软件指令。N型及P型晶体管可以借由形成于集成电路100中的金属内连线耦合在一起。
晶体管104及106为全绕式栅极晶体管。全绕式栅极晶体管结构可以借由任何适合的方法来图案化。举例而言，可以使用一或多个微影制程图案化上述结构，包括双重图案化或多重图案化制程。一般来说，双重图案化或多重图案化制程结合了微影制程与自对准制程，以创建出例如，比使用单一、直接微影制程所得的节距更小的图案。例如，在一实施例中，在基板上方形成牺牲层，并使用微影制程对其进行图案化。使用自对准制程在图案化的牺牲层旁边形成间隔物。之后去除牺牲层，然后可以使用剩余的间隔物图案化全绕式栅极结构。
集成电路100包括半导体基板102。在一个实施例中，基板102在至少一表面部分上包括单晶半导体层。基板102可以包括单晶半导体材料，例如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。基板102可以在其表面区域中包括一或多个缓冲层(未显示)。缓冲层能够用以逐渐改变从基板到源极/漏极区的晶格常数。缓冲层可以由外延成长单晶半导体材料所形成，上述单晶半导体材料为例如但不限于Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP、及InP。在一特定的实施例中，基板102包括在硅基板102上外延成长的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从最底缓冲层的30原子％锗增加到最顶缓冲层的70原子％锗。基板102可以包括适当地以杂质(例如，p型或n型传导性)掺杂的各种区域。上述掺质为例如用于n型晶体管的硼(BF2)以及用于p型晶体管的磷。
集成电路100可以包括一或多个浅沟槽隔离(未显示)，其分隔N型晶体管104与P型晶体管106，或将N型晶体管104彼此分隔并将P型晶体管106彼此分隔。浅沟槽隔离可以用于分隔与半导体基板102一起形成的晶体管结构的群组。浅沟槽隔离可以包括介电材料。用于浅沟槽隔离的介电材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、氟掺杂硅酸盐玻璃(fluorine-doped silicate glass，FSG)、或低介电常数介电材料，且借由LPCVD(low pressure chemical vapor deposition)、等离子体辅助CVD或流动式CVD所形成。其他的材料及结构可以用于浅沟槽隔离且不偏离本公开的范围。
集成电路100包括多个半导体纳米片108或纳米线。半导体纳米片108为半导体材料的膜层。半导体纳米片108对应晶体管104及106的通道区。半导体纳米片108形成于基板102上。半导体纳米片108可以包括一或多层的Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。在一个实施例中，半导体纳米片108是与基板102相同的半导体材料。其他的半导体材料可以用于半导体纳米片108且不偏离本公开的范围。
在图1A中，各个晶体管104及106具有三个纳米片108。然而，实际上，各个晶体管104及106可以具有多于三个的半导体纳米片108。举例而言，各个晶体管104可以包括3到20个半导体纳米片108。可以使用其他数目的半导体纳米片且不偏离本公开的范围。
纳米片108的宽度可以在10nm及50nm之间。纳米片108的厚度可以在4nm及10nm之间。纳米片108之间的距离可以在8nm及15nm之间。其他的尺寸可以用于半导体纳米片108且不偏离本公开的范围。
各个纳米片108被界面介电层110覆盖。可以使用界面介电层110以在半导体纳米片108与后续的介电层之间产生良好的界面，如以下所进一步详述。界面介电层110可以协助抑制电荷载子在半导体纳米片108中的移动率劣化，其中半导体纳米片108用作晶体管104及106的通道区。
界面介电层110可以包括介电材料，例如氧化硅、氮化硅、或其他适合的介电材料。相对于可以用于晶体管的栅极介电质中的例如氧化铪或其他高介电常数介电材料的高介电常数的介电质，界面介电层110可以包括相对低介电常数的介电质。在图1A的范例中，界面介电层110为二氧化硅。
界面介电层110可以借由热氧化制程、化学气相沉积(CVD)制程、或原子层沉积(ALD)制程。界面介电层110可以具有0.1nm及2nm之间的厚度。选择界面介电层110的厚度的一个考虑因素为：在纳米片108之间为栅极金属留下足够的空间，如以下所进一步详述。其他的材料、沉积制程、及厚度可以用于界面介电层110且不偏离本公开的范围。
界面介电层110被高介电常数介电层112覆盖。高介电常数介电层112及界面介电层110一起形成晶体管晶体管104及106的栅极介电质。高介电常数介电层112及界面介电层110将半导体纳米片108与将在后续步骤中沉积的栅极金属分隔。高介电常数介电层112及界面介电层110将栅极金属与对应晶体管的通道区的半导体纳米片108隔离。
高介电常数介电层112包括一或多层的介电材料，例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪－氧化铝(HfO2-Al2O3)合金、其他适合的高介电常数介电材料、及/或前述的组合。高介电常数介电层112可以包括第一层及第二层，第一层包括HfO2与包括La及Mg的偶极掺杂，第二层包括具有结晶的较高介电常数的ZrO层。
高介电常数介电层112可以借由CVD、ALD、或任何适合的方法形成。在一个实施例中，高介电常数介电层112是使用高度顺应性的沉积制程所形成，例如ALD，借此确保栅极介电层的形成在各个半导体纳米片108周围具有一致的厚度。在一个实施例中，高介电常数介电质的厚度在从1nm到约3nm的范围内。其他的厚度、沉积制程、及材料可以用于高介电常数介电层112且不偏离本公开的范围。
在一个实施例中，在图1A所示的制造的阶段，界面介电层110在N型晶体管104及P型晶体管106两者的纳米片108上具有相同的厚度。因此，在图1A所示的制造阶段，可以在同一沉积步骤中将界面介电层110沉积在N型晶体管104及P型晶体管106的纳米片108上。同样地，可以在同一沉积步骤或制程中将高介电常数介电层112形成于晶体管104及106的界面介电层110上。高介电常数介电层112可以在晶体管104及106中具有相同的厚度。
图1B是根据一个实施例，绘示出集成电路100在制造的中间阶段的剖面图。在图1B中，在N型晶体管104及P型晶体管106两者的高介电常数介电层112上沉积第一金属栅极层114。第一金属栅极层114可以包括TiC、TiAlC、TaC、TaAlC、TaSiAlC、TiSiAlC或其他适合的材料中的一或多个。第一金属栅极层114可以具有0.1nm及10nm之间的厚度。选择第一金属栅极层114的厚度以在晶体管104及晶体管106两者的邻近的纳米片108之间留下间隙。第一金属栅极层114可以借由物理气相沉积(PVD)制程、ALD制程、CVD制程、或其他适合的沉积制程所形成。第一金属栅极层114可以具有其他的厚度、材料、及沉积制程且不偏离本公开的范围。
第一金属栅极层114为用于N型晶体管104的薄栅极金属。第一金属栅极层在半导体纳米片108周围沉积在高介电常数介电层112上。选择第一金属栅极层的材料以协助给N型晶体管104提供所需的功函数。在一个实施例中，第一金属栅极层114不赋予P型晶体管106所需的功函数及临界电压特性。
因此，在图1B中，沉积并图案化光阻116的膜层。光阻116的膜层被图案化以在P型晶体管106的半导体纳米片108的高介电常数介电层112上露出第一金属栅极层114。N型晶体管104的第一金属栅极层114被光阻116的膜层覆盖。光阻116的膜层可以借由标准的光阻沉积技术来沉积，包括气相沉积、扩散沉积(spread deposition)、旋转涂布，或借由其他适合的制程来沉积。可以借由通过微影遮罩曝光光阻116的膜层以图案化光阻116的膜层。因此，光阻116的膜层可以使用标准的微影技术沉积并图案化。
图1C是根据一些实施例，绘示出集成电路100在制造的中间阶段的剖面图。在图1C中，已在集成电路100上进行蚀刻制程。特别是，在集成电路100的并未被光阻116覆盖的部分上进行蚀刻制程。上述蚀刻制程从晶体管106蚀刻第一金属栅极层114。上述蚀刻制程可以包括在所有方向上均等地蚀刻第一金属栅极层114及硬遮罩层116的等向性蚀刻制程。选择蚀刻制程的持续时间以从晶体管106的纳米片108完全移除第一金属栅极层114。上述蚀刻制程可以包括湿蚀刻、干蚀刻、原子层蚀刻(atomic layer etching，ALE)制程、定时蚀刻(timed etch)、或其他适合的蚀刻制程。第一金属栅极层114依然存在于N型晶体管104的高介电常数介电层112上，因为N型晶体管104在蚀刻制程时被光阻116覆盖。
图1D是根据一些实施例，绘示出集成电路100在制造的中间阶段的剖面图。在图1D中，光阻层116已被移除光阻层116可以借由等离子体灰化制程(plasma ash process)来移除。可以使用其他的移除制程移除光阻层116且不偏离本公开的范围。
在图1D中，在光阻层116的移除之后沉积第二金属栅极层118。第二金属栅极层118被沉积在晶体管104及晶体管106两者上。特别是，第二金属栅极层118被沉积在N型晶体管104的第一金属栅极层114上。第二金属栅极层118填充N型晶体管104的半导体纳米片108之间的任何剩余的间隙。
第二金属栅极层118被直接沉积在P型晶体管106的高介电常数介电层112上。这是因为从P型晶体管106的高介电常数介电层112移除第一金属栅极层的蚀刻制程露出了P型晶体管106的高介电常数介电层112。因此，第二金属栅极层118被直接沉积在P型晶体管106的高介电常数介电层112上。
第二金属栅极层118是用于P型晶体管106的薄栅极金属。因此，第二金属栅极层118可以被称为P金属栅极层。选择P金属栅极层的材料及厚度以产生P型晶体管106的所需功函数。第二金属栅极层是最接近P型晶体管106的半导体纳米片108的导电层。因此，第二金属栅极层118强烈地影响P型晶体管106的功函数及整体的临界电压。选择第二金属栅极层118的材料以给P型晶体管106带来较高的功函数。P型晶体管106的高功函数导致P型晶体管的低临界电压。对于N型晶体管104，较低的功函数导致更低的临界电压。因此，选择第一金属栅极层114以具有相对低的功函数，使得N型晶体管104具有低临界电压。
第二金属栅极层118可以包括TiN、TaN、WCN、MoN、或其他适合的材料中的一或多个。第二金属栅极层118可以具有0.1nm及10nm之间的厚度。选择第二金属栅极层118的厚度以在晶体管104及晶体管106两者的邻近的纳米片108之间留下间隙。第二金属栅极层118可以借由物理气相沉积(PVD)制程、ALD制程、CVD制程、或其他适合的沉积制程来沉积。第二金属栅极层118可以具有其他的厚度、材料、及沉积制程且不偏离本公开的范围。
当形成第二金属栅极层118时的一个考虑因素为：第二金属栅极层118的潜在氧化。如果第二金属栅极层118氧化，P型晶体管106的功函数可能会降低。这是因为如果第二金属栅极层118被氧化，氧、碳、及氟的原子或化合物可以扩散通过第二金属栅极层118。这会降低P型晶体管106的功函数并增加P型晶体管106的临界电压。
用于防止第二金属栅极层118氧化的一个潜在解决方法为在第二金属栅极层118上形成钝化层。钝化层能够防止氧、碳、及氟扩散穿过第二金属栅极层118。然而，如果钝化层是在与第二栅极金属层118钝化层的沉积分开的制程中被沉积，钝化层的形成本身可能会造成第二金属栅极层118的氧化。
借由与第二金属栅极层118的沉积一起原位沉积钝化层120，本公开的原理克服了其他潜在解决方法的缺点。钝化层120与第二金属栅极层118的原位沉积确保了在钝化层120的沉积之前没有氧被引入第二金属栅极层118的环境。因此，在钝化层120的沉积之前，将没有第二金属栅极层118的氧化。在一个范例中，钝化层120完全禁止例如氧、碳、及氟的元素穿透到第二金属栅极层118中。钝化层120可以禁止所有这种不想要的粒子或元素穿透过钝化层120的表面。在这个情况中，在钝化层120内的不想要的粒子的浓度实质上为零。
在一个实施例中，沉积钝化层120且不破坏来自第二金属栅极层118的沉积的真空条件。这对应了钝化层120的原位沉积。钝化层120的沉积可以在与第二金属栅极层118的沉积相同的沉积腔室中进行且不破坏真空。替代地，钝化层120可以在与第二金属栅极层118的沉积分开的沉积腔室中进行且不破坏真空。在这个情况中，借由管(tube)连接两个沉积腔室。上述管造成上述沉积腔室流体相通(in fluid communication)，使得上述腔室中的压力将大约相等。在第一沉积腔室中沉积第二金属栅极层118之后，包括集成电路100的晶圆可以借由机器手臂通过上述管转移到第二沉积腔室。第一及第二沉积腔室相通地耦合，使得存在于第一沉积腔室中的真空条件也存在于第二沉积腔室中。钝化层120可以接着在第二沉积腔室中被沉积且不破坏真空。这也对应了钝化层120的原位沉积。
在一个范例中，以ALD制程沉积第二金属栅极层。可以在沉积第二金属栅极层118的ALD制程之后立即开始ALD制程以沉积钝化层120，且不破坏真空条件。因此，在钝化层120的沉积之前，第二金属栅极层118并未暴露于任何氧。这确保了第二金属栅极层118将不氧化。这个制程能够导致功函数大于或等于4.9eV。这个制程的第二个好处为：P型晶体管106的金属栅极的整体电阻非常低，因为没有产生第二金属栅极层118的氧化。
钝化层120可以包括TaN、TaN及TiN的组合、WCN及TiN的组合、Al、AlOx、Si、SiOx、SiOn、SiN、或其他适合的材料中的一或多个。钝化层120可以具有0.1nm及10nm之间的厚度。在一个范例中，如果钝化层120比0.1nm薄，可能不足以防止掺质扩散到第二金属栅极层118中。在一个范例中，如果钝化层120比10nm厚，可能不具有足够的空间以用于后续的填充制程。钝化层120可以借由ALD或PVD来沉积。钝化层120可以具有其他的厚度、材料、及沉积制程且不偏离本公开的范围。
第二金属栅极层118在N型晶体管104位于第一金属栅极层114上。钝化层120在晶体管104位于第二金属栅极层118上。因此，晶体管104包括第一金属栅极层114及第二金属栅极层118两者。
图1E是根据一个实施例，绘示出集成电路100的剖面图。在图1E中，第三金属栅极层122在N型晶体管104及P型晶体管106两者被沉积在钝化层120上。第三金属栅极层122为栅极填充材料。栅极填充材料填充纳米片108周围的剩余间隙。栅极填充材料也填充沟槽，借此提供用于晶体管104及106的栅极，如关于图1F所更清楚地绘示。
在图1E的视图中，将第三金属栅极层122绘示为单一的栅极金属。然而，实际上，第三金属栅极层122可以包括多个分隔的金属层。第三金属栅极层122可以包括W、Co、Mo、或其他适合的材料。最初的金属栅极层及栅极填充材料共同构成第三金属栅极层122。第三金属栅极层122可以以一或多个沉积制程沉积，包括PVD、CVD、ALD、或其他适合的沉积制程。其他材料、膜层的类型、及沉积制程可以用于第三金属栅极层122且不偏离本公开的范围。
参照沿着金属栅极方向的剖面图，第二金属栅极层118在N型晶体管104中在两个邻近的纳米片108之间合并。在P型晶体管106中，第二金属栅极层118不在邻近的纳米片之间合并。这是因为第一金属栅极层114在N型晶体管中的存在以及第一栅极金属层114在P型晶体管中的不存在所造成。
图1F是根据一个实施例，绘示出集成电路100的剖面图。图1F的视图是沿着图1E的剖面线F。图1F的视图更完整地绘示出晶体管106的整体结构。N型晶体管104的结构将实质上类似于P型晶体管106的结构，除了已经绘示的差异以及半导体区域的掺杂上的差异。
图1F绘示出邻近半导体基板102的浅沟槽隔离126。浅沟槽隔离126可以用于分隔与半导体基板102一起形成的晶体管结构的群组。浅沟槽隔离126可以包括介电材料。用于浅沟槽隔离126的介电材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、SiCN、氟掺杂硅酸盐玻璃(FSG)、或低介电常数介电材料，且借由低压CVD(low pressure CVD，LPCVD)、等离子体CVD(plasma-CVD)或流动式CVD所形成。其他的材料及结构可以用于浅沟槽隔离126且不偏离本公开的范围。
集成电路100包括源极及漏极区128。源极及漏极区128包括半导体材料。源极及漏极区128可以从半导体纳米片108外延成长。源极及漏极区128可以从半导体纳米片108外延成长或在形成纳米片108之前从基板102外延成长。在N型晶体管的情况下，源极及漏极区128可以以N型掺质物种掺杂。在P型晶体管的情况下，源极及漏极区128可以以P型掺质物种掺杂。
纳米片108在源极及漏极区128之间延伸。如上所述，纳米片108对应N型晶体管104的通道区。借由施加所选的电压到第三金属栅极层122及源极及漏极区128，电流流过源极及漏极区128之间的纳米片108。
图1F也绘示出位于源极及漏极区128与第三金属栅极层122之间的介电间隔物138。更具体地，间隔物138位于高介电常数介电层112与源极及漏极区128之间。间隔物138可以包括一或多个介电材料，包括氮化硅、SiON、SiOCN、SiCN、氧化硅、或其他介电材料。其他的介电材料可以用于间隔物138且不偏离本公开的范围。
图1F的视图绘示出与半导体纳米片108接触的界面介电层110。高介电常数介电层112与界面介电层110接触。第三金属栅极层122与高介电常数介电层112接触。
集成电路100包括位于源极及漏极区128上的界面介电层132。界面介电层132可以包括氧化硅、氮化硅、SiCOH、SiOC、或有机聚合物中的一或多个。其他类型的介电材料可以用于界面介电层132且不偏离本公开的范围。
集成电路100包括硅化物区130，其形成于源极及漏极区128中。硅化物区130可以包括硅化钛、硅化钴、或其他类型的硅化物。接触插塞134形成于界面介电层132中。接触插塞134可以包括钴或另一个适合的导电材料。接触插塞134可以用于施加电压到晶体管104的源极及漏极区128。接触插塞134可以被氮化钛粘着层围绕。
第三金属栅极层122被沉积在形成于层间介电层132中的沟槽中。第三金属栅极层122也围绕纳米片108，如图1E所示。侧壁间隔物136在层间介电层132中的沟槽中位于第三金属栅极层122的周围。侧壁间隔物136可以包括多个介电层，包括氮化硅、氧化硅、碳化硅、或其他适合的介电材料中的一或多个。高介电常数介电层112也位于侧壁间隔物136与第三金属栅极层122之间的沟槽的侧壁上。其他的材料、结构、及特征可以被包括在全绕式栅极N型晶体管104中，且对应地，被包括在全绕式栅极P型晶体管106中且不偏离本公开的范围。
图2是根据一个实施例，绘示出集成电路200的剖面图。集成电路200包括N型晶体管104及P型晶体管106。集成电路200与图1E的集成电路实质上类似，除了钝化层120不存在于N型晶体管104上。钝化层120只存在于P型晶体管106上。
在一个范例中，直到图1D的视图为止，用于形成集成电路200的制程与用于形成集成电路100的制程实质上相同。对于集成电路200，可以在P型晶体管106上形成遮罩，使N型晶体管104露出。接着可以在遮罩的存在下进行蚀刻制程以从N型晶体管104移除钝化层120。接着可以从P型晶体管106移除遮罩。接着可以如图1E所描述地沉积第三栅极金属层122。其结果为图2所示的结构。各种其他的制程可以用于形成图2的集成电路200，且不偏离本公开的范围。钝化层120有助于确保P型晶体管106的高功函数。这一部分是基于防止第二栅极金属层118的氧化，如上所述。此外，钝化层120本身可以增加P型晶体管106的功函数。钝化层120不存在于N型晶体管104可以造成N型晶体管104的功函数降低。
图3是根据一个实施例，绘示出用于形成集成电路的方法300的流程图。方法300可以使用关于第1A～1F、2图所公开的结构、制程、及组件。在步骤302，方法300包括形成对应N型全绕式栅极晶体管的通道区的多个第一半导体纳米片。N型全绕式栅极晶体管的一个范例为图1A～图1F的全绕式栅极晶体管104。第一半导体纳米片的一个范例为图1A～图1F的晶体管104的半导体纳米片108。在步骤304，方法300包括形成对应P型全绕式晶体管的通道区的多个第二半导体纳米片。P型全绕式栅极晶体管的一个范例为图1A～图1F的全绕式栅极晶体管106。第二半导体纳米片的一个范例为图1A～图1F的晶体管106的半导体纳米片108。在步骤306，方法300包括在第一及第二半导体纳米片上沉积界面介电层。界面介电层的一个范例为图1A的界面介电层110。在步骤308，方法300包括在界面介电层上沉积高介电常数介电层。高介电常数介电层的一个范例为图1A的高介电常数介电层112。在步骤310，方法300包括第一及第二半导体纳米片的高介电常数介电层上的第一金属栅极层。第一金属栅极层的一个范例为图1B的第一金属栅极层114。在步骤312，方法300包括从第二半导体纳米片上的高介电常数介电层移除第一金属栅极层。在步骤314，方法300包括在第二半导体纳米片的高介电常数介电层上沉积第二金属栅极层。第二栅极金属层的一个范例为图1D的第二栅极金属层。在步骤316，方法300包括沉积第二金属栅极层并在第二金属栅极层上原位沉积钝化层。钝化层的一个范例为图1E的钝化层120。
图4是根据一些实施例，绘示出用于形成集成电路的方法400的流程图。方法400可以使用关于图1A～图1F、图2所公开的结构、制程、及组件。在步骤402，方法400包括形成对应P型全绕式栅极晶体管的通道区的多个半导体纳米片。P型全绕式栅极晶体管的一个范例为图1A～图1F的晶体管106。半导体纳米片的一个范例为图1A的半导体纳米片108。在步骤404，方法400包括在半导体纳米片上沉积界面介电层。界面介电层的一个范例为图1A的界面介电层110。在步骤406，方法400包括在界面介电层上沉积高介电常数介电层。高介电常数介电层的一个范例为图1A的高介电常数介电层112。在步骤408，方法400包括在高介电常数介电层上以及半导体纳米片之间沉积金属栅极层。金属栅极层的一个范例为图1D的金属栅极层118。在步骤410，方法400包括沉积金属栅极层并在金属栅极层上原位沉积钝化层。钝化层的一个范例为图1D的钝化层120。在步骤412，方法400包括在钝化层上沉积金属栅极填充材料。金属栅极填充材料的一个范例为图1E的金属栅极层122。
在一个实施例中，一种方法包括：形成对应P型全绕式栅极晶体管的多个通道区的多个半导体纳米片；在半导体纳米片上沉积界面介电层；以及在界面介电层上沉积高介电常数介电层。上述方法包括：在高介电常数介电层上以及半导体纳米片之间沉积金属栅极层；沉积金属栅极层并在金属栅极层上原位沉积钝化层；以及在钝化层上沉积金属栅极填充材料。
在一些实施例中，上述方法更包括：在真空中沉积金属栅极层；以及沉积钝化层且不破坏真空。
在一些实施例中，上述方法更包括以第一原子层沉积制程沉积金属栅极层。
在一些实施例中，上述方法更包括以第二原子层沉积制程沉积钝化层且不破坏来自第一原子层沉积制程的真空。
在一些实施例中，上述方法更包括：在第一沉积腔室中沉积金属栅极层；以及在与第一沉积腔室流体相通的第二沉积腔室中沉积钝化层。
在一些实施例中，其中钝化层位于半导体纳米片之间。
在一些实施例中，其中P型全绕式栅极晶体管的功函数大于或等于4.9eV。
在一个实施例中，一种方法包括：形成对应N型全绕式栅极晶体管的多个通道区的多个第一半导体纳米片；形成对应P型全绕式栅极晶体管的多个通道区的多个第二半导体纳米片；以及在第一及第二半导体纳米片上沉积界面介电层。上述方法包括：在界面介电层上沉积高介电常数介电层；在第一及第二半导体纳米片的高介电常数介电层上沉积第一金属栅极层；以及从第二半导体纳米片上的高介电常数介电层移除第一金属栅极层。上述方法包括：在第二半导体纳米片的高介电常数介电层上沉积第二金属栅极层以及沉积第二金属栅极层并在第二金属栅极层上原位沉积钝化层。
在一些实施例中，上述方法更包括在位于第一N型全绕式栅极晶体管的第一金属栅极层上沉积第二金属栅极层。
在一些实施例中，上述方法更包括：在N型全绕式栅极晶体管以光阻覆盖第一金属栅极层；从第二半导体纳米片上的高介电常数介电层移除第一金属栅极层，且第一金属栅极层在N型全绕式栅极晶体管被光阻覆盖；以及从在第二半导体纳米片上的高介电常数介电层移除第一金属栅极层之后，从位于N型全绕式栅极晶体管的第一金属栅极层移除光阻。
在一些实施例中，上述方法更包括在从位于N型全绕式栅极晶体管的第一金属栅极层移除光阻之后，沉积第二金属栅极层。
在一些实施例中，上述方法更包括在位于N型全绕式栅极晶体管以及位于P型全绕式栅极晶体管的钝化层上沉积金属栅极填充材料。
在一些实施例中，金属栅极填充材料及第二金属栅极层对应P型全绕式栅极晶体管的金属栅极。
在一个实施例中，集成电路包括N型全绕式栅极晶体管。N型全绕式栅极晶体管包括：多个第一半导体纳米片，对应N型全绕式栅极晶体管的多个通道区；界面介电层，位于第一半导体纳米片上；高介电常数介电层，位于界面介电层上；第一金属栅极层，直接位于高介电常数介电层上；以及第二金属栅极层，位于第一金属栅极层上。集成电路包括P型全绕式栅极晶体管。P型全绕式栅极晶体管包括：多个第二半导体纳米片，对应P型全绕式栅极晶体管的多个通道区；上述界面介电层，位于上述第二半导体纳米片上；上述高介电常数介电层，位于上述界面介电层上；上述第二金属栅极层，直接位于上述高介电常数介电层上；以及原位钝化层，位于上述第二金属栅极层上。
在一些实施例中，第二金属栅极层位于半导体纳米片之间。
在一些实施例中，第一金属栅极层包括碳以及钛及钽中的一或多个。
在一些实施例中，第二金属栅极层包括氮以及钛、钽、钨及钼中的一或多个。
在一些实施例中，钝化层包括与第二金属栅极层不同的材料。
在一些实施例中，上述集成电路更包括位于钝化层上的栅极填充材料。
在一些实施例中，钝化层位于第二半导体纳米片之间，其中钝化层不位于第一半导体纳米片之间。
可以合并上述各种实施例以提供进一步的实施例。如果必要，可以修饰上述实施例的多个面向以应用各种专利、申请及公开的概念以提供更进一步的实施例。
可以根据以上详细描述对实施例进行上述改变和其他改变。一般而言，在以下权利要求中，所使用的术语不应被解释为将权利要求限制为在说明书和权利要求中公开的特定实施例，而应被解释为包括所有可能的实施例以及这样的权利要求所授予的等价物的全部范围。因此，权利要求不受本公开的限制。

Claims (1)

1.一种集成电路的制造方法，包括：
形成对应一P型全绕式栅极晶体管的多个通道区的多个半导体纳米片；
在所述半导体纳米片上沉积一界面介电层；
在该界面介电层上沉积一高介电常数介电层；
在该高介电常数介电层上以及所述半导体纳米片之间沉积一金属栅极层；
沉积该金属栅极层并在该金属栅极层上原位沉积一钝化层；以及
在该钝化层上沉积一金属栅极填充材料。
CN202210705786.1A 2021-07-20 2022-06-21 集成电路的制造方法 Pending CN115394721A (zh)

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