CN115394651A - Method for manufacturing semiconductor device and method for manufacturing memory - Google Patents

Method for manufacturing semiconductor device and method for manufacturing memory Download PDF

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Publication number
CN115394651A
CN115394651A CN202211040208.7A CN202211040208A CN115394651A CN 115394651 A CN115394651 A CN 115394651A CN 202211040208 A CN202211040208 A CN 202211040208A CN 115394651 A CN115394651 A CN 115394651A
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CN
China
Prior art keywords
layer
forming
insulating layer
gate structures
semiconductor substrate
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CN202211040208.7A
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Chinese (zh)
Inventor
杨号号
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Zhixun Innovation Technology Wuxi Co ltd
Jones Union Semiconductor Shanghai Co ltd
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Zhixun Innovation Technology Wuxi Co ltd
Jones Union Semiconductor Shanghai Co ltd
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Priority to CN202211040208.7A priority Critical patent/CN115394651A/en
Publication of CN115394651A publication Critical patent/CN115394651A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention discloses a manufacturing method of a semiconductor device and a manufacturing method of a memory, wherein the method comprises the following steps: providing a semiconductor substrate; forming an insulating layer on a semiconductor substrate; forming a plurality of gate structures on the insulating layer; forming an etching barrier layer on the side wall of the adjacent gate structure and the exposed insulating layer; performing dry etching on the insulating layer and the semiconductor substrate at the gap between the adjacent gate structures to form a plurality of grooves; carrying out first wet etching on the surface of the groove; removing the first oxide layer; carrying out second wet etching on the side walls of the plurality of grid structures and the side walls of the grooves; forming oxide layers on the upper surfaces and the side walls of the plurality of grid structures and the side walls and the bottoms of the grooves; and forming a gate dielectric layer on the oxide layer, wherein the gate dielectric layer covers gaps between the adjacent gate structures. The method can solve the problem of side wall damage of the grid structure caused by the manufacturing process of the conventional two-dimensional memory, and is favorable for improving the device characteristics of the memory.

Description

Method for manufacturing semiconductor device and method for manufacturing memory
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a method for manufacturing a semiconductor device and a method for manufacturing a memory.
Background
Memory fabrication technology is currently an important component of semiconductor integrated circuit fabrication. As the device size of the memory device is continuously reduced, the gate-to-gate dimension is smaller. A substrate of a two-dimensional memory (2D NAND) is generally divided into an edge (peripheral) region and a device (cell) region, on which a plurality of gate structures are formed (also referred to as a cell region). Researches show that in the process of dry etching of a substrate in a gap between adjacent gate structures in a device region, on one hand, the side wall of the stacked gate structure is damaged to a certain extent, and the electrical performance is seriously even deteriorated, and finally the yield and the reliability are deteriorated. On the other hand, the tunnel oxide layer is easily damaged by the etching ions, thereby affecting the quality of the tunnel oxide layer and causing the electrical property and reliability failure.
Therefore, it is desirable to provide a new method for manufacturing a two-dimensional memory to improve the above-mentioned problems.
Disclosure of Invention
Embodiments of the present invention provide a method for manufacturing a semiconductor device and a method for manufacturing a memory, so as to solve the problem of sidewall damage of a gate structure caused by a conventional two-dimensional memory manufacturing process.
In a first aspect, the present invention provides a method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a plurality of gate structures on the insulating layer; forming an etching barrier layer on the side wall of the adjacent gate structure and the exposed insulating layer; performing dry etching on the insulating layer and the semiconductor substrate at the gap between the adjacent gate structures to form a plurality of grooves; carrying out first wet etching on the surface of the groove; removing the etching barrier layer; carrying out second wet etching on the side walls of the plurality of grid structures and the side wall of the groove; forming oxide layers on the upper surfaces and the side walls of the plurality of grid structures and the side walls and the bottoms of the grooves; and forming a gate dielectric layer on the oxide layer, wherein the gate dielectric layer covers the gap between the adjacent gate structures.
The manufacturing method of the semiconductor device provided by the invention has the beneficial effects that: by adding the etching barrier layer, the side wall of the grid structure can be protected, particularly the damage to the bottom of the side wall of the grid structure caused by dry etching is avoided, and in addition, the ion damage of the insulating layer caused by the dry etching can be repaired by two times of wet etching.
Optionally, forming a plurality of gate structures on the insulating layer includes: sequentially forming a floating gate structure layer and a hard mask layer on the insulating layer; and etching the floating gate structure layer and the hard mask layer to form a plurality of gate structures.
Optionally, the etching barrier layer and the oxide layer are liner oxide layers, and the liner oxide layers can repair damage caused by dry etching and protect the gate structure, so that damage to the sidewalls caused by subsequent dry etching is avoided.
Optionally, the liner oxide layer is silicon oxide or silicon nitride, or is silicon oxynitride.
Optionally, the method further comprises: and carrying out ion implantation on the semiconductor substrate to form an active region and a drain region in the substrate at two sides of the grid structure.
Optionally, the gate dielectric layer is made of a low-dielectric-constant material, such as organic spin-on glass.
Optionally, the insulating layer is a tunnel oxide layer.
Optionally, after performing the second wet etching on the sidewalls of the plurality of gate structures and the sidewalls of the trench, a feature size of the channel is smaller than or equal to a bottom feature size of the gate structure.
Optionally, after performing the second wet etching on the sidewalls of the plurality of gate structures and the sidewalls of the trench, an end portion of the insulating layer under the gate structures is exposed.
In a second aspect, the present invention further provides a method for manufacturing a memory, which includes any one of the possible implementation methods of the first aspect. Specific advantageous effects can be seen from the description of the first aspect described above.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to the prior art;
fig. 2A to fig. 2H are schematic diagrams of stages of a manufacturing process of a semiconductor device according to an embodiment of the invention.
Element number description:
100 semiconductor substrate
200 insulating layer
300 gate structure 301 floating gate structure layer 302 hard mask layer
400 etch stop layer
500 groove
600 oxidation layer
700 gate dielectric layer
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, it should be understood that the structure shown in the drawings is not drawn to general scale and is partially enlarged, modified or simplified, so that the present invention is not limited thereto.
In order to make the objects, technical solutions and advantages of the present invention clearer, a flow chart of a manufacturing method of a semiconductor device is further shown below with reference to fig. 1, and fig. 2A to 2H show a schematic diagram of a stage result of each process preparation stage in this example.
Referring to fig. 1, a process for manufacturing a memory of a semiconductor device according to an embodiment of the present invention includes the following steps:
s101, a semiconductor substrate 100 is provided.
As shown in (a) of fig. 2A, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the semiconductor substrate 100 may also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate. The semiconductor substrate 100 may include various doped regions depending on the design requirements of a memory or other semiconductor device. The semiconductor substrate 100 may further include an isolation structure (e.g., a Shallow Trench Isolation (STI)) to isolate the regions.
In this embodiment, the semiconductor substrate 100 may be a silicon substrate, and the semiconductor substrate 100 includes a device region (also referred to as a cell region) and a peripheral region (also referred to as an edge region).
S102, an insulating layer 200 is formed on the semiconductor substrate 100.
Specifically, referring to (b) in fig. 2A, an oxide is deposited on the front surface of the semiconductor substrate 100 by Physical Vapor Deposition (PVD), thereby forming an insulating layer 200, which is also called a tunnel oxide (tunnel OX). The oxide of the insulating layer 200 may be at least one of copper oxide with a low oxygen content, aluminum oxide, hafnium oxide, titanium oxide, and tantalum oxide.
S103, forming a plurality of gate structures 300 on the insulating layer.
Specifically, in one possible implementation, referring to fig. 2B (a), a floating gate structure layer 301 and a hard mask layer 302 may be sequentially formed on the insulating layer, and then the floating gate structure layer 301 and the hard mask layer 302 may be patterned and etched to form a plurality of gate structures 300, referring to fig. 2B (B).
And S104, forming an etching barrier layer 400 on the top and the side wall of the adjacent gate structure 300 and the exposed insulating layer 200.
Specifically, the etch stop layer 400 may be a liner oxide (liner oxide) layer, which is silicon oxide, silicon nitride, or silicon oxynitride. Referring to fig. 2C, before etching the semiconductor substrate 100, a pad oxide layer is grown, which not only can repair the damage caused by the dry etching, but also can protect the gate structure to prevent the sidewall from being damaged by the subsequent dry etching.
S105, dry etching is performed on the insulating layer 200 and the semiconductor substrate 100 in the gap between the adjacent gate structures 300 to form a plurality of trenches 500.
Specifically, referring to fig. 2D, a photoresist is coated, and the insulating layer 200 and the semiconductor substrate 100 in the window region are dry-etched using the gap between the adjacent gate structures 300 as a window, thereby forming a plurality of trenches 500.
S106, carrying out first wet etching on the surface of the groove 500.
Alternatively, as shown in FIG. 2E, a high temperature semiconductor substrate or diluted TMAH may be used for repair (pull back) that is single sided from about 1nm to about 3nm in Critical Dimension (CD). CD is the minimum size of a semiconductor device in an integrated circuit, and is an important measure for measuring the design and manufacturing level of the integrated circuit, and this step can effectively repair the damage caused by the dry etching on the sidewalls of the gate structure 300 and the trench 500, and prevent the leakage current caused by the damage, or prevent the electrical failure.
S107, removing the etching stop layer 400, and performing a second wet etching on the sidewalls of the plurality of gate structures 300 and the sidewalls of the trench 500.
Alternatively, the intermediate structure after removing the etch stopper 400 is as shown in (a) of fig. 2F. Thereafter, a second wet etching is further performed on the sidewalls of the gate structures 300 and the sidewalls of the trench 500, so as to obtain an intermediate structure as shown in (b) of fig. 2F. The method can effectively avoid the damage risk of the tunneling oxide layer caused by dry etching, effectively ensure high-quality tunneling oxide layer between the grid structure 300 and the channel, and prevent electrical property and reliability from losing efficacy.
In this embodiment, after performing the second wet etching on the sidewalls of the plurality of gate structures and the sidewalls of the trench, the feature size of the channel is smaller than or equal to the bottom feature size of the gate structure. And an end portion of the insulating layer under the gate structure is exposed.
And S108, forming an oxidation layer 600 on the upper surfaces and the side walls of the plurality of gate structures and the side walls and the bottom of the groove.
Optionally, referring to fig. 2G, a liner oxide layer (liner oxide) is grown on the top surface and sidewalls of the gate structures, and the sidewalls and bottom of the trench.
S109, forming a gate dielectric layer 700 on the oxide layer 600, where the gate dielectric layer 700 covers the gap between the adjacent gate structures 300.
Optionally, referring to fig. 2H, a gate dielectric layer 700 is formed on the oxide layer 600, and the material of the gate dielectric layer 700 is a low dielectric constant material, such as organic spin-on glass.
Optionally, the method may further include: the semiconductor substrate 100 is ion-implanted to form active and drain regions in the substrate at both sides of the gate structure 300, and then a two-dimensional memory is formed based on the above method.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.

Claims (9)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming an insulating layer on the semiconductor substrate;
forming a plurality of gate structures on the insulating layer;
forming an etching barrier layer on the side wall of the adjacent gate structure and the exposed insulating layer;
performing dry etching on the insulating layer and the semiconductor substrate at the gap between the adjacent gate structures to form a plurality of grooves;
carrying out first wet etching on the surface of the groove;
removing the etching barrier layer;
performing second wet etching on the side walls of the plurality of gate structures and the side walls of the grooves, so that the end parts of the insulating layers below the gate structures are exposed;
forming oxide layers on the upper surfaces and the side walls of the plurality of grid structures and the side walls and the bottoms of the grooves;
and forming a gate dielectric layer on the oxide layer, wherein the gate dielectric layer covers the gap between the adjacent gate structures.
2. The method of claim 1, wherein forming a plurality of gate structures on the insulating layer comprises:
sequentially forming a floating gate structure layer and a hard mask layer on the insulating layer;
and etching the floating gate structure layer and the hard mask layer to form a plurality of gate structures.
3. The method of claim 2, wherein the etch stop layer and the oxide layer are liner oxide layers.
4. The method of claim 3, wherein the pad oxide layer is silicon oxide, silicon nitride, or silicon oxynitride.
5. The method according to any one of claims 1 to 4, further comprising:
and carrying out ion implantation on the semiconductor substrate to form an active region and a drain region in the substrate at two sides of the grid structure.
6. The method of any of claims 1 to 4, wherein the material of the gate dielectric layer is a low dielectric constant material.
7. The method of any of claims 1 to 4, wherein the insulating layer is a tunnel oxide layer.
8. The method of claim 5, wherein after the second wet etching of the sidewalls of the plurality of gate structures and the sidewalls of the trench, a feature size of the channel is less than or equal to a bottom feature size of the gate structures.
9. A method for manufacturing a memory, comprising the method for manufacturing a semiconductor device according to any one of claims 1 to 8.
CN202211040208.7A 2022-08-29 2022-08-29 Method for manufacturing semiconductor device and method for manufacturing memory Pending CN115394651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211040208.7A CN115394651A (en) 2022-08-29 2022-08-29 Method for manufacturing semiconductor device and method for manufacturing memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211040208.7A CN115394651A (en) 2022-08-29 2022-08-29 Method for manufacturing semiconductor device and method for manufacturing memory

Publications (1)

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CN115394651A true CN115394651A (en) 2022-11-25

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