CN115392186A - Fault collection management system and method in system on chip - Google Patents
Fault collection management system and method in system on chip Download PDFInfo
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- CN115392186A CN115392186A CN202211001815.2A CN202211001815A CN115392186A CN 115392186 A CN115392186 A CN 115392186A CN 202211001815 A CN202211001815 A CN 202211001815A CN 115392186 A CN115392186 A CN 115392186A
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Abstract
The invention relates to a fault collection management system and method in a system on chip. The system comprises a register interface unit, a handshake unit, a state machine unit, a state output unit and a fault interface unit, wherein the register interface unit is connected with the handshake unit, the handshake unit is connected with the state machine unit, the state machine unit is connected with the state output unit, and the register interface unit realizes the configuration of a register, a bus interface, an interrupt interface and the like; the handshake unit realizes the synchronization of the bus clock signal and the internal logic signal; the fault interface unit realizes the input, detection and classification of faults; the state machine unit realizes the control management of faults, including the configuration of predefined faults, the alarm of the faults, the response of the faults and the like; the state output unit realizes the state output of the system and the output of the response. The invention adopts a pure hardware mode to realize the detection, collection and processing of system faults under the condition of no processor participation, and guides the equipment to a safe state in a controllable mode when the equipment has faults, thereby improving the safety and reliability of the operation of the processor in the system on chip and improving the efficiency of system debugging.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a fault collection management system and method in a system on a chip.
Background
Along with the continuous development of integrated circuits, the scale of a system on a chip is larger and larger, the frequency of system faults occurring in the operation process of a processor chip is higher and higher, the sources of the faults are difficult to be accurately positioned and timely processed, and the safety and the reliability of the system are greatly reduced.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides a system and a method for collecting and managing faults in a system on chip, which adopt a pure hardware mode to realize the detection, collection and processing of system faults under the condition of not needing processor participation, and guide equipment to a safe state in a controllable mode when the equipment has faults, thereby improving the safety and reliability of the operation of the processor in the system on chip and improving the efficiency of system debugging.
The technical solution of the invention is as follows: the invention relates to a fault collection management system in a system on chip, which is characterized in that: the management system comprises a register interface unit, a handshake unit, a state machine unit, a state output unit and a fault interface unit, wherein the register interface unit is connected with the handshake unit, the handshake unit is connected with the state machine unit, the state machine unit is connected with the state output unit, and the register interface unit realizes the configuration of a register, a bus interface, an interrupt interface and the like; the handshake unit realizes the synchronization of the bus clock signal and the internal logic signal; the fault interface unit realizes the input, detection and classification of faults; the state machine unit realizes the control management of faults, including the configuration of predefined faults, the alarm of the faults, the response of the faults and the like; the state output unit realizes the state output of the system and the output of the response.
Furthermore, the register interface unit is provided with a standard APB bus slave device interface, and a 32-bit address bus and a 32-bit data bus are adopted; after the system is enabled by software to enter a configuration state, the enabling and responding modes of key and non-key faults can be configured through the register interface unit, and the processing state of the faults is read.
Further, the handshake unit synchronizes the configuration information of the critical and non-critical faults to the state machine unit and the fault interface unit; the handshake unit comprises a master handshake unit and a slave handshake unit, the register interface unit is connected with the master handshake unit, the master handshake unit is connected with the slave handshake unit, and the slave handshake unit is connected with the state machine unit.
Further, the fault interface unit locks the fault of the external input and distinguishes the input fault as a non-critical fault and a critical fault.
Further, the state output unit manages and outputs two signals indicating the states of the system, including a fault state, a normal state, a configuration state, and the like.
Furthermore, a state machine, a watchdog, a safe mode request timer and an alarm timer are arranged in the state machine unit, the watchdog, the safe mode request timer and the alarm timer are respectively connected with the state machine to realize control processing and the like of faults, control management of the faults is realized through the internal watchdog, the safe mode request timer and the alarm timer, and the like, and the control management is realized through the state machine.
Further, the state machine includes 4 states, which are specifically as follows:
1) Configuring the state: the system is used for changing the default configuration of the system, the configuration state defines the global configuration, the fault response, the timeout, the shielding of non-critical faults and the like of the system, and the related registers can only be accessed in a write mode in the configuration state;
2) And (4) a normal state: the state without fault occurrence is a default state or a reset state;
after a critical fault occurs, switching to a fault state;
after non-critical faults which are not shielded and are forbidden to be overtime occur, the non-critical faults are converted into a fault state;
after non-key faults which are not shielded and enable overtime occur, the system is switched to an alarm state;
after the shielding non-critical fault occurs, keeping a normal state;
3) An alarm state: when a non-critical fault which is not shielded and is enabled to be overtime occurs, the system enters an alarm state, and the alarm state is accompanied by the output of an interrupt request;
if the fault is recovered within a programmable timeout period, the system moves to a normal state and the timeout counter needs to be reinitialized;
if the system has key faults in the alarm state, the system is switched to the fault state from the alarm state, and the overtime counting is stopped;
when the fault state is recovered to the alarm state, the overtime timer is restarted;
4) A fault state: the system will enter a fault state after the following occurs:
a critical fault occurs;
when the system is in an alarm state and non-critical faults are overtime;
non-critical faults that are unmasked and not enabled for timeout occur.
Further, the transition from the normal or alarm state to the fault state in the state machine is typically accompanied by the following outputs:
interrupting;
outputting a management signal change;
requesting a security mode after a certain time;
software configurable response: responding by software;
software configurable response: and responding by hardware.
A method for realizing the fault collection management system in the system on chip is characterized in that: the method comprises the following steps:
1) The fault collection management system collects predefined faults in the running process of the chip and performs classified management; according to the criticality of the fault, two types of fault types are defined: critical faults and non-critical faults;
2) Responding to the fault without processor participation; after the software enables the fault collection management system to enter a configuration state, the enabling and responding modes of key and non-key faults can be configured through the register, and the processing state of the faults is read.
Further, the specific steps of step 2) are as follows:
2.1 After the configuration information of key faults and non-key faults is synchronized to the state machine unit, when the fault interface locks the non-key faults, the fault collection management system enters an alarm state, an alarm timer is started, and meanwhile, the response of the alarm state is output; before the alarm timer is overtime, the fault processing is completed, and the system enters a normal state; after the alarm timer is overtime, the alarm timer enters a fault state, a fault state response is output, and the safety mode requests the timer to be started; before the safe mode request timer is overtime, if the non-key fault is recovered, the system enters a normal state, otherwise, a safe mode request is initiated;
2.2 When a critical fault is locked out by a faulty interface, the system enters a fault state and outputs a fault state response, including non-maskable interrupts, safe mode requests, long-short function resets, and the like. When the key failure is recovered, the system enters a normal state;
2.3 Fault collection management system is in a normal state, if a critical fault and a non-critical fault occur simultaneously, the priority of the fault state is higher than the alarm state; in the case of simultaneous critical faults, the fault response corresponds to the worst case (long function reset will respond if the fault is programmed);
2.4 A failure collection management system transitions from an alarm state to a failure state if a critical or non-critical failure (non-masked and disable timeout) is active in the alarm state;
2.5 Any critical faults that occur when the fault collection management system is already in a fault state will result in a hardware or software response (i.e., a long function reset or a short function reset);
2.6 The fault collection management system is switched from the alarm state to the normal state only when all non-critical faults (including faults captured after the fault collection management system enters the alarm state, i.e., software or hardware recoverable faults) are cleared, otherwise, the fault collection management system remains in the alarm state;
2.7 The fault collection management system may enter a normal state from the fault state only if all critical and non-critical faults (including faulty software or hardware recoverable faults collected after the fault collection management system entered the fault or an alarm state) are cleared, otherwise the fault collection management system remains in the fault state (if any critical faults are to be resolved) or returns to the alarm state (if any non-critical faults are to be resolved and have timed out).
The invention provides a fault collection management system and method in a system on chip, wherein the system mainly comprises five modules: register interface unit, handshake unit (master/slave), fault interface unit, state machine unit and state output unit. Wherein the register interface unit: the configuration of a register, a bus interface, an interrupt interface and the like are realized; handshake unit (master/slave): the synchronization of the bus clock signal and the internal logic signal is realized; a fault interface unit: the input, the detection and the classification of the faults are realized; a state machine unit: the control management of the faults is realized, including the configuration of predefined faults, the alarm of the faults, the response of the faults and the like, and the control management of the faults is realized through an internal watchdog, a safety mode request timer, an alarm timer and the like; a state output unit: the state output and the response output of the system are realized. The invention detects and collects system faults through a programmable hardware channel, guides the equipment to a safe state in a controllable mode when the equipment has faults, does not need processor participation in the detection and collection process, and can configure the criticality of the faults and the response mode of output by software. The system provided by the invention improves the safety and reliability of the operation of the processor in the system on chip to a great extent.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a state transition diagram of the fault collection management of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the structure of the embodiment of the fault collection management system in the soc of the present invention includes a register interface unit, a master handshake unit, a slave handshake unit, a state machine unit, a state output unit, and a fault interface unit, where the register interface unit is connected to the master handshake unit, the master handshake unit is connected to the slave handshake unit, the slave handshake unit is connected to the state machine unit, and the state machine unit is connected to the state output unit. Wherein:
the register interface unit realizes the configuration of a register, a bus interface, an interrupt interface and the like; the register interface unit is provided with a standard APB bus slave equipment interface and adopts a 32-bit address bus and a 32-bit data bus; after the system is enabled by software to enter a configuration state, the enabling and responding modes of key and non-key faults can be configured through the register interface unit, and the processing state of the faults is read.
The handshake unit realizes the synchronization of the bus clock signal and the internal logic signal; synchronizing configuration information of critical and non-critical faults to a state machine unit and a fault interface unit;
the fault interface unit realizes the input, detection and classification of faults; the fault interface unit locks the fault of the external input and distinguishes the input fault into a non-critical fault and a critical fault.
The state output unit is used for realizing state output and response output of the system, and managing and outputting two signals to indicate the state of the system, including a fault state, a normal state, a configuration state and the like.
The state machine unit realizes the control management of faults, including the configuration of predefined faults, the alarm of the faults, the response of the faults and the like; the state machine unit is internally provided with a state machine, a watchdog, a safety mode request timer and an alarm timer, the watchdog, the safety mode request timer and the alarm timer are respectively connected with the state machine to realize control processing and the like of faults, control management of the faults is realized through the internal watchdog, the safety mode request timer, the alarm timer and the like, and the control management is realized by the state machine. The state machine includes 4 states, which are specifically as follows:
1) Configuration state: the system is used for changing the default configuration of the system, the configuration state defines the global configuration, fault response, timeout, shielding of non-critical faults and the like of the system, and related registers can only be accessed in a write mode in the configuration state;
2) And (3) normal state: the state without fault is a default state or a reset state;
after a critical fault occurs, switching to a fault state;
after non-critical faults which are not shielded and are forbidden to be overtime occur, the non-critical faults are converted into a fault state;
after non-key faults which are not shielded and enable overtime occur, switching to an alarm state;
after the shielding non-critical fault occurs, keeping a normal state;
3) And (4) alarm state: when a non-critical fault which is not shielded and is enabled to be overtime occurs, the system enters an alarm state, and the alarm state is accompanied by the output of an interrupt request;
if the fault is recovered within a programmable timeout period, the system moves to normal and the timeout counter needs to be reinitialized;
if the system has key faults in the alarm state, the system is switched to the fault state from the alarm state, and the overtime counting is stopped;
when the fault state is recovered to the alarm state, the overtime timer is restarted;
4) And (3) fault state: the system will enter a fault state after the following occurs:
a critical fault occurs;
when the system is in an alarm state and the non-critical fault is overtime;
non-critical faults that are unmasked and not enabled for timeout occur.
In a state machine, the transition from a normal or alarm state to a fault state is typically accompanied by the following outputs:
interrupting;
outputting a management signal change;
requesting a security mode after a certain time;
software configurable response: responding by software;
software configurable response: and responding by hardware.
The invention also provides a fault collection management method in the system on chip, which comprises the following steps:
1) The fault collection management system collects predefined faults in the running process of the chip and performs classified management; according to the criticality of the fault, two types of fault types are defined: critical faults and non-critical faults;
2) Responding to the fault under the condition of no processor participation; the system is provided with a standard APB bus slave device interface, and after a software-enabled fault collection management system enters a configuration state, the system can read the processing state of faults through the enabling and responding modes of key and non-key faults of a register configuration.
Referring to fig. 2, the fault collection management state transition of the present invention is specifically as follows:
2.1 After the configuration information of key and non-key faults is synchronized to the state machine unit, when a fault interface locks the non-key faults, the fault collection management system enters an alarm state, an alarm timer is started, and meanwhile, the response of the alarm state is output; before the alarm timer is overtime, the fault processing is finished, and the system enters a normal state; after the alarm timer is overtime, the alarm timer enters a fault state, a fault state response is output, and the safety mode requests the timer to be started; before the safe mode request timer is overtime, if the non-key fault is recovered, the system enters a normal state, otherwise, a safe mode request is initiated;
2.2 When a critical failure is locked out by a failed interface, the system enters a failure state and outputs a failure state response, including non-maskable interrupts, security mode requests, long-short function resets, and the like. When the key failure is recovered, the system enters a normal state;
2.3 Fault collection management system is in a normal state, if a critical fault and a non-critical fault occur simultaneously, the priority of the fault state is higher than the alarm state; in the case of simultaneous critical faults, the fault response corresponds to the worst case (if the fault is programmed, a long functional reset will respond);
2.4 If a critical or non-critical fault (non-masked and disable timeout) is valid in the alarm state, the fault collection management system transitions from the alarm state to the fault state;
2.5 Any critical faults that occur when the fault collection management system is already in a fault state will result in a hardware or software response (i.e., a long function reset or a short function reset);
2.6 The fault collection management system is switched from the alarm state to the normal state only when all non-critical faults (including faults captured after the fault collection management system enters the alarm state, i.e., software or hardware recoverable faults) are cleared, otherwise, the fault collection management system remains in the alarm state;
2.7 The fault collection management system enters a normal state from the fault state only when all critical and non-critical faults (including faulty software or hardware recoverable faults collected after the fault collection management system enters the fault or an alarm state) are cleared, otherwise the fault collection management system remains in the fault state (if any critical faults are to be resolved) or returns to the alarm state (if any non-critical faults are to be resolved and have timed out).
The basic definition of the invention is as follows:
hardware recoverable failure: the fault indication is an edge and level sensitive signal and is valid until the cause of the fault is captured, i.e. if a 0 on the fault signal indicates a fault, the status flag is valid until the fault signal is 0. When the fault signal becomes 1, the state is automatically disappeared. A typical fault signal is latched in an external module of the fault collection management system, and the state of the fault collection management system is changed according to the state of the input fault signal.
And (3) software recoverable faults: the fault indication signal is a valid signal of undefined duration, the fault signal is captured in the fault collection management system and the fault recovery performs a software recovery procedure (status/flag register clear).
Long function reset: flash memory and most digital systems are initialized.
Short function reset: initialization of most digital systems.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A system-on-chip fault collection management system is characterized in that: the management system comprises a register interface unit, a handshake unit, a state machine unit, a state output unit and a fault interface unit, wherein the register interface unit is connected with the handshake unit, the handshake unit is connected with the state machine unit, the state machine unit is connected with the state output unit, and the register interface unit realizes the configuration of a register, a bus interface and an interrupt interface; the handshake unit realizes the synchronization of a bus clock signal and an internal logic signal; the fault interface unit realizes the input, detection and classification of faults; the state machine unit realizes control management on faults, including configuration of predefined faults, alarm of the faults and response of the faults; the state output unit realizes the state output and the response output of the system.
2. The system-on-chip fault collection management system according to claim 1, wherein: the register interface unit is provided with a standard APB bus slave equipment interface and adopts a 32-bit address bus and a 32-bit data bus; after the system is enabled by software to enter a configuration state, the enabling and responding modes of key and non-key faults can be configured through the register interface unit, and the processing state of the faults is read.
3. The system-on-chip failure collection management system according to claim 1, wherein: the handshake unit synchronizes configuration information of critical and non-critical faults to the state machine unit and the fault interface unit; the handshake unit comprises a master handshake unit and a slave handshake unit, the register interface unit is connected with the master handshake unit, the master handshake unit is connected with the slave handshake unit, and the slave handshake unit is connected with the state machine unit.
4. The system-on-chip fault collection management system according to claim 1, wherein: the fault interface unit locks the fault of the external input and distinguishes the input fault into a non-critical fault and a critical fault.
5. The system-on-chip fault collection management system according to claim 1, wherein: the state output unit manages and outputs two signals, and indicates the states of the system, including a fault state, a normal state and a configuration state.
6. The system-on-chip failure collection management system according to claim 1, wherein: the system comprises a state machine unit, a watchdog unit, a safety mode request timer and an alarm timer, wherein the state machine unit is internally provided with the state machine, the watchdog unit, the safety mode request timer and the alarm timer are respectively connected with the state machine to realize control processing of faults, control management of the faults is realized through the internal watchdog unit, the safety mode request timer and the alarm timer, and the control management is realized through the state machine.
7. The system-on-chip fault collection management system according to claim 6, wherein: the state machine comprises 4 states, which are specifically as follows:
1) Configuring the state: the system is used for changing the default configuration of the system, the configuration state defines the global configuration, fault response, timeout, shielding of non-critical faults and the like of the system, and related registers can only be accessed in a write mode in the configuration state;
2) And (4) a normal state: the state without fault occurrence is a default state or a reset state;
after a critical fault occurs, switching to a fault state;
after non-critical faults which are not shielded and are forbidden to be overtime occur, the non-critical faults are converted into a fault state;
after non-key faults which are not shielded and enable overtime occur, the system is switched to an alarm state;
after shielding non-critical faults, keeping a normal state;
3) And (4) alarm state: when a non-critical fault which is not shielded and is enabled to be overtime occurs, the system enters an alarm state, and the alarm state is accompanied by the output of an interrupt request;
if the fault is recovered within a programmable timeout period, the system moves to normal and the timeout counter needs to be reinitialized;
if the system has key faults in the alarm state, the system is switched to the fault state from the alarm state, and the overtime counting is stopped;
when the fault state is recovered to the alarm state, the overtime timer is restarted;
4) A fault state: the system will enter a fault state after the following occurs:
a critical fault occurs;
when the system is in an alarm state and the non-critical fault is overtime;
non-critical faults that are unmasked and not enabled for timeout occur.
8. The system-on-chip failure collection management system according to claim 7, wherein: the transition from the normal or alarm state to the fault state in the state machine is typically accompanied by the following outputs:
interrupting;
outputting a management signal change;
requesting a security mode after a certain time;
software configurable response: responding by software;
software configurable response: and responding by hardware.
9. A method for implementing the system for fault collection management in a system-on-chip of claim 1, wherein: the method comprises the following steps:
1) The fault collection management system collects predefined faults in the running process of the chip and performs classified management; according to the criticality of the fault, two types of fault types are defined: critical faults and non-critical faults;
2) Responding to the fault without processor participation; after the software enables the fault collection management system to enter a configuration state, the enabling and responding modes of key and non-key faults can be configured through the register, and the processing state of the faults is read.
10. The method of fault collection management in a system on a chip of claim 9, wherein: the specific steps of the step 2) are as follows:
2.1 After the configuration information of key faults and non-key faults is synchronized to the state machine unit, when the fault interface locks the non-key faults, the fault collection management system enters an alarm state, an alarm timer is started, and meanwhile, the response of the alarm state is output; before the alarm timer is overtime, the fault processing is finished, and the system enters a normal state; after the alarm timer is overtime, the alarm timer enters a fault state, a fault state response is output, and the safety mode requests the timer to be started; before the safe mode request timer is overtime, if the non-key fault is recovered, the system enters a normal state, otherwise, a safe mode request is initiated;
2.2 When a critical fault is locked out by a faulty interface, the system enters a fault state and outputs a fault state response, including non-maskable interrupts, safe mode requests, long-short function resets, and the like. When the key failure is recovered, the system enters a normal state;
2.3 Fault collection management system is in normal state, if critical fault and non-critical fault occur simultaneously, then fault state has higher priority than alarm state; in the case of simultaneous occurrence of critical faults, the fault response corresponds to the worst case;
2.4 A failure collection management system transitions from an alarm state to a failure state if a critical failure or a non-critical failure is valid in the alarm state;
2.5 Any critical faults that occur when the fault collection management system is already in a fault state will result in a hardware or software response;
2.6 The fault collection management system will transition from the alarm state to the normal state only if all non-critical faults are cleared, otherwise the fault collection management system remains in the alarm state;
2.7 The fault collection management system will go from the fault state to the normal state only if all critical and non-critical faults are cleared, otherwise the fault collection management system remains in the fault state or returns to the alarm state.
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| CN116501008A (en) * | 2023-03-31 | 2023-07-28 | 北京辉羲智能科技有限公司 | Fault management system for automatic driving control chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116501008A (en) * | 2023-03-31 | 2023-07-28 | 北京辉羲智能科技有限公司 | Fault management system for automatic driving control chip |
| CN116501008B (en) * | 2023-03-31 | 2024-03-05 | 北京辉羲智能信息技术有限公司 | Fault management system for automatic driving control chip |
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