CN115453315A - Fault detection circuit, method and chip for signal transmission line - Google Patents

Abstract

The invention discloses a fault detection circuit, a fault detection method, a chip, electronic equipment and a vehicle of a signal transmission line. The signal generation branch circuit is provided with a synchronizer module and a functional module which are the same as the signal transmission line, wherein the functional module is used for receiving IO signals through the synchronizer module and processing the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. Therefore, the first detection branch circuit judges the fault of the signal transmission line according to the first signal relation between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch circuit, and monitors the signal transmitted by the signal transmission line in real time.

Description

Fault detection circuit, method and chip for signal transmission line

technical field

The invention relates to the technical field of microprocessors, in particular to a fault detection circuit, method, chip, electronic equipment and vehicle of a signal transmission line.

Background technique

With the popularity of smart devices, the requirements for the use of chips are getting higher and higher. There are usually a large number of IO (Input Output, input and output) signal transmission lines connected to peripheral devices in the chip. How to ensure the correctness of the IO signal during the transmission process in the entire chip and how to perform effective real-time fault detection on the IO signal, for A highly functionally safe chip and the systems that use it are a critical element. Especially for input signals with high importance, in order to ensure the accuracy of signal transmission, it is necessary to monitor the signal transmission line in real time, so that any circuit failure or signal interference in the signal path can be detected and reported in real time.

Contents of the invention

In order to solve the above problems, embodiments of the present invention provide a fault detection circuit, method, chip, electronic device and vehicle of a signal transmission line.

According to the first aspect of the present invention, a fault detection circuit of a signal transmission line is provided, the fault detection circuit is arranged in a system-on-a-chip, including: a signal generation branch, having the same synchronizer module and function as the signal transmission line module, the functional module is used to receive the IO signal through the synchronizer module and process the received IO signal; the first detection branch is connected to the output terminal of the synchronizer circuit module of the signal transmission line and the signal generation Between the output terminals of the synchronizer circuit module of the branch, it includes: a first detection module, which is used to judge the first intermediate signal of the output terminal of the synchronizer module of the signal transmission line and the output terminal of the synchronizer module of the signal generation branch. A first signal relationship among the first generated signals, and a fault judgment is performed on the signal transmission line based on the first signal relationship; a first error injection module is used to judge the working state of the first detection module.

According to an embodiment of the present invention, the first detection module is an inequality comparison module; correspondingly, when the first signal relationship is that the first intermediate signal and the first occurrence signal are not equal , determining that the signal transmission line is faulty, and outputting a first interruption signal.

According to an embodiment of the present invention, both the signal generation branch and the signal transmission line further include a pulse width filter module; correspondingly, the fault detection circuit further includes: a second detection branch connected to the signal Between the output end of the pulse width filter module of the transmission line and the output end of the pulse width filter module of the signal generation branch, it includes: a second detection module for judging the output of the pulse width filter module of the signal transmission line The second signal relationship between the second intermediate signal at the terminal and the second generated signal at the output end of the pulse width filter module of the signal generation branch, and based on the second signal relationship, fault judgment is performed on the signal transmission line; the second An error injection module is used for judging the working state of the second detection module.

According to an embodiment of the present invention, the second detection branch further includes: a selector, the input end of which is connected to the output end of the synchronizer module of the signal transmission line and the output end of the synchronizer module of the signal generation line, and the output terminal is connected with the input end of the pulse width filter module of the signal generation branch, and is used to select the output signal of the synchronizer module of the signal transmission line or the output signal of the signal generation branch as the Input signal to the pulse width filter block of the signal generation branch.

According to an embodiment of the present invention, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generation branch are configured as a filtering configuration for filtering the same pulse width but opposite pulse polarity.

According to an embodiment of the present invention, the second detection branch further includes: an inverter connected between the output end of the synchronizer module of the signal transmission line and the input end of the pulse width filter module of the signal generation branch During the period, it is used to reverse the output signal of the synchronizer module of the signal transmission line and then input it to the pulse width filter module of the signal generation branch; correspondingly, the pulse width filter module of the signal transmission line and the The pulse width filtering module of the signal generation branch is configured as a filtering configuration for filtering the same pulse width but opposite pulse polarity.

According to an embodiment of the present invention, the signal generation branch is an independently set signal transmission line that is the same as the signal transmission line or another signal transmission line that is currently idle and is the same as the signal transmission line.

According to the second aspect of the present invention, there is also provided a fault detection method for a signal transmission line, the method comprising: receiving the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first intermediate signal at the output end of the synchronizer module of the signal generation branch a first generation signal; outputting a first interrupt instruction when a first signal relationship between the first intermediate signal and the first generation signal satisfies a first setting condition.

According to the third aspect of the present invention, a chip is also provided, and the chip includes the above-mentioned signal transmission line fault detection circuit.

According to a fourth aspect of the present invention, an electronic device is further provided, and the electronic device includes the above-mentioned chip.

According to a fifth aspect of the present invention, a vehicle is further provided, the vehicle including the above-mentioned electronic device.

In the fault detection circuit, method, chip, electronic device and vehicle of the signal transmission line in the embodiment of the present invention, the fault detection circuit is set in the system level chip, including the signal generation branch and the first detection branch. The signal generation branch has the same synchronizer module and function module as the signal transmission line, wherein the function module is used to receive IO signals through the synchronizer module and process the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. The first detection branch includes a first detection module and a first error injection module. The first detection module is used for judging the first signal relationship between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch, and based on the first signal relationship Signal transmission line for fault diagnosis. The first error injection module is used for judging the working state of the first detection module. Thus, the first signal relationship between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch is performed on the signal transmission line through the first detection branch Fault judgment, real-time monitoring of the signal transmitted by the signal transmission line to ensure the correctness of signal transmission, in the event of circuit failure or signal interference, timely determine the failure of the signal transmission line, which meets the high requirements of the signal transmission line Functional safety requirements. In addition, the signal generation branch and the signal transmission line have the same module configuration, so the currently idle signal transmission line can be used as the signal generation branch, effectively saving circuit resources.

It should be understood that the teaching of the present invention does not need to realize all the beneficial effects described above, but specific technical solutions can achieve specific technical effects, and other implementations of the present invention can also achieve beneficial effects not mentioned above Effect.

Description of drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are shown by way of illustration and not limitation, in which:

In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

Fig. 1 shows the composition structure diagram of the signal transmission line detected by the fault detection circuit of the embodiment of the present invention;

Fig. 2 shows a schematic diagram of the composition and structure of a fault detection circuit of a signal transmission line provided by an embodiment of the present invention;

FIG. 3 shows a schematic diagram of the composition and structure of a fault detection circuit of a signal transmission line provided by another embodiment of the present invention;

FIG. 4 shows a schematic diagram of the composition and structure of a fault detection circuit of a signal transmission line provided by another embodiment of the present invention;

FIG. 5 shows a schematic diagram of the composition and structure of a specific application example of a fault detection circuit for a signal transmission line provided by an embodiment of the present invention;

FIG. 6 shows a schematic diagram of the composition and structure of a specific application example of a fault detection circuit for a signal transmission line provided by another embodiment of the present invention;

FIG. 7 shows a schematic diagram of the composition and structure of a specific application example of a fault detection circuit for a signal transmission line provided by another embodiment of the present invention;

Fig. 8 shows a schematic flowchart of the implementation of the fault detection method for the signal transmission line provided by the embodiment of the present invention.

detailed description

The principle and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are given only to enable those skilled in the art to better understand and implement the present invention, rather than to limit the scope of the present invention in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The technical solutions of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 shows a schematic diagram of the composition and structure of a signal transmission line detected by a fault detection circuit according to an embodiment of the present invention.

Referring to FIG. 1 , two lines are used to illustrate the signal transmission line. The signal transmission line mainly transmits IO signals. The signal transmission line may include IO PAD (IO pin), synchronizer, pulse width filter and functional modules. Each signal transmission line in FIG. 1 can show the signal direction diagram of the input signal from the IO PAD to the functional module.

Specifically, the IO PAD is the pin processing module of the chip, which can not only process the received IO signal of the chip pin and send it to the chip, but also process the IO signal output inside the chip and send it to the chip pin, and further transmitted to the outside of the chip. The synchronizer can be used to perform two-stage sampling of the input IO signal to avoid the metastable state propagation of signal sampling. The pulse width filter can remove glitches of specified pulse width on IO signals. The physical wiring of the chip and the driving buffer (buffer) can be shown as the connection between different modules in FIG. 1 . The input IO signal is input into the chip from the IO PAD. First, the signal is synchronized by the synchronizer, and then the possible burrs on the IO signal are filtered by the pulse width filter, and finally enters the function module for function triggering.

It should be noted that the pulse width filter is preferably a module configured in the signal transmission line of the IO signal, and the pulse width filter may not be configured in some signal transmission lines. Since there are a large number of IO signal transmission lines that need to be connected with peripheral devices in the chip, how to ensure the correctness and stability of the IO signal transmission process in the entire chip is particularly critical. Based on this, this application designs the following A fault detection circuit and method for a signal transmission line are described.

FIG. 2 shows a schematic diagram of the composition and structure of a fault detection circuit for a signal transmission line provided by an embodiment of the present invention.

Referring to FIG. 2 , the fault detection circuit of the signal transmission line according to the embodiment of the present invention is set in a SOC (System on Chip, system-on-chip), and includes a signal generation branch 12 and a first detection branch 13 . The signal generation branch 12 has the same synchronizer module 111 and function module 112 as the signal transmission line 11 . Wherein, the function module 112 is configured to receive the IO signal through the synchronizer module 111 and process the received IO signal. The first detection branch 13 is connected between the output end of the synchronizer circuit module 111 of the signal transmission line 11 and the output end of the synchronizer circuit module 111 of the signal generation branch 12 . The first detection branch 13 includes a first detection module 131 and a first error injection module 132 . The first detection module 131 is used to judge the first signal relationship between the first intermediate signal at the output end of the synchronizer module 111 of the signal transmission line 11 and the first generated signal at the output end of the synchronizer module of the signal generation branch, and based on the first The signal relationship performs fault judgment on the signal transmission line 11 . The first error injection module 132 is used for judging the working state of the first detection module 131 .

Wherein, the first error injection module 132 is used to judge the working state of the first detection module 131 can be realized through the following operations: at the set moment, the first error injection module 132 inputs a preset error signal to the first detection module 131, the The error signal is different from the output signal of the synchronizer module 111 of the signal transmission line 11 . Therefore, when receiving the error signal, the first detection module 131 needs to be able to identify a signal error and output an error interrupt. If the first detection module 131 normally outputs an error interrupt at this time, it can be determined that the first detection module 131 is in a normal working state. In this way, the logic self-test of the first detection module 131 is realized. The judgment of the first error injection module 132 on the working state of the first detection module 131 in the following figures 2 to 7 and the judgment of the second error injection module 142 on the working state of the second detection module 141 can refer to the above description. No longer.

It should be noted that, for the fault detection circuit of the signal transmission line shown in FIG. 2 , the signal transmission line 11 and the signal generation circuit 12 may or may not have a pulse width filter module. If there is a pulse width filter module in the signal transmission line 11 , it is also preferable to configure a pulse width filter module in the signal generation branch 12 .

In order to further improve the timeliness and accuracy of fault detection of the fault detection circuit, on the basis of the fault detection circuit shown in FIG. 2 , the present invention provides another implementation as shown in FIG. 3 .

Fig. 3 shows a schematic diagram of the composition and structure of a fault detection circuit of a signal transmission line provided by another embodiment of the present invention.

Referring to FIG. 3 , in this embodiment of the present invention, both the signal generation branch 12 and the signal transmission line 11 further include a pulse width filter module 113 . Correspondingly, the fault detection circuit further includes: a second detection branch 14 connected between the output end of the pulse width filter module 113 of the signal transmission line 11 and the output end of the pulse width filter module 113 of the signal generation branch 12 . The second detection branch 14 includes: a second detection module 141 and a second error injection module 142 . The second detection module 141 is used to judge the second signal relationship between the second intermediate signal at the output end of the pulse width filter module 113 of the signal transmission line 11 and the second generated signal at the output end of the pulse width filter module 113 of the signal generation branch, and A fault judgment is performed on the signal transmission line 11 based on the second signal relationship. The second error injection module 142 is used for judging the working state of the second detection module 141 .

In this embodiment of the present invention, the second detection branch 14 may further include a selector (not shown in FIG. 2 and FIG. 3 , but shown as an IO lockstep lock synchronization circuit in FIG. 4 ). The input end of the selector is connected with the output end of the synchronizer module 111 of the signal transmission line 11 and the output end of the synchronizer module of the signal generation line 12 . The output end of the selector is connected with the input end of the pulse width filter module 113 of the signal generation branch 12, and is used to select the output end signal of the synchronizer module 111 of the signal transmission line 11 or the output end signal of the signal generation branch 12 As the input signal of the pulse width filter module 113 of the signal generating branch 12 .

Wherein, other specific implementation processes in FIG. 3 are similar to the specific implementation details in the embodiment shown in FIG. 2 , and will not be repeated here.

Fig. 4 shows a schematic diagram of the composition and structure of a fault detection circuit of a signal transmission line provided by another embodiment of the present invention.

In this embodiment of the present invention, the second detection branch 13 also includes an inverter N. The inverter N is connected between the output end of the signal transmission line 11 and the input end of the pulse width filter module 113 of the signal generation branch 12, and is used for inverting the signal at the output end of the synchronizer module 111 of the signal transmission line 11 Input to the pulse width filtering module 113 of the signal generating branch 12 . Correspondingly, the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 are configured as a filtering configuration for filtering the same pulse width and opposite pulse polarity.

It should be noted that, in the embodiments shown in Figures 2 to 4 above, if the second detection branch includes an inverter, the pulse width filter module of the signal transmission line and the pulse width filter module of the signal generation branch are configured Filter configuration for filtering same pulse width but opposite pulse polarity. If the second detection branch 14 does not include an inverter, the pulse width filter module of the signal transmission line and the pulse width filter module of the signal generation branch need to be configured as a filtering configuration for filtering the same pulse width and opposite pulse polarity.

In the embodiments of the present invention shown in FIGS. 2-4 , the first detection module 131 may be implemented by using an inequality comparison module (not shown in FIGS. 2-4 ). Correspondingly, when the first signal relationship is that the first intermediate signal and the first occurrence signal are not equal, the first detection module 131 determines that the signal transmission line 11 is faulty, and outputs a first interrupt signal.

In the embodiments of the present invention shown in Figures 2 to 4, the signal generating branch 12 can be an independently set signal transmission line identical to the signal transmission line or other signal transmission lines that are currently in an idle state and are identical to the signal transmission line. line.

Wherein, other specific implementation processes in FIG. 4 are similar to the specific implementation details in the embodiments shown in FIG. 2 and FIG. 3 , and will not be repeated here.

The implementation logic of the fault detection circuit for the signal transmission line provided by the embodiment of the present invention will be further described below in conjunction with specific application examples of the fault detection circuit for the signal transmission line provided by the embodiment of the present invention as shown in FIGS. 5 to 7 .

FIG. 5 shows a schematic diagram of the composition and structure of a specific application example of a fault detection circuit for a signal transmission line provided by an embodiment of the present invention.

Referring to FIG. 5 , an external input signal 1 is simultaneously input into the chip from IO PAD1 and IO PAD2 .

After passing through the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generation branch 12, the IO signal enters the inequality comparison module 151 for real-time comparison. If the signals output by the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generating branch 12 are not equal, an error interrupt can be reported, for example, a first interrupt can be reported to the CPU.

Further, before the signal is input to the inequality comparison module 151 through the synchronizer module 111 of the signal generation branch 12 , a first error injection module 132 is added. The first error injection module 132 can provide a logic self-test for the inequality comparison module to detect whether the working state of the inequality comparison module 151 is normal.

Here, it is based on the consideration of sampling deviation between the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generation branch 12 . In terms of physical implementation, the difference between the path delay T1 from the IO PAD 101 of the signal transmission line 11 to the synchronizer 111 and the path delay T2 from the IO PAD 101 of the signal generation branch 12 to the synchronizer 111 is less than one sampling clock cycle . That is |T1-T2|<Tclk_period, where Tclk_period represents a sampling clock period. Thus, it can be ensured that the sampling deviation of the two synchronizers is less than or equal to one period. Further, when performing signal comparison, it is necessary to filter the signal changes of the two signal edges. When the input IO signal changes in the first sampling clock cycle, the inequality comparison module 151 does not perform signal comparison, which effectively avoids the False alarms for signal transmission circuit failures.

The inequality comparison module 151 can perform real-time fault detection on all circuits on the signal transmission line from the IO PAD 101 to the synchronizer module 111 in real time to ensure the correctness of the output signal of the synchronizer module 111 .

It should be noted that, in FIGS. 4 to 7 , the signal transmission line 11 , the signal generation branch 12 , etc. are not specifically framed. You can refer to the schematic diagrams of the composition and structure of the fault detection circuit shown in Figure 2 and Figure 3, the synchronizer module 111 and the functional module 112 on the upper side of the figure belong to the signal transmission line 11, and the synchronizer module 111 and the functional module 112 on the lower side of the figure etc. belong to the signal generation line 12.

Since the output of the synchronizer module 111 of the signal transmission line 11 and the output of the synchronizer module 111 of the signal generation branch 12 must have sampling deviations, if the pulse width filter module 113 and the signal generation branch of the signal transmission line 11 are used respectively 12 of the pulse width filter module 113 input, even if there is no fault in the circuit, the output of the two pulse width filters 113 may be different, there is a large difference when the output of the pulse width filter module is detected and compared Possibility of false positives for failures.

Therefore, the correctness of the output signal of the synchronizer module 111 has been guaranteed based on the inequality comparison module 151. Here, only the output of the synchronizer module 111 of the signal transmission line can be used as the pulse width filtering module 113 and the signal generation of the signal transmission line 11 at the same time. The input of the pulse width filtering module 113 of the branch 12. The pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12 are further compared by the equality comparison module 152 . At the same time, the output of the synchronizer module 111 of the signal transmission branch 11 can be inverted by the inverter N and then input to the pulse width filter module 113 of the signal generation branch. In this way, common cause interference that may occur between the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12 can be eliminated. At this time, the software pulse filtering configurations of the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 need to be configured to filter with the same pulse width and different pulse polarity. For example, if the pulse width filter module 113 of the signal transmission line 11 is configured to filter positive edge pulses of 3 cycles, the pulse width filter module 113 of the signal generating branch 12 needs to be configured to filter negative edge pulses of 3 cycles.

After passing through the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generating branch 12 , the signal is input to the equality comparison module 152 . The equal comparison module 152 only needs to compare whether the two signals input by the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12 are equal, and if they are equal, an interrupt error will be generated, for example: A second interrupt may be generated and reported to the CPU.

Likewise, before the output signal of the pulse width filtering module 113 of the signal generation branch 12 is input to the equality comparison module 152 , a second error injection module 142 is added. A logic self-test for the equality comparison module 152 may be provided by the second error injection module 142 .

The output of the pulse width filter module 113 of the signal transmission line 11 is monitored in real time by the equality comparison module 152 to effectively ensure the correctness of the output signal of the pulse width filter module 113 of the signal transmission line 11 . Further, the output signal of the pulse width filter module 113 of the signal transmission line 11 is input to the function module 112 of the signal transmission line 11 to trigger the function.

It should be noted that the inverter N may not be added between the synchronizer module 111 and the pulse width filtering module 113 of the signal generating branch 12 . At this point, the circuit and software configuration need to be adjusted. Specifically, reference may be made to the embodiment shown in FIG. 6 .

FIG. 6 shows a schematic diagram of the composition and structure of a specific application example of a fault detection circuit for a signal transmission line provided by another embodiment of the present invention.

Referring to FIG. 6 , no inverter N is arranged between the synchronizer module 111 and the pulse width filter module 113 of the signal generating branch 12 . At this time, the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12 need to be configured to filter with the same pulse width and the same pulse polarity. For example, if the pulse width filter module 113 of the signal transmission line 11 is configured to filter positive edge pulses of 3 cycles, the pulse width filter module 113 of the signal generation branch 12 also needs to be configured to filter positive edge pulses of 3 cycles.

Further, the equality comparison module 152 shown in FIG. 5 needs to be replaced with another inequality comparison module 151 . Thus, the inequality comparing module 151 compares the two input signals of the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 for inequality. If the two signals input by the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12 are not equal, an interrupt error is generated, for example: a second interrupt can be generated, and the second interrupt can be reported to CPU.

Furthermore, based on the specific application example of the fault detection circuit of the signal transmission line shown in Figure 5, when the chip is used in some application fields with slightly lower functional safety requirements, the currently idle signal transmission line can be released as a signal generation support road. At this point, some software configuration changes need to be made. For details, please refer to FIG. 7 .

Fig. 7 shows a schematic composition structure diagram of a specific application example of a fault detection circuit for a signal transmission line provided by another embodiment of the present invention.

As shown in FIG. 7 , the input enable signal io_lockstep_en of the IO lockstep (IO lock synchronization circuit) can be set to 0 by software, then the output signal of the synchronizer module 111 of the currently idle signal transmission line can be input to different The comparison module 151 compares the signal at the output end of the synchronizer module 111 of the signal transmission line currently requiring fault detection to realize the fault detection of the signal transmission line currently requiring fault detection.

If the currently idle signal transmission line needs to enable the signal transmission function, the inequality comparison module 151 and the equality comparison module 152 can be turned off by software.

In the fault detection circuit, method, chip, electronic device and vehicle of the signal transmission line in the embodiment of the present invention, the fault detection circuit is set in the system level chip, including the signal generation branch and the first detection branch. The signal generation branch has the same synchronizer module and function module as the signal transmission line, wherein the function module is used to receive IO signals through the synchronizer module and process the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. The first detection branch includes a first detection module and a first error injection module. The first detection module is used for judging the first signal relationship between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch, and based on the first signal relationship Signal transmission line for fault diagnosis. The first error injection module is used for judging the working state of the first detection module. Thus, the first signal relationship between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch is performed on the signal transmission line through the first detection branch Fault judgment, real-time monitoring of the signal transmitted by the signal transmission line to ensure the correctness of signal transmission, in the event of circuit failure or signal interference, timely determine the failure of the signal transmission line, which meets the high requirements of the signal transmission line Functional safety requirements. In addition, the signal generation branch and the signal transmission line have the same module configuration, so the currently idle signal transmission line can be used as the signal generation branch, effectively saving circuit resources.

Similarly, based on the above fault detection circuit of the signal transmission line, the embodiment of the present invention also provides a fault detection method of the signal transmission line, as shown in FIG. The first intermediate signal at the output end of the synchronizer module and the first generated signal at the output end of the synchronizer module of the signal generation branch; in operation 802, the first signal relationship between the first intermediate signal and the first generated signal satisfies the first setting condition When the first interrupt command is output.

Furthermore, based on the above-mentioned fault detection circuit for the signal transmission line, an embodiment of the present invention further provides a chip, and the chip includes the above-mentioned fault detection circuit for the signal transmission line.

Furthermore, based on the above fault detection circuit of the signal transmission line, an embodiment of the present invention also provides an electronic device, which includes the above-mentioned chip.

Still further, based on the above fault detection circuit of the signal transmission line, an embodiment of the present invention also provides a vehicle, which includes the above-mentioned electronic device.

It should be pointed out here that: the above description of the fault detection method for the signal transmission line, the chip, the electronic equipment and the vehicle embodiment are similar to the description of the method embodiment shown in Figures 1 to 7, and have the same The embodiment of the fault detection circuit of the transmission line shown in FIGS. 1 to 7 has similar beneficial effects, so details are not repeated here. For the technical details not disclosed in the transmission line fault detection method, chip, electronic equipment, and vehicle embodiments of the present invention, please refer to the description of the fault detection circuit embodiment of the transmission line shown in Figures 1 to 7 of the present invention for understanding , in order to save space, it is not repeated here.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration The unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above method embodiments can be completed by hardware related to program instructions, and the aforementioned programs can be stored in computer-readable storage media. When the program is executed, the execution includes: The steps of the above-mentioned method embodiments; and the aforementioned storage medium includes: various media capable of storing program codes such as removable storage devices, read only memory (Read Only Memory, ROM), magnetic disks or optical disks.

Alternatively, if the above-mentioned integrated units of the present invention are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for Make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the methods in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program codes such as removable storage devices, ROMs, magnetic disks or optical disks.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present invention, and should cover all Within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (11)

1. A fault detection circuit of a signal transmission line, said fault detection circuit is arranged in a SoC, comprising: The signal generation branch has a synchronizer module and a function module identical to the signal transmission line, and the function module is used to receive the IO signal through the synchronizer module and process the received IO signal; The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch, including: The first detection module is used to judge the first signal relationship between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch, and based on The first signal relationship performs fault judgment on the signal transmission line; The first error injection module is used to judge the working state of the first detection module. 2. The circuit according to claim 1, the first detection module is an inequality comparison module; correspondingly, When the first signal relationship is that the first intermediate signal is not equal to the first occurrence signal, the first detection module determines that the signal transmission line is faulty, and outputs a first interrupt signal. 3. The circuit according to claim 1, the signal generation branch and the signal transmission line also include a pulse width filter module; correspondingly, the fault detection circuit also includes: The second detection branch is connected between the output end of the pulse width filter module of the signal transmission line and the output end of the pulse width filter module of the signal generation branch, including: The second detection module is used to judge the second signal relationship between the second intermediate signal at the output end of the pulse width filter module of the signal transmission line and the second signal generated at the output end of the pulse width filter module of the signal generation branch, and performing fault judgment on the signal transmission line based on the second signal relationship; The second error injection module is used to judge the working state of the second detection module. 4. The circuit of claim 3, the second detection branch further comprising: A selector, the input end of which is connected to the output end of the synchronizer module of the signal transmission line and the output end of the synchronizer module of the signal generation line, and the output end is connected to the input end of the pulse width filter module of the signal generation branch are connected, and are used to select the output signal of the synchronizer module of the signal transmission line or the output signal of the signal generation branch as the input signal of the pulse width filter module of the signal generation branch. 5. The circuit according to claim 4, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch are configured as a filtering configuration for filtering the same pulse width but opposite pulse polarity. 6. The circuit of claim 4, the second detection branch further comprising: an inverter, connected between the output end of the synchronizer module of the signal transmission line and the input end of the pulse width filter module of the signal generation branch, and used to transfer the output signal of the synchronizer module of the signal transmission line input to the pulse width filtering module of the signal generation branch after reverse; correspondingly, The pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch are configured as a filtering configuration for filtering the same pulse width but opposite pulse polarity. 7. The circuit according to claim 1, the signal generation branch is an independently set signal transmission line identical to the signal transmission line or another signal transmission line identical to the signal transmission line currently in an idle state . 8. A fault detection method for a signal transmission line, said method comprising: receiving the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch; Outputting a first interruption instruction when a first signal relationship between the first intermediate signal and the first generation signal satisfies a first setting condition. 9. A chip, comprising the signal transmission line fault detection circuit according to any one of claims 1-6. 10. An electronic device comprising the chip of claim 9. 11. A vehicle comprising the electronic device of claim 10.

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