CN115453315A - Fault detection circuit, method and chip of signal transmission line - Google Patents

Abstract

The invention discloses a fault detection circuit, a fault detection method, a chip, electronic equipment and a vehicle of a signal transmission line. The signal generation branch circuit is provided with a synchronizer module and a functional module which are the same as the signal transmission line, wherein the functional module is used for receiving IO signals through the synchronizer module and processing the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. Therefore, the first detection branch circuit judges the fault of the signal transmission line according to the first signal relation between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch circuit, and monitors the signal transmitted by the signal transmission line in real time.

Description

Fault detection circuit, method and chip of signal transmission line

Technical Field

The present invention relates to the field of microprocessor technologies, and in particular, to a fault detection circuit, a fault detection method, a fault detection chip, an electronic device, and a vehicle for a signal transmission line.

Background

With the popularization of intelligent devices, the use requirements of chips are higher and higher. A large number of IO (Input Output) signal transmission lines are usually arranged in a chip to connect with peripheral devices, how to ensure the correctness of an IO signal in the whole chip transmission process and how to perform effective real-time fault detection on the IO signal are very critical elements for a high-functional safety chip and a system using the chip. Especially for input signals with high importance, in order to ensure the accuracy of signal transmission, it is necessary to monitor a signal transmission line in real time, so that when any circuit fault or signal interference occurs in a signal path, the signal can be detected and reported in real time.

Disclosure of Invention

In order to solve the above problems, embodiments of the present invention provide a fault detection circuit, a fault detection method, a chip, an electronic device, and a vehicle for a signal transmission line.

According to a first aspect of the present invention, there is provided a fault detection circuit of a signal transmission line, the fault detection circuit being provided in a system on a chip, comprising: the signal generation branch circuit is provided with a synchronizer module and a functional module which are the same as the signal transmission line, and the functional module is used for receiving IO signals through the synchronizer module and processing the received IO signals; first detection branch road, connect in between signal transmission line's the synchronizer circuit module output of module output and signal generation branch road's the synchronizer circuit module output, include: a first detection module, configured to determine a first signal relationship between a first intermediate signal at an output end of a synchronizer module of the signal transmission line and a first generated signal at an output end of the synchronizer module of the signal generation branch, and perform fault determination on the signal transmission line based on the first signal relationship; and the first error injection module is used for judging the working state of the first detection module.

According to an embodiment of the present invention, the first detecting module is an unequal comparison module; correspondingly, when the first signal relationship is that the first intermediate signal and the first generated signal are not equal, the first detection module determines that the signal transmission line has a fault, and outputs a first interrupt signal.

According to an embodiment of the present invention, each of the signal generating branch and the signal transmission line further comprises a pulse width filter module; correspondingly, the fault detection circuit further comprises: the second detects the branch road, connect in signal transmission line's pulse width filter module output with between the pulse width filter module output of branch road takes place for the signal, include: a second detection module, configured to determine a second signal relationship between a second intermediate signal at the output end of the pulse width filter module of the signal transmission line and a second generated signal at the output end of the pulse width filter module of the signal generation branch, and perform fault determination on the signal transmission line based on the second signal relationship; and the second error injection module is used for judging the working state of the second detection module.

According to an embodiment of the present invention, the second detection branch further includes: and the input end of the selector is connected with the output end of the synchronizer module of the signal transmission line and the output end of the synchronizer module of the signal generation line, and the output end of the selector is connected with the input end of the pulse width filter module of the signal generation branch, and the selector is used for selecting the output end signal of the synchronizer module of the signal transmission line or the output end signal of the signal generation branch as the input signal of the pulse width filter module of the signal generation branch.

According to an embodiment of the invention, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch are configured as a filtering configuration for filtering pulses of opposite polarity of the same pulse width.

According to an embodiment of the present invention, the second detection branch further includes: the inverter is connected between the output end of the synchronizer module of the signal transmission line and the input end of the pulse width filtering module of the signal generation branch, and is used for inverting the signal at the output end of the synchronizer module of the signal transmission line and inputting the inverted signal to the pulse width filtering module of the signal generation branch; accordingly, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch are configured as a filtering configuration for filtering the same pulse width with opposite pulse polarities.

According to an embodiment of the present invention, the signal generating branch is a signal transmission line which is the same as the signal transmission line and is independently provided, or another signal transmission line which is the same as the signal transmission line and is currently in an idle state.

According to the second aspect of the present invention, there is also provided a fault detection method of a signal transmission line, the method including: receiving a first intermediate signal at an output terminal of a synchronizer module of the signal transmission line and a first generation signal at an output terminal of the synchronizer module of the signal generation branch; and outputting a first interrupt instruction when a first signal relation between the first intermediate signal and the first generation signal meets a first set condition.

According to the third aspect of the present invention, there is also provided a chip including the above-described signal transmission line fault detection circuit.

According to a fourth aspect of the present invention, there is also provided an electronic device, which includes the above chip.

According to a fifth aspect of the present invention, there is also provided a vehicle including the above electronic apparatus.

In the fault detection circuit, the fault detection method, the chip, the electronic device and the vehicle of the signal transmission line, the fault detection circuit is arranged in a system-level chip and comprises a signal generation branch and a first detection branch. The signal generation branch circuit is provided with a synchronizer module and a functional module which are the same as the signal transmission line, wherein the functional module is used for receiving IO signals through the synchronizer module and processing the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. The first detection branch comprises a first detection module and a first error injection module. The first detection module is used for judging a first signal relation between a first intermediate signal at the output end of the synchronizer module of the signal transmission line and a first generated signal at the output end of the synchronizer module of the signal generation branch, and carrying out fault judgment on the signal transmission line based on the first signal relation. The first error injection module is used for judging the working state of the first detection module. Therefore, the first detection branch circuit carries out fault judgment on the signal transmission line according to the first signal relation between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch circuit, the signals transmitted by the signal transmission line are monitored in real time, the correctness of signal transmission is ensured, when the problems of circuit fault or signal interference and the like occur, the signal transmission line is judged to have faults in time, and the high-function safety requirement on the signal transmission line is met. In addition, the signal generation branch and the signal transmission line have the same module arrangement, so that the currently idle signal transmission line can be used as the signal generation branch, and the circuit resource is effectively saved.

It is to be understood that the teachings of the present invention need not achieve all of the above-described benefits, but rather that specific embodiments may achieve specific technical results, and that other embodiments of the present invention may achieve benefits not mentioned above.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

Fig. 1 is a schematic diagram showing a configuration of a signal transmission line detected by a fault detection circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating a configuration of a fault detection circuit of a signal transmission line according to an embodiment of the present invention;

fig. 3 is a schematic diagram showing a configuration of a fault detection circuit of a signal transmission line according to another embodiment of the present invention;

fig. 4 is a schematic diagram showing a configuration of a fault detection circuit of a signal transmission line according to still another embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a configuration of a specific application example of a fault detection circuit of a signal transmission line according to an embodiment of the present invention;

fig. 6 is a schematic diagram showing a configuration of a specific application example of a fault detection circuit of a signal transmission line according to another embodiment of the present invention;

fig. 7 is a schematic diagram illustrating a configuration of a specific application example of a fault detection circuit of a signal transmission line according to still another embodiment of the present invention;

fig. 8 shows a schematic implementation flow diagram of a fault detection method for a signal transmission line according to an embodiment of the present invention.

Detailed Description

The principles and spirit of the present invention will be described with reference to a number of exemplary embodiments. It is understood that these embodiments are given only to enable those skilled in the art to better understand and to implement the present invention, and do not limit the scope of the present invention in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The technical scheme of the invention is further elaborated by combining the attached drawings and specific embodiments.

Fig. 1 is a schematic diagram showing a configuration of a signal transmission line detected by a fault detection circuit according to an embodiment of the present invention.

Referring to fig. 1, signal transmission lines are shown in two lines, the signal transmission lines primarily transmitting IO signals, which may include IO PADs (IO pins), synchronizers, pulse width filters, and functional blocks. Each signal transmission line in fig. 1 may show a signal trace of an input signal from an IO PAD to a functional module.

Specifically, the IO PAD is a pin processing module of the chip, and can send an IO signal received by a chip pin to the inside of the chip through processing, and can send an IO signal output by the inside of the chip to the outside of the chip through processing. The synchronizer may be used to sample the input IO signal in two stages to avoid metastability propagation of the signal samples. The pulse width filter may remove glitches on the IO signal specifying the pulse width. The physical routing and drive buffers of the chip may be illustrated as the connections between the different modules in fig. 1. The input IO signal is input into the chip from the IO PAD, the signal is synchronized through the synchronizer firstly, then burrs possibly existing on the IO signal are filtered through the pulse width filter, and finally the IO signal enters the functional module to be triggered in function.

The pulse width filter is preferably disposed in the signal transmission line of the IO signal, and the pulse width filter may not be disposed in some of the signal transmission lines. Because a large number of IO signal transmission lines which need to be connected with peripheral devices exist in a chip, how to ensure the correctness and stability of the IO signals in the transmission process in the whole chip is particularly critical.

Fig. 2 is a schematic diagram illustrating a configuration of a fault detection circuit of a signal transmission line according to an embodiment of the present invention.

Referring to fig. 2, the fault detection circuit of the signal transmission line according to the embodiment of the present invention is disposed in an SOC (System on Chip), and includes a signal generation branch 12 and a first detection branch 13. The signal generating branch 12 has the same synchronizer block 111 and function block 112 as the signal transmission line 11. The functional module 112 is configured to receive an IO signal through the synchronizer module 111 and process the received IO signal. The first detection branch 13 is connected between the output of the synchronizer circuit module 111 of the signal transmission line 11 and the output of the synchronizer circuit module 111 of the signal generation branch 12. The first detection branch 13 includes a first detection module 131 and a first staggering module 132. The first detection module 131 is configured to determine a first signal relationship between the first intermediate signal at the output end of the synchronizer module 111 of the signal transmission line 11 and the first generated signal at the output end of the synchronizer module of the signal generation branch, and perform fault determination on the signal transmission line 11 based on the first signal relationship. The first error injection module 132 is used for determining an operating state of the first detection module 131.

The first error injection module 132 is configured to determine the working state of the first detection module 131 by: the first error injection module 132 inputs a predetermined error signal to the first detection module 131 at a predetermined timing, and the error signal is different from the output signal of the synchronizer module 111 of the signal transmission line 11. Thus, the first detection module 131 needs to be able to recognize a signal error and output an error interrupt when receiving the error signal. If the first detecting module 131 normally outputs an error interrupt at this time, it may be determined that the first detecting module 131 is in a normal operating state. Thereby, a logical self-test of the first detection module 131 is achieved. In the following fig. 2 to fig. 7, the determination of the working state of the first detection module 131 by the first error injection module 132 and the determination of the working state of the second detection module 141 by the second error injection module 142 can both refer to the above description, and are not described again below.

In the fault detection circuit of the signal transmission line shown in fig. 2, the signal transmission line 11 and the signal generation circuit 12 may or may not have a pulse width filter module. If the signal transmission line 11 has a pulse width filter module, the signal generating branch 12 is preferably also provided with a pulse width filter module.

In order to further improve the timeliness and accuracy of fault detection of the fault detection circuit, the invention provides another embodiment as shown in fig. 3 on the basis of the fault detection circuit shown in fig. 2.

Fig. 3 is a schematic diagram illustrating a configuration of a fault detection circuit of a signal transmission line according to another embodiment of the present invention.

Referring to fig. 3, in this embodiment of the present invention, the signal generating branch 12 and the signal transmission line 11 each further include a pulse width filter module 113. Correspondingly, the fault detection circuit further comprises: the second detection branch 14 is connected between the output end of the pulse width filter module 113 of the signal transmission line 11 and the output end of the pulse width filter module 113 of the signal generation branch 12. The second detection branch 14 comprises: a second detection module 141 and a second error injection module 142. The second detecting module 141 is configured to determine a second signal relationship between the second intermediate signal at the output end of the pulse width filter module 113 of the signal transmission line 11 and the second generating signal at the output end of the pulse width filter module 113 of the signal generating branch, and perform fault determination on the signal transmission line 11 based on the second signal relationship. And the second error injection module 142 is configured to determine an operating state of the second detection module 141.

In this embodiment of the present invention, the second detection branch 14 may further include a selector (not shown in fig. 2 and 3, but shown in fig. 4 as an IO lockstep lock synchronization circuit). The input of the selector is connected to the output of the synchronizer module 111 of the signal transmission line 11 and to the output of the synchronizer module of the signal generation line 12. The output of the selector is connected to the input of the pulse width filter module 113 of the signal generating branch 12 for selecting either the signal at the output of the synchronizer module 111 of the signal transmission line 11 or the signal at the output of the signal generating branch 12 as the input signal of the pulse width filter module 113 of the signal generating branch 12.

The other specific implementation process of fig. 3 is similar to the specific implementation details in the embodiment shown in fig. 2, and is not described here again.

Fig. 4 is a schematic diagram showing a configuration of a fault detection circuit of a signal transmission line according to still another embodiment of the present invention.

In this embodiment of the invention, the second detection branch 13 further comprises an inverter N. The inverter N is connected between the output end of the signal transmission line 11 and the input end of the pulse width filtering module 113 of the signal generating branch 12, and is configured to invert the signal at the output end of the synchronizer module 111 of the signal transmission line 11 and input the inverted signal to the pulse width filtering module 113 of the signal generating branch 12. Accordingly, the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 are configured as a filtering configuration for filtering the same pulse width with opposite pulse polarities.

It should be noted that, as in the embodiments shown in fig. 2 to 4, if the second detection branch includes an inverter, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generation branch are configured as a filtering configuration for filtering pulses of the same pulse width but of opposite pulse polarity. If the second detection branch 14 does not comprise an inverter, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generation branch need to be configured as a filtering configuration for filtering pulses of the same pulse width but opposite pulse polarity.

In the embodiment of the present invention as shown in fig. 2 to 4, the first detection module 131 may be implemented by an unequal comparison module (not shown in fig. 2 to 4). Accordingly, when the first signal relationship is that the first intermediate signal and the first generated signal are not equal, the first detection module 131 determines that the signal transmission line 11 has a fault, and outputs a first interrupt signal.

In the embodiments of the present invention shown in fig. 2 to 4, the signal generating branch 12 may be a signal transmission line which is the same as the signal transmission line and is independently installed or another signal transmission line which is currently in an idle state and is the same as the signal transmission line.

The other specific implementation process of fig. 4 is similar to the specific implementation details in the embodiments shown in fig. 2 and fig. 3, and is not described here again.

The following describes the implementation logic of the fault detection circuit of the signal transmission line according to the embodiment of the present invention with reference to specific application examples of the fault detection circuit of the signal transmission line according to the embodiment of the present invention shown in fig. 5 to fig. 7.

Fig. 5 is a schematic diagram illustrating a specific application example of the fault detection circuit of the signal transmission line according to an embodiment of the present invention.

Referring to fig. 5, an external input signal 1 is simultaneously input from IO PAD1 and IO PAD2 to the inside of the chip.

The IO signal passes through the synchronizer block 111 of the signal transmission line 11 and the synchronizer block 111 of the signal generation branch 12, and then enters the unequal comparison block 151 to be compared in real time. If the signals output by the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generating branch 12 are not equal, an error interrupt may be reported, for example: the first interrupt may be reported to the CPU.

Further, the first error injection module 132 is added before the signal is input to the unequal comparison module 151 through the synchronizer module 111 of the signal generation branch 12. A logic self-test of the unequal comparison module may be provided by the first error injection module 132 to detect whether the operation state of the unequal comparison module 151 is normal.

Here, the deviation of the sampling is considered in the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generation branch 12. The difference between the path delay T1 from the IO PAD 101 of the signal transmission line 11 to the synchronizer 111 and the path delay T2 from the IO PAD 101 of the signal generating branch 12 to the synchronizer 111 is constrained by physical implementation to be less than one sampling clock period. I.e., T1-T2 < Tclk _ period, where Tclk _ period represents one sampling clock cycle. Therefore, the sampling deviation of the two synchronizers can be ensured to be less than or equal to one period. Furthermore, when signal comparison is performed, signal changes of two signal edges need to be filtered, and when the input IO signal changes in the first sampling clock period, the unequal comparison module 151 does not perform signal comparison, thereby effectively avoiding fault misinformation of the signal transmission circuit caused by sampling deviation.

The unequal comparison module 151 can perform real-time fault detection on all circuits on a signal transmission path between the IO PAD 101 and the synchronizer module 111 on the signal transmission line in real time, so as to ensure the correctness of the output signal of the synchronizer module 111.

In fig. 4 to 7, the signal transmission line 11, the signal generation branch 12, and the like are not specifically selected. Referring to the schematic configuration of the fault detection circuit shown in fig. 2 and 3, the synchronizer module 111 and the functional module 112, etc. located on the upper side of the figure belong to the signal transmission line 11, and the synchronizer module 111 and the functional module 112, etc. located on the lower side of the figure belong to the signal generation line 12.

Since there is always a sampling variation in the outputs of the synchronizer module 111 of the signal transmission line 11 and the synchronizer module 111 of the signal generation branch 12, if the outputs are respectively used as the inputs of the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generation branch 12, even if there is no fault in the circuit, the outputs of the two pulse width filters 113 may not be the same, and there is a high possibility of false alarm of fault when detecting and comparing the outputs of the pulse width filtering modules.

Therefore, based on the unequal comparison module 151 having guaranteed the correctness of the output signal of the synchronizer module 111, here, only the output of the synchronizer module 111 of the signal transmission line may be adopted as the input of both the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12. To further compare the pulse width filtering module 113 of the signal transmission line 11 with the pulse width filtering module 113 of the signal generating branch 12 through the equality comparing module 152. Meanwhile, the output of the synchronizer module 111 of the signal transmission branch 11 may be inverted by the inverter N and then input to the pulse width filter module 113 of the signal generation branch. In this way, the common cause interference which may occur in the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 can be eliminated. At this time, the software pulse filtering configurations of the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 need to be configured to be the same pulse width and different pulse polarity filtering. For example, if the pulse width filtering module 113 of the signal transmission line 11 configures 3 cycles of positive edge pulse filtering, the pulse width filtering module 113 of the signal generation branch 12 needs to configure 3 cycles of negative edge pulse filtering.

After passing through the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12, the signals are input to the equality comparing module 152. The equality comparison module 152 only needs to compare whether the two signals input by the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generation branch 12 are equal, and if they are equal, an interrupt error is generated, for example: a second interrupt may be generated and reported to the CPU.

Similarly, a second error injection module 142 is added before the output signal of the pulse width filtering module 113 of the signal generating branch 12 is input to the equal comparison module 152. A logical self-test of the equality comparison module 152 may be provided by the second error injection module 142.

The output of the pulse width filtering module 113 of the signal transmission line 11 is monitored in real time through the equal comparing module 152, so that the correctness of the output signal of the pulse width filtering module 113 of the signal transmission line 11 is effectively ensured. Further, the output signal of the pulse width filter module 113 of the signal transmission line 11 is input to the function module 112 of the signal transmission line 11 to trigger the function.

It should be noted that the inverter N may not be added between the synchronizer module 111 and the pulse width filter module 113 of the signal generation branch 12. At this time, the circuit and software configuration need to be adjusted. In particular, reference may be made to the embodiment shown in fig. 6.

Fig. 6 is a schematic diagram showing a configuration of a specific application example of the fault detection circuit of the signal transmission line according to another embodiment of the present invention.

Referring to fig. 6, the inverter N is not disposed between the synchronizer module 111 and the pulse width filter module 113 of the signal generating branch 12. At this time, the software pulse filtering configurations of the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 need to be configured to be the same pulse width and the same pulse polarity. For example, if the pulse width filtering module 113 of the signal transmission line 11 configures 3 cycles of positive edge pulse filtering, the pulse width filtering module 113 of the signal generating branch 12 also needs to configure 3 cycles of positive edge pulse filtering.

Further, the equal comparison module 152 shown in fig. 5 needs to be replaced with another unequal comparison module 151. Thus, the unequal comparison module 151 performs unequal comparison between the two input signals, the pulse width filter module 113 of the signal transmission line 11 and the pulse width filter module 113 of the signal generation branch 12. If the two signals input by the pulse width filtering module 113 of the signal transmission line 11 and the pulse width filtering module 113 of the signal generating branch 12 are not equal, an interrupt error is generated, for example: a second interrupt may be generated and reported to the CPU.

Further, based on the specific application example of the fault detection circuit of the signal transmission line shown in fig. 5, when the chip is in some application fields with slightly lower functional safety requirements, the currently idle signal transmission line can be released as a signal generation branch. At this point, some software configuration changes need to be made. Reference may be made in particular to fig. 7.

Fig. 7 is a schematic diagram showing a configuration of a specific application example of the fault detection circuit of the signal transmission line according to still another embodiment of the present invention.

Referring to fig. 7, if the input enable signal IO _ lockstep _ en of the IO lock synchronization circuit is set to 0 by software, the output end signal of the synchronizer module 111 of the currently idle signal transmission line may be input to the unequal comparison module 151, and compared with the output end signal of the synchronizer module 111 of the signal transmission line currently required to be subjected to fault detection, so as to implement fault detection of the signal transmission line currently required to be subjected to fault detection.

If the currently idle signal transmission line needs to enable the signal transmission function, the unequal comparison module 151 and the equal comparison module 152 may be turned off by software.

In the fault detection circuit, the fault detection method, the chip, the electronic device and the vehicle of the signal transmission line, the fault detection circuit is arranged in a system-level chip and comprises a signal generation branch and a first detection branch. The signal generation branch circuit is provided with a synchronizer module and a function module which are the same as the signal transmission line, wherein the function module is used for receiving IO signals through the synchronizer module and processing the received IO signals. The first detection branch is connected between the output end of the synchronizer circuit module of the signal transmission line and the output end of the synchronizer circuit module of the signal generation branch. The first detection branch comprises a first detection module and a first error injection module. The first detection module is used for judging a first signal relation between a first intermediate signal at the output end of the synchronizer module of the signal transmission line and a first generated signal at the output end of the synchronizer module of the signal generation branch, and performing fault judgment on the signal transmission line based on the first signal relation. The first error injection module is used for judging the working state of the first detection module. Therefore, the first detection branch circuit carries out fault judgment on the signal transmission line according to the first signal relation between the first intermediate signal at the output end of the synchronizer module of the signal transmission line and the first generated signal at the output end of the synchronizer module of the signal generation branch circuit, the signals transmitted by the signal transmission line are monitored in real time, the correctness of signal transmission is ensured, when the problems of circuit fault or signal interference and the like occur, the signal transmission line is judged to have faults in time, and the high-function safety requirement on the signal transmission line is met. In addition, the signal generation branch and the signal transmission line have the same module arrangement, so that the currently idle signal transmission line can be used as the signal generation branch, and the circuit resource is effectively saved.

Similarly, based on the above fault detection circuit of the signal transmission line, the embodiment of the present invention further provides a fault detection method of the signal transmission line, as shown in fig. 8, the method at least includes the following procedures: operation 801, receiving a first intermediate signal at a synchronizer module output of a signal transmission line and a first generated signal at a synchronizer module output of a signal generation branch; in operation 802, a first interrupt instruction is output when a first signal relationship of the first intermediate signal and the first generation signal satisfies a first set condition.

Further, based on the fault detection circuit of the signal transmission line, the embodiment of the present invention further provides a chip, where the chip includes the fault detection circuit of the signal transmission line.

Furthermore, based on the fault detection circuit of the signal transmission line, the embodiment of the invention also provides an electronic device, and the electronic device comprises the chip.

Still further, based on the fault detection circuit of the signal transmission line, the embodiment of the invention also provides a vehicle, and the vehicle comprises the electronic equipment.

It is to be noted here that: the above descriptions of the fault detection method, the chip, the electronic device, and the vehicle embodiment for the signal transmission line are similar to the descriptions of the method embodiments shown in fig. 1 to 7, and have similar beneficial effects to the fault detection circuit embodiments of the transmission line shown in fig. 1 to 7, and therefore are not repeated. For technical details that are not disclosed in the embodiments of the transmission line fault detection method, the chip, the electronic device, and the vehicle of the present invention, please refer to the description of the transmission line fault detection circuit embodiments shown in fig. 1 to fig. 7 of the present invention for understanding, and therefore, for brevity, detailed description is omitted.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in a process, method, article, or apparatus comprising the element.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of a unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Those of ordinary skill in the art will understand that: all or part of the steps of implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer-readable storage medium, and when executed, executes the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.

Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods of the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (11)

1. A fault detection circuit of a signal transmission line, the fault detection circuit being provided in a system-on-chip, comprising:

the signal generation branch circuit is provided with a synchronizer module and a functional module which are the same as the signal transmission line, and the functional module is used for receiving IO signals through the synchronizer module and processing the received IO signals;

first detection branch road, connect in between the synchronizer circuit module output of signal transmission line's synchronizer circuit module output and the signal generation branch road, include:

a first detection module, configured to determine a first signal relationship between a first intermediate signal at an output end of a synchronizer module of the signal transmission line and a first generated signal at an output end of the synchronizer module of the signal generation branch, and perform fault determination on the signal transmission line based on the first signal relationship;

and the first error injection module is used for judging the working state of the first detection module.

2. The circuit of claim 1, the first detection module being an unequal comparison module; accordingly, the method can be used for solving the problems that,

and when the first signal relation is that the first intermediate signal and the first generated signal are not equal, the first detection module judges that the signal transmission line has a fault and outputs a first interrupt signal.

3. The circuit of claim 1, the signal generating branch and the signal transmission line each further comprising a pulse width filter module; correspondingly, the fault detection circuit further comprises:

the second detects the branch road, connect in signal transmission line's pulse width filter module output with between the pulse width filter module output of branch road takes place for the signal, include:

a second detection module, configured to determine a second signal relationship between a second intermediate signal at the output end of the pulse width filter module of the signal transmission line and a second generated signal at the output end of the pulse width filter module of the signal generation branch, and perform fault determination on the signal transmission line based on the second signal relationship;

and the second error injection module is used for judging the working state of the second detection module.

4. The circuit of claim 3, the second detection branch further comprising:

and the input end of the selector is connected with the output end of the synchronizer module of the signal transmission line and the output end of the synchronizer module of the signal generation line, and the output end of the selector is connected with the input end of the pulse width filter module of the signal generation branch and used for selecting the output end signal of the synchronizer module of the signal transmission line or the output end signal of the signal generation branch as the input signal of the pulse width filter module of the signal generation branch.

5. The circuit of claim 4, the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch being configured in a filtering configuration for filtering the same pulse width with opposite pulse polarity.

6. The circuit of claim 4, the second detection branch further comprising:

the inverter is connected between the output end of the synchronizer module of the signal transmission line and the input end of the pulse width filtering module of the signal generation branch, and is used for inverting the signal at the output end of the synchronizer module of the signal transmission line and inputting the inverted signal to the pulse width filtering module of the signal generation branch; accordingly, the method has the advantages that,

the pulse width filtering module of the signal transmission line and the pulse width filtering module of the signal generating branch are configured as a filtering configuration for filtering the same pulse width with opposite pulse polarities.

7. The circuit according to claim 1, wherein the signal generating branch is a signal transmission line which is the same as the signal transmission line and is independently provided, or another signal transmission line which is the same as the signal transmission line and is currently in an idle state.

8. A method of fault detection of a signal transmission line, the method comprising:

receiving a first intermediate signal at an output terminal of a synchronizer module of the signal transmission line and a first generation signal at an output terminal of the synchronizer module of the signal generation branch;

and outputting a first interrupt instruction when a first signal relation between the first intermediate signal and the first generation signal meets a first set condition.

9. A chip comprising the signal transmission line fault detection circuit of any one of claims 1-6.

10. An electronic device comprising the chip of claim 9.

11. A vehicle comprising the electronic device of claim 10.

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