CN115377201A - Asymmetric electrode reconfigurable transistor operated by source-drain voltage and debugging method - Google Patents

Asymmetric electrode reconfigurable transistor operated by source-drain voltage and debugging method Download PDF

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CN115377201A
CN115377201A CN202211067410.9A CN202211067410A CN115377201A CN 115377201 A CN115377201 A CN 115377201A CN 202211067410 A CN202211067410 A CN 202211067410A CN 115377201 A CN115377201 A CN 115377201A
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drain
electrode
nanowire
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余林蔚
钱文涛
王军转
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Nanjing University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract

The invention discloses an asymmetric electrode reconfigurable transistor operated by source-drain voltage, which comprises a substrate and doped nanowire arrays distributed in a multi-step channel arranged on the substrate, drain contact metals and source contact metals are respectively precipitated at two ends of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, and a gate dielectric layer and a gate thin film layer are deposited above the space between the drain contact metals and the source contact metals at the two ends of the substrate. Asymmetric source and drain electrode metal is adopted to contact with the doped nanowire channel, asymmetric Schottky barriers can be obtained, the Schottky barriers between the drain electrode metal and the doped nanowire channel can be initially adjusted through the pre-bias effect of drain electrode voltage, the polarity of the transistor can be changed by changing the positive and negative of the drain electrode voltage and adding grid electrode regulation, and the reconfigurable transistor without changing the carrier type is obtained.

Description

Asymmetric electrode reconfigurable transistor operated by source-drain voltage and debugging method
Technical Field
The invention relates to the technical field of microelectronics, in particular to an asymmetric electrode reconfigurable transistor operated by source-drain voltage and a debugging method, which can be used for an editable logic device. And more particularly to the use of asymmetric energy band contacts formed by asymmetric electrodes and doped nanowires to more easily achieve switching of the polarity of the transistor simply by changing the positive and negative voltages at the drain.
Background
Semiconductor crystal silicon Nanowire (Nanowire) is a core material of modern microelectronic technology due to its advantages of high carrier mobility, high efficiency, stability, reliable doping process and the like, and the inventor of the present application firstly proposes a planar solid-liquid-solid (IP SLS) growth mode: wherein, the low-melting metal nano-particles absorb the amorphous silicon precursor to grow the crystalline silicon nanowire structure. Meanwhile, the inventor of the present application has also proposed a method for preparing a multi-step guiding channel by using a positive photoresist process through circulation of anisotropic etching and isotropic shrink etching to grow a positionable planar nanowire array.
In today's post-molar times, reconfigurable Field Effect Transistors (RFETs) are receiving increasing attention in order to overcome the static characteristics in CMOS processes and reduce overall circuit area and power consumption. By means of the structural advantages, the polarity of carriers in a channel can be controlled through different voltage configurations, and the N-type state and the P-type state of the device can be switched. However, most of the existing reconfigurable transistors are of a dual-Gate or even tri-Gate structure, a polarity Gate (Program Gate) controls a schottky barrier between a source and a drain and a nanowire channel so as to Control the type of a carrier, a Control Gate (Control Gate) controls the on and off of the transistor, and various RFETs are derived on the basis, but the multi-Gate Control structure is complex to prepare and needs multiple potential controls in actual use, which is not favorable for the reduction of the size of a device and the integration of a circuit. Doping of a channel material and formation of a Schottky barrier between a source electrode and a channel are all important for RFET, but reports of a reconfigurable transistor can be realized only by controlling source and drain voltages and regulating and controlling a single gate by means of single carrier types do not exist at present.
Disclosure of Invention
The application provides an asymmetric electrode reconfigurable transistor operated by source-drain voltage, and under the control condition of a single grid, the polarity of the reconfigurable transistor can be regulated and controlled without changing the type of a carrier only by changing the positive and negative of the drain voltage in the asymmetric electrode.
The embodiment of the application provides a preparation method of an asymmetric electrode reconfigurable transistor operated by source-drain voltage, which is characterized by comprising the following steps:
1) Spin-coating a layer of photoresist on the substrate by a spin-coating method;
2) Transferring the mask channel pattern to the substrate by contact exposure and positive photoresist etching;
3) Forming a multi-step channel on the substrate by circulation of anisotropic etching and isotropic shrink etching by using the positive photoresist pattern formed in the step 2);
4) Defining a catalyst metal pattern by a negative photoresist process according to the multi-step channel formed in the step 3), and locally depositing a band-shaped catalyst metal layer in a direction vertical to the channel;
5) In a PECVD system and other systems, raising the temperature to be above the melting point of the catalytic metal, performing plasma treatment by using reducing gas to remove an oxide layer on the surface of the catalytic metal, and simultaneously separating the catalytic metal into metal nano-particles;
6) Reducing the temperature to below the melting point of the catalytic metal particles to enable the catalytic metal particles to be solid, and covering the whole sample surface with a doped amorphous semiconductor precursor film; then raising the temperature to be higher than the eutectic point of the catalytic metal and the amorphous layer, so that the catalytic metal particles are changed into liquid pellets again, the front end of the catalytic metal particles starts to absorb the amorphous semiconductor precursor film layer, and the rear end of the catalytic metal particles deposits crystalline doped nanowires;
7) Removing the amorphous semiconductor precursor film layer remained on the surface of the sample by hydrogen plasma, RIE or wet etching process, and passivating the surface by high-temperature thermal oxidation;
8) Defining a drain metal pattern by adopting a negative photoresist process, removing a surface oxide layer and depositing drain contact metal;
9) Defining a source metal pattern by adopting a negative photoresist process, removing a surface oxide layer and depositing source contact metal;
10 Depositing a gate dielectric layer on the surface of the sample;
11 Adopting negative photoresist process to define opening pattern in source-drain electrode region, and removing dielectric layer in said region to make subsequent electric contact;
12 Adopting a negative photoresist process to define a grid pattern, depositing a grid film, and carrying out vacuum low-temperature annealing to improve contact and eliminate interface defects after the whole device is prepared according to requirements.
The invention further defines the technical scheme as follows:
the nanowire grown in the step 6) is a doped nanowire, and the doped amorphous precursor film can be deposited by introducing doping gas to start luminance together while depositing the amorphous precursor film, so that a P-type or N-type nanowire grows, wherein the nanowire grown in the invention is an N-type nanowire, and silane SiH (SiH) 4 And phosphane PH 3 The ratio of (1) to (2) is 6;
further, in step 8), the deposited Drain contact metal (Drain) needs to form a large schottky barrier with the nanowire channel; if metal Pt is contacted with the silicon nanowire, a potential barrier larger than 1 eV is formed;
further, in step 8), the deposited Source contact metal (Source) needs to form a small schottky barrier with the nanowire channel, so as to obtain an ohmic or ohmic-like contact; such as metal Ti, al and silicon nanowires form a potential barrier around 0.1 eV, so that ohmic or ohmic-like contact is obtained.
Furthermore, the process in the above steps is not limited to photoresist, and may be high precision lithography or other electrical photoresist, and only needs to transfer the mask pattern to the substrate and withstand the cyclic etching and shrink etching processes to form a multi-step channel;
further, the substrate in the step 1) is made of crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, polyimide or poly-p-phthalic plastic;
further, a band-shaped catalytic metal layer is deposited In the direction vertical to the multi-step channel In the step 4), and the catalytic metal layer can be In, sn, bi or Ga metal and metal alloy thereof;
further, in step 6), the amorphous semiconductor precursor thin film layer is an amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or a-Ge/a-Si heterogeneous laminated structure, and the doping gas can be phosphine PH 3 Borane B 2 H 6 Arsine AsH 3 And the like;
further, in step 10), the gate dielectric is aluminum oxide, hafnium oxide, silicon nitride, silicon oxide, titanium oxide, lanthanum oxide, or the like;
further, in step 12), the gate thin film is Al, ni, ti/Au, pt/Au, niMn alloy or polysilicon, etc.
The invention also discloses an asymmetric electrode reconfigurable transistor operated by source-drain voltage, which comprises a substrate and is characterized in that doped nanowire arrays are distributed in a multi-step channel arranged on the substrate, drain contact metal and source contact metal are respectively precipitated at two ends of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, a gate dielectric layer is deposited on the surface of the substrate except drain contact metal and source contact metal areas at two ends, and a gate thin film layer is deposited on the gate dielectric layer.
The invention also discloses a regulation and control method of the asymmetric electrode reconfigurable transistor operated by source-drain voltage, which is suitable for the asymmetric electrode reconfigurable transistor and comprises the following regulation and control methods:
1) When positive bias is applied to the drain contact electrode, the metal Fermi level at the drain end moves downwards, and the Schottky barrier height of the contact energy band of the drain end and the silicon nanowire is reduced by the pre-bias effect;
when the applied gate voltage is positive bias, the silicon nanowire energy band moves downwards, the Schottky barrier height of the drain end and the doped silicon nanowire channel is increased, electrons in the N-type silicon nanowire cannot easily cross the Schottky barrier, and therefore the N-type silicon nanowire energy band is in a closed state;
when the applied grid voltage is negative bias voltage, the doped silicon nanowire energy band moves upwards, the Schottky barrier height of the drain end and the doped silicon nanowire channel is gradually reduced, and electrons in the N-type silicon nanowire can cross the Schottky barrier to reach the drain end and gradually turn on; a P-type transistor corresponding to a thermionic emission type;
2) When negative bias is applied to the drain contact electrode, the metal Fermi level at the drain end moves upwards, the Schottky barrier height of the contact energy band of the drain end and the silicon nanowire is increased by the pre-bias effect, and meanwhile, the thickness of the Schottky barrier is reduced in advance;
when the applied grid voltage is positive bias, the silicon nanowire energy band moves downwards, the thickness of a Schottky barrier between the drain end and the doped silicon nanowire channel is further reduced, and electrons in the N-type silicon nanowire can tunnel through the Schottky barrier to reach a Ti end so as to be in an open state;
when the applied grid voltage is negative bias voltage, the energy band of the doped silicon nanowire moves upwards, the height of a Schottky barrier between the drain end and the doped silicon nanowire channel is gradually reduced but is not enough to enable electrons to cross the Schottky barrier, and meanwhile, the electrons in the N-type silicon nanowire are difficult to tunnel due to the increase of the thickness of the Schottky barrier and are in a closed state; and thus corresponds to a tunneling type N-type transistor.
The invention also discloses an asymmetric electrode phase inverter integrated on a single or multiple nanowires, which comprises a substrate and is characterized in that doped nanowire arrays are distributed in a multi-step channel arranged on the substrate, drain contact metals Drain are respectively precipitated at two ends of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, source contact metals Source are precipitated at one side of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, gate dielectric layers are precipitated on the surface of the substrate except regions of the Drain contact metals and the Source contact metals at the two ends, and gate thin film layers are deposited on the gate dielectric layers;
a drain contact metal at one end and a middle source electrode form a first asymmetric electrode FET, a drain contact metal at the other end and the middle source electrode form a second asymmetric electrode FET, a drain of the first asymmetric electrode FET is applied with a constant positive bias, a drain of the second asymmetric electrode FET is applied with a constant negative bias, and the first asymmetric electrode and the second asymmetric electrode share the same grid as an input;
when the applied grid voltage is negative, the first asymmetric electrode FET hot electron emission type P-type transistor is switched on, the tunneling type N-type transistor of the second asymmetric electrode FET is switched off, and the obtained output is a constant positive bias voltage;
when the applied grid voltage is positive, the hot electron emission type P-type transistor of the first asymmetric electrode FET is turned off, the tunneling type N-type transistor of the second asymmetric electrode FET is turned on, and the obtained output is a constant negative bias voltage; thereby realizing the high-low switching of the output end.
Advantageous effects: the technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:
1) The invention adopts modern micromachining technology to prepare a multi-step channel, and utilizes methods such as IP-SLS and the like to grow a channel-guided doped crystalline nanowire array at low temperature in PECVD;
2) The self-positioning and self-orientation of the growth of the nano wire can be realized after a multi-step guide channel and a positioned catalytic metal area are formed by photoetching or electron beam direct writing and etching technology;
3) Asymmetric Schottky barriers can be obtained by contacting asymmetric source drain metal with the doped nanowire channels, the Schottky barriers between the drain metal and the doped nanowire channels can be initially adjusted through the pre-biasing effect of drain voltage, the polarity of the transistor can be changed by changing the positive and negative of the drain voltage and the grid regulation, and the reconfigurable transistor without changing the carrier type is obtained;
4) The reconfigurable transistor can be regulated and controlled only by three electrodes, namely an asymmetric source electrode, an asymmetric drain electrode and a grid electrode, does not need multiple potential controls, does not change the structure of the original device, is favorable for reducing the size of the device and integrating circuits, and is expected to be applied to logic device arrays and new-generation FPGAs.
Drawings
Fig. 1 is a flow chart illustrating a manufacturing process of an asymmetric electrode reconfigurable transistor operated by source-drain voltage in embodiment 1 of the present invention.
Fig. 2 is a schematic energy band diagram of the contact between the source-drain electrode and the doped nanowire channel when no source-drain voltage and no gate voltage are applied in embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of an energy band of a contact between a source drain electrode and a doped nanowire channel and a change thereof with a gate voltage Vg when a positive bias is applied to a drain in embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of an energy band of a contact between a source-drain electrode and a doped nanowire channel when a negative bias is applied to a drain electrode in embodiment 1 of the present invention, and a change of the energy band with a gate voltage Vg.
Fig. 5 is an SEM image of the source-drain electrode and nanowire channel contact in embodiment 1 of the present invention, and an SD current curve after annealing at 350 ℃ for 5min in vacuum of the device as a whole.
Fig. 6 is a graph showing transfer characteristics in the case where a positive bias voltage and a negative bias voltage are applied to the Drain (Drain) in example 1 of the present invention, respectively.
Fig. 7 is a schematic diagram of the overall structure of the asymmetric electrode reconfigurable transistor manufactured in embodiment 1 of the present invention.
Fig. 8 is a schematic diagram of a single-line integrated asymmetric-electrode inverter according to a further design in embodiment 1 of embodiment 2 of the present invention.
Detailed Description
The invention prepares a multi-step channel by photoetching and cyclic etching shrinkage and utilizes a nanowire growth method of planar solid-liquid-solid (IPSLS) to prepare a doped nanowire array which can be positioned and oriented, then prepares an asymmetric electrode, deposits a gate medium and prepares a gate. Under the control condition of a single grid, the polarity of the reconfigurable transistor can be regulated and controlled under the condition of not changing the type of a carrier only by changing the positive and negative of the voltage of the drain electrode in the asymmetric electrode. The invention can realize the most basic reconfigurable transistor through the potential control of three electrodes on the premise of not changing the original structure of the device, is beneficial to the reduction of the size of the device and the integration of a circuit, and is expected to be applied to a logic device array and a new generation FPGA.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
Example 1
The embodiment provides an asymmetric electrode reconfigurable transistor operated by source-drain voltage, and the preparation flow is as shown in fig. 1, and specifically includes the following steps:
1) Silicon chip, glass, aluminum foil, compound such as silicon nitride, silicon oxide, silicon oxynitride, polymer or other metal materials are used as a substrate, and a layer of photoresist is spin-coated on the substrate at the rotating speed of 4000 rpm;
2) Transferring a mask plate pattern onto a substrate by using a positive photoresist process through contact type ultraviolet exposure, performing anisotropic etching on the substrate by using gases such as SF6, CF4, C4F8 and the like through ICP (inductively coupled plasma) or RIE (reactive ion etching), performing isotropic shrink etching on the photoresist by using O2 to perform denudation on the photoresist, and removing the photoresist after multiple cycles, wherein a multi-step channel is formed in an original positive photoresist pattern area, as shown in a) in the figure 1;
3) Defining a pattern perpendicular to the channel direction by using the multi-step channel formed In the step 2) again through a photoresist process, developing, and locally depositing a belt-shaped catalytic metal layer such as In, sn, bi or Ga through an evaporation or sputtering process, as shown In a b) diagram In fig. 1, wherein the thickness of the In evaporated In the step is 6nm.
4) Raising the temperature to be above the melting point of the catalytic metal in PECVD, and introducing reducing gas plasma for treatment to convert the catalytic metal layer into separated metal nano-particles;
5) Reducing the temperature to below the melting point of the catalytic metal particles by using a PECVD system again to enable the catalytic metal particles to become solid, and covering the surface of the whole structure with a doped amorphous semiconductor precursor thin film layer through plasma deposition; then raising the temperature to be higher than the eutectic point of the catalytic metal and the amorphous thin film layer, so that the nano metal particles are re-melted, the doped amorphous precursor thin film layer is absorbed at the front end of the nano metal particles, and the crystalline doped nanowire is deposited at the rear end of the nano metal particles, as shown in a c) diagram in fig. 1;
the precursor source used in this step is silane SiH 4 And phosphane PH 3 Simultaneously, the brightness is started, the ratio is 6:0.5, and the diameter of the grown N-type nanowire is about 30-40nm;
6) The residual doped amorphous semiconductor precursor film layer is removed by etching processes such as hydrogen plasma, RIE dry etching or wet etching; the wet etching solution is an alkaline etching system such as potassium hydroxide (KOH), ammonia (NH 4 OH), tetramethylammonium hydroxide (TMAH), etc., and the RIE dry etching gas is a fluorine-containing gas such as carbon tetrafluoride (CF 4), tetracarbon octafluoride (C4F 8), etc. Then carrying out high-temperature passivation treatment;
in the step, carbon tetrafluoride (CF 4) in RIE is adopted to carry out dry etching to remove the doped amorphous film layer, and then annealing is carried out for 15min at 850 ℃ in a tube annealing furnace under the oxygen atmosphere, so that the diameter of the nanowire is further reduced, and a high-quality oxide layer is formed on the surface;
7) Defining a Drain region pattern by utilizing a negative photoresist lithography process or electron beam direct writing, then removing an oxide layer on the surface of the contact region nanowire by adopting solutions such as HF (hydrogen fluoride), BOE (biaxially oriented ethylene), and the like, and locally depositing a layer of Drain contact metal (Drain) such as Pt, au, pt/Au, and the like by an evaporation or sputtering process, as shown in a d) diagram in fig. 1, wherein the Drain contact metal (Drain) adopted in the step needs to form a large Schottky barrier with the nanowire channel, for example, the barrier larger than 1 eV is formed by the contact of metal Pt and the silicon nanowire; meanwhile, the surface oxide layer is also required to be removed by wet etching of a solution before the source contact metal is prepared, so that the Drain contact metal (Drain) is required to be resistant to acid etching. In this step we define the Drain region with EBL and use Pt/Au (7/50 nm) as the Drain contact electrode (Drain), where Pt and N-type nanowire channels form a large schottky barrier, as shown in fig. 2;
8) Defining a Source region pattern by utilizing a negative photoresist lithography process or electron beam direct writing, then removing an oxide layer on the surface of a contact region nanowire by adopting solutions such as HF, BOE and the like, and locally depositing a layer of Source contact metal (Source) such as Ni, al, ti/Au, ti/Al, pt/Au, pt/Al and the like by an evaporation or sputtering process, as shown in an e) diagram in FIG. 1, wherein the Source contact metal (Source) adopted in the step needs to form a small Schottky barrier with the nanowire channel, for example, the metal Ti, al and the silicon nanowire form a barrier of about 0.1 eV, so as to obtain ohmic or ohmic-like contact, and in the step, the Source region is defined by utilizing EBL, and Ti/Al (7/50 nm) is adopted as the Source contact metal (Source), wherein Ti and an N-type nanowire channel form a small Schottky barrier, as shown in FIG. 2;
9) A Gate dielectric layer such as aluminum oxide, hafnium oxide, silicon nitride, silicon oxide, titanium oxide, lanthanum oxide, etc. is deposited and covered on the whole sample by ALD or PECVD, a Gate region pattern is defined by using a photoresist process or electron beam direct writing, and a Gate thin film (Gate) such as Al, ni, ti/Au, pt/Au, niMn alloy or polysilicon, etc. is locally deposited by an evaporation or sputtering process, and the structure is shown in fig. 7, wherein a is a top view of the whole structure, and b is a perspective view of the whole structure. The gate dielectric adopted in the step is 25nm aluminum oxide Al deposited at 300 ℃ by ALD 2 O 3 And defining a grid region by adopting EBL (electron beam lithography), depositing 60nm Al by utilizing magnetron sputtering, and finally annealing the whole device in a vacuum tube type annealing furnace at 350 ℃ for 5min for improving contact and eliminating interface defects.
Fig. 2 is a schematic diagram of an energy band of a channel contact between a source-drain metal and a doped silicon nanowire when no source-drain voltage and gate voltage are applied, where in this embodiment 1, a larger schottky barrier is formed under Pt and N-type silicon nanowires, and a smaller schottky barrier is formed between Ti and N-type silicon nanowires, which are in ohmic or ohmic-like contact;
fig. 3 shows that when a positive bias is applied to the Drain contact electrode (Drain), the metal fermi level at the Pt terminal moves downward, and the pre-bias effect reduces the schottky barrier height of the Pt terminal and the silicon nanowire contact energy band, as shown in the left diagram of fig. 3.
When the applied gate voltage is positive bias, the silicon nanowire energy band moves downwards, the Schottky barrier height of the Pt end and the doped silicon nanowire channel is further increased, and electrons in the N-type silicon nanowire cannot easily cross the Schottky barrier, so that the N-type silicon nanowire channel is in a closed state;
when the applied grid voltage is negative bias voltage, the doped silicon nanowire energy band moves upwards, the height of a Schottky barrier between the Pt end and the doped silicon nanowire channel is gradually reduced, and for electrons in the N-type silicon nanowire, the electrons can cross the Schottky barrier to reach the Pt end, so that the N-type silicon nanowire energy band is gradually in an opening state; fig. 3 thus corresponds to a P-type transistor of the hot electron emission type.
Fig. 4 shows that when a negative bias is applied to the Drain contact electrode (Drain), the metal fermi level at the Pt terminal is shifted upward, and the pre-bias effect increases the schottky barrier height of the Pt terminal and the silicon nanowire contact band, but at the same time the schottky barrier thickness has been reduced in advance, as shown in the left diagram of fig. 4.
When the applied gate voltage is positive bias voltage, the silicon nanowire energy band moves downwards, the thickness of a Schottky barrier between the Pt end and the doped silicon nanowire channel is further reduced, and electrons in the N-type silicon nanowire can tunnel through the Schottky barrier to the Ti end, so that the N-type silicon nanowire is in an open state;
when the applied gate voltage is negative bias voltage, the doped silicon nanowire energy band moves upwards, the Schottky barrier height of the Pt end and the doped silicon nanowire channel is gradually reduced but is not enough to enable electrons to cross the Schottky barrier, and meanwhile, the electrons in the N-type silicon nanowire are difficult to tunnel due to the increase of the Schottky barrier thickness, so that the N-type silicon nanowire is in an off state; fig. 4 thus corresponds to a tunneling type N-type transistor;
FIG. 5 is SEM image of an asymmetric electrode prepared by EBL in the embodiment, about 3 chords, wherein the length of the nanowire channel is 465nm, and the right image is SD current curve of the whole device after annealing at 350 ℃ for 5min in vacuum, and it can be seen from the curve that the asymmetric electrode can obtain asymmetric contact shown in an energy band diagram, vds in the graph is applied on a drain contact metal Pt/Au, and a source contact metal is grounded;
fig. 6 is a transfer characteristic curve of the asymmetric-electrode reconfigurable transistor operated by source-drain voltage in this embodiment 1, the left graph of fig. 6 corresponds to the analysis of fig. 3, the right graph of fig. 6 corresponds to the analysis of fig. 4, since the transistor is a tunneling N-type transistor when Vds applies negative voltage, a smaller SS is obtained, and the minimum SS is 79mV/dec. It should be noted that, since the schottky barrier height between the Pt terminal and the doped nanowire is reduced by the pre-bias effect when the drain metal is applied with the forward bias voltage, so as to form the P-type transistor of the thermionic emission type, if the applied forward bias voltage is small and the pre-bias effect is not sufficient, tunneling may easily occur under a certain forward gate voltage.
The invention can operate and change the polarity of the transistor without adopting multi-gate control by changing the positive and negative voltages applied to the drain electrode, thereby realizing a simpler reconfigurable transistor.
Example 2
The embodiment provides a schematic diagram of an asymmetric electrode inverter integrated by multiple lines. The structure is shown in fig. 8, and comprises:
the doped nanowire array is arranged in a multi-step channel on the substrate, doped nanowire arrays are arranged at two ends of the doped nanowire array and are perpendicular to the doped nanowire direction, drain contact metals are respectively precipitated in the doped nanowire array, source contact metals are precipitated in the middle of the doped nanowire array and are perpendicular to one side of the doped nanowire direction, grid dielectric layers are deposited on the surface of the substrate except regions, at two ends, of the drain contact metals and the source contact metals, and grid thin film layers are deposited on the grid dielectric layers.
The top Pt/Au electrode is applied with a constant positive bias, the bottom Pt/Au electrode is applied with a constant negative bias, the grid is used as input, and the Ti/Al electrode is used as output.
The upper half part is an asymmetric electrode FET consisting of a top Pt/Au electrode (Drain 1) and a middle Ti/Al electrode (Source), the lower half part is an asymmetric electrode FET consisting of a bottom Pt/Au electrode (Drain 2) and a middle Ti/Al electrode (Source), and the upper part and the lower part share the same grid as input.
When the applied grid voltage is negative, the top half of the thermal electron emission type P-type transistor is turned on, the bottom half of the tunneling type N-type transistor is turned off, and the obtained output is a constant positive bias voltage;
when the applied grid voltage is positive, the top half of the hot electron emission type P-type transistor is closed, the bottom half of the tunneling type N-type transistor is opened, and the obtained output is constant negative bias voltage; thereby realizing the high-low switching of the output end;
it should be noted that the asymmetric electrode has similar effect on the P-type nanowire, and it will be apparent to those skilled in the art that several modifications can be made without departing from the principle of the present invention, and these modifications should be construed as the protection scope of the present invention.

Claims (8)

1. A preparation method of an asymmetric electrode reconfigurable transistor operated by source-drain voltage is characterized by comprising the following steps:
1) Spin-coating a layer of photoresist on the substrate by a spin-coating method;
2) Transferring the mask channel pattern to the substrate by contact exposure and positive photoresist etching;
3) Forming a multi-step channel on the substrate by circulation of anisotropic etching and isotropic shrink etching by using the positive photoresist pattern formed in the step 2);
4) Defining a catalyst metal pattern by a negative photoresist process according to the multi-step channel formed in the step 3), and locally depositing a band-shaped catalyst metal layer in a direction vertical to the channel;
5) In a PECVD system and other systems, raising the temperature to be above the melting point of the catalytic metal, performing plasma treatment by using reducing gas to remove an oxide layer on the surface of the catalytic metal, and simultaneously separating the catalytic metal into metal nano-particles;
6) Reducing the temperature to be below the melting point of the catalytic metal particles to change the catalytic metal particles into a solid state, and covering the whole sample surface with a doped amorphous semiconductor precursor film; then raising the temperature to be higher than the eutectic point of the catalytic metal and the amorphous layer, so that the catalytic metal particles are changed into liquid pellets again, the front end of the catalytic metal particles starts to absorb the amorphous semiconductor precursor film layer, and the rear end of the catalytic metal particles deposits crystalline doped nanowires;
7) Removing the amorphous semiconductor precursor film layer remained on the surface of the sample by hydrogen plasma, RIE or wet etching process, and passivating the surface by high-temperature thermal oxidation;
8) Defining a drain metal pattern by adopting a negative photoresist process, removing a surface oxide layer and depositing drain contact metal;
9) Defining a source electrode metal pattern by adopting a negative photoresist process, removing a surface oxidation layer and depositing source electrode contact metal;
10 Depositing a grid dielectric layer on the surface of the sample;
11 Adopting negative photoresist process to define opening pattern in source-drain electrode region, and removing dielectric layer in said region to make subsequent electric contact;
12 Adopting a negative photoresist process to define a grid pattern, depositing a grid film, and carrying out vacuum low-temperature annealing to improve contact and eliminate interface defects after the whole device is prepared according to requirements.
2. The method for manufacturing an asymmetric-electrode reconfigurable transistor operated by source-drain voltages according to claim 1, characterized in that:
in the step 6), the doped nanowire is a P-type or N-type nanowire, and when the doped nanowire is an N-type nanowire, silane SiH is used 4 And phospholane PH 3 The ratio of (2) to (3) is 6.
3. The method for manufacturing an asymmetric-electrode reconfigurable transistor by source-drain voltage operation according to claim 2, characterized in that: in step 8), the deposited drain contact metal forms a schottky barrier with the nanowire channel of more than 1 eV, and the deposited source contact metal needs to form a schottky barrier with the nanowire channel of 0.1 eV in order to obtain an ohmic or ohmic-like contact.
4. The method for manufacturing an asymmetric-electrode reconfigurable transistor by source-drain voltage operation according to claim 1, characterized in that: the substrate in the step 1) is made of crystalline silicon, glass, aluminum foil, silicon nitride, silicon oxide, silicon carbide, sapphire, polyimide or poly-p-phthalic plastic.
5. The method for manufacturing an asymmetric-electrode reconfigurable transistor by source-drain voltage operation according to claim 1, characterized in that: and 4) depositing a band-shaped catalytic metal layer In the direction vertical to the multi-step channel, wherein the catalytic metal layer is In, sn, bi or Ga metal and metal alloy thereof.
6. The asymmetric electrode reconfigurable transistor operated by source-drain voltage comprises a substrate and is characterized in that doped nanowire arrays are distributed in a multi-step channel arranged on the substrate, drain contact metals and source contact metals are respectively precipitated at two ends of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, a gate dielectric layer is deposited on the surface of the substrate except drain contact metals and source contact metal areas at the two ends, and a gate thin film layer is deposited on the gate dielectric layer.
7. A regulation and control method of an asymmetric electrode reconfigurable transistor operated by source-drain voltage is suitable for the asymmetric electrode reconfigurable transistor of claim 6, and is characterized by comprising the following regulation and control methods:
1) When positive bias is applied to the drain contact electrode, the metal Fermi level at the drain end moves downwards, and the Schottky barrier height of the contact energy band of the drain end and the silicon nanowire is reduced by the pre-bias effect;
when the applied gate voltage is positive bias, the silicon nanowire energy band moves downwards, the Schottky barrier height of the drain end and the doped silicon nanowire channel is increased, electrons in the N-type silicon nanowire cannot easily cross the Schottky barrier, and therefore the N-type silicon nanowire energy band is in a closed state;
when the applied grid voltage is negative bias voltage, the doped silicon nanowire energy band moves upwards, the Schottky barrier height of the drain end and the doped silicon nanowire channel is gradually reduced, and electrons in the N-type silicon nanowire can cross the Schottky barrier to reach the drain end and gradually turn on; a P-type transistor corresponding to a hot electron emission type;
2) When negative bias is applied to the drain contact electrode, the metal Fermi level at the drain end moves upwards, the Schottky barrier height of the contact energy band of the drain end and the silicon nanowire is increased by the pre-bias effect, and meanwhile, the thickness of the Schottky barrier is reduced in advance;
when the applied gate voltage is positive bias, the silicon nanowire energy band moves downwards, the thickness of a Schottky barrier between the drain end and the doped silicon nanowire channel is further reduced, and electrons in the N-type silicon nanowire can tunnel through the Schottky barrier to reach the Ti end, so that the N-type silicon nanowire energy band is in an open state;
when the applied grid voltage is negative bias voltage, the energy band of the doped silicon nanowire moves upwards, the height of a Schottky barrier between the drain end and the doped silicon nanowire channel is gradually reduced but is not enough to enable electrons to cross the Schottky barrier, and meanwhile, the electrons in the N-type silicon nanowire are difficult to tunnel due to the increase of the thickness of the Schottky barrier and are in a closed state; and thus corresponds to a tunneling type N-type transistor.
8. The asymmetric electrode phase inverter integrated on one or more nanowires comprises a substrate and is characterized in that doped nanowire arrays are distributed in a multi-step channel arranged on the substrate, drain contact metals Drain are respectively precipitated at two ends of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, source contact metals Source are precipitated at one side of the middle of the doped nanowire arrays and in a direction perpendicular to the doped nanowire arrays, gate dielectric layers are precipitated on the surface of the substrate except regions of the Drain contact metals and the Source contact metals at the two ends, and gate thin film layers are deposited on the gate dielectric layers;
a drain contact metal at one end of the substrate and a middle source electrode form a first asymmetric electrode FET, a drain contact metal at the other end of the substrate and the middle source electrode form a second asymmetric electrode FET, a drain electrode of the first asymmetric electrode FET is applied with a constant positive bias, a drain electrode of the second asymmetric electrode FET is applied with a constant negative bias, and the first asymmetric electrode and the second asymmetric electrode share the same grid as an input;
when the applied grid voltage is negative, the first asymmetric electrode FET hot electron emission type P-type transistor is turned on, the second asymmetric electrode FET tunneling type N-type transistor is turned off, and the obtained output is a constant positive bias voltage;
when the applied grid voltage is positive, the hot electron emission type P-type transistor of the first asymmetric electrode FET is turned off, the tunneling type N-type transistor of the second asymmetric electrode FET is turned on, and the obtained output is a constant negative bias voltage; therefore, the high-low switching of the output end is realized.
CN202211067410.9A 2022-09-01 2022-09-01 Asymmetric electrode reconfigurable transistor operated by source-drain voltage and debugging method Pending CN115377201A (en)

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