CN116206981B - Method for preparing full-two-dimensional short-channel field effect transistor in large scale - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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Abstract
The invention discloses a method for preparing a full two-dimensional short channel field effect transistor in a large scale. According to the invention, the single-layer graphene is adopted as the source electrode and the drain electrode which are in contact with the semiconductor material, so that the Schottky barrier is effectively inhibited, and the power consumption of the field effect transistor is reduced; a single-layer two-dimensional semiconductor layer is adopted as a channel material, so that the influence caused by short channel effect is reduced; carrying out focused helium ion beam direct writing etching on the single-layer graphene by adopting a helium ion microscope, so that a nanoscale channel can be stably obtained; the width of the channel defined by the invention is the width of a single-layer two-dimensional semiconductor layer actually participating in work in the field effect transistor, so that the stability of the performance of the field effect transistor is improved; the van der Waals heterojunction is obtained by dry transfer, and the local dielectric layer is used as a protective layer to encapsulate the channel material, so that the quality and durability of the field effect transistor are effectively improved; the local dielectric layer and the global dielectric layer form a double-grid structure which is modulated up and down, so that the performance of the field effect transistor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a method for preparing an all-two-dimensional short-channel field effect transistor in a large scale.
Background
With the continuous development of integrated circuit technology, the requirements for the performance of field effect transistors are gradually increased. For transistor devices with gate lengths scaled down to submicron and even sub-10 nanometers, an unavoidable problem is short channel effects caused by their small size, which results in overall degradation of device performance, such as reduced threshold voltage with reduced channel length, reduced subthreshold slope of device transfer characteristics with increased source-drain voltage, and so forth. The short channel effect can also cause the carrier velocity saturation of the device, so that the saturation current of the drain terminal is greatly reduced; the size of the device enters the deep submicron groove length range, the electric field intensity in the device is enhanced along with the reduction of the size of the device, particularly, a strong electric field exists near a drain junction, and carriers acquire higher energy in the strong electric field and become hot carriers. The hot carrier affects the device performance in two aspects, 1) it crosses the Si-SiO2 barrier and injects into the oxide layer, continuously accumulates, changes the threshold voltage, affects the device lifetime; 2) Electron hole pairs are generated in the depletion region near the drain by collision with the crystal lattice, and an additional leakage current is formed for the electrons generated by collision of the N-type metal oxide semiconductor transistor, and the holes are collected by the substrate to form a substrate current, so that the total current is the sum of the saturated leakage current and the substrate current. The larger the substrate current, the more collisions that occur in the channel, and the more severe the corresponding hot carrier effect.
For the above short channel effect, the main countermeasures currently in main use are as follows: firstly, a fin field effect transistor (FinFET), a channel region is designed into a 3D fin type slice, a grid electrode adopts a three-side surrounding grid structure, and control of a channel can be effectively inhibited by utilizing side grids on two sides to enhance, but compared with a planar device, the FinFET has a much more complicated preparation process and is not suitable for large-scale mass production; secondly, by introducing a very thin oxide layer between a silicon channel layer and a substrate layer in a silicon-on-insulator (SOI) technology, leakage current between a source electrode and a drain electrode can be effectively inhibited under the condition of full depletion of the channel layer, but the SOI silicon wafer has higher preparation cost and relatively complex process; finally, a metal source-drain Schottky barrier transistor (SB MOSFET) uses tunneling current of a Schottky barrier between a metal source and a semiconductor channel as working current of the transistor, so that sensitivity to short channel effect is reduced.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a method for preparing a full-two-dimensional short-channel field effect transistor in a large scale, a short channel is obtained by focusing helium ion beam direct writing mode, a full-two-dimensional van der Waals heterojunction is obtained by adopting a dry transfer process, and finally a metal electrode is evaporated through a standard electron beam exposure process to obtain the required field effect transistor.
The method for preparing the full two-dimensional short channel field effect transistor in a large scale comprises the following steps:
1) Obtaining one or more pieces of single-layer graphene, transferring the one or more pieces of single-layer graphene onto a global dielectric layer formed on the surface of the first substrate, wherein the global dielectric layer covers the surface of the first substrate, and the single-layer graphene covers part of the surface of the global dielectric layer;
2) Performing direct-write line scanning etching on each single-layer graphene by utilizing a focused helium ion beam, so that a nano seam is formed on each single-layer graphene, the nano seam penetrates through the upper surface and the lower surface of the single-layer graphene, the nano seam formed in the single-layer graphene is used as a channel, the width of the nano seam is the width of the channel, is a direct physical quantity, and can be represented by an atomic force microscope or a scanning electron microscope;
3) Obtaining a single-layer two-dimensional semiconductor layer, and transferring the two-dimensional semiconductor layer onto a second substrate by adopting a 2H phase transition metal chalcogenide compound; obtaining a local dielectric layer, and transferring the local dielectric layer onto a third substrate;
4) A dry transfer process is adopted, a local dielectric layer is covered on a corresponding two-dimensional semiconductor layer, the two-dimensional semiconductor layer covered with the local dielectric layer is transferred to a corresponding single-layer graphene etched with a channel at fixed points, the two-dimensional semiconductor layer covers the channel, and at the moment, the local dielectric layer, the two-dimensional semiconductor layer and the single-layer graphene are used as Van der Waals materials to form a Van der Waals heterostructure, and the three are combined through Van der Waals force, so that the combination among the three is more compact and stable; in the dry transfer process, the two-dimensional semiconductor layer is filled into the channel, the part of the two-dimensional semiconductor layer filled into the channel is used as a channel material, the area, which is in contact with the two sides of the two-dimensional semiconductor layer, of the upper surface of the single-layer graphene is used as a source electrode and a drain electrode, and compared with the metal electrode, the single-layer graphene has better electrical contact with the two-dimensional semiconductor, so that the power consumption of the field effect transistor is reduced, and the short channel effect of the single-layer graphene can be reduced;
5) Spin-coating photoresist, covering the surface of the local dielectric layer, the exposed surface of the single-layer graphene and the exposed surface of the global dielectric layer, forming a pattern of a contact electrode on a source electrode and a drain electrode by using an electron beam exposure machine, forming a pattern of a top gate electrode on the local dielectric layer, then performing development and electron beam coating, evaporating a metal electrode, respectively forming the contact electrode on the source electrode and the drain electrode and forming the top gate on the local dielectric layer, and finally removing the photoresist to complete the preparation of the field effect transistor.
In the step 1), one or more single-layer graphenes are obtained by mechanically stripping massive graphenes or directly depositing and growing, and the thickness of the graphenes is determined by contrast ratio under an optical microscope or an atomic force microscope; the global dielectric layer adopts SiO 2 The thickness is 285-300 nm; the first substrate is Si. SiO (SiO) 2 And Si has good interface characteristics, and Si has very high hole mobility, so that the performance requirement of the transistor is met.
In the step 2), the ion dose of the focused helium ion beam is 0.02-0.05 pC/nm, the larger the ion dose is, the larger the width of the nano-slit is, and the too small ion dose can cause the etching of the lower surface of the impermeable monolayer graphene; the width of the channel is 3-5 nm.
In step 3), a single-layered two-dimensional semiconductor layer, such as WSe, is obtained by mechanical lift-off or direct growth 2 、WS 2 Or MoS 2 Etc.; obtaining a local dielectric layer by a mechanical stripping or direct growth method, wherein the thickness of the local dielectric layer is 10-20 nm; the local dielectric layer adopts a two-dimensional van der Waals dielectric material, such as hexagonal boron nitride (hBN); si is used for the second substrate and the third substrate.
In step 5), the contact electrode and the top gate are made of Ti/Au or Cr/Au.
The invention has the advantages that:
according to the invention, the single-layer graphene is adopted as the source electrode and the drain electrode which are in contact with the semiconductor material, so that the Schottky barrier between the traditional metal electrode and the semiconductor is effectively inhibited, and the power consumption of the field effect transistor is reduced; the single-layer two-dimensional semiconductor layer is adopted as a channel material, so that the influence caused by short channel effect is effectively reduced; the helium ion microscope is adopted to carry out focused helium ion beam direct writing etching on the single-layer graphene, so that the pollution of photoresist to the surface of the material is avoided, the operation difficulty is reduced, and a channel with a nanometer scale (5 nm) can be stably obtained; different from the widely applied concept of the equivalent gate length of gate diffusion, the width of the channel defined by the invention is the width of a single-layer two-dimensional semiconductor layer actually participating in work in the field effect transistor, so that the stability of the performance of the field effect transistor is improved; the Van der Waals heterojunction obtained by dry transfer is utilized, and the local dielectric layer is used as a protective layer to encapsulate the channel material, so that the quality and durability of the field effect transistor are effectively improved; the local dielectric layer and the global dielectric layer form a double-grid structure which is modulated up and down, so that the performance of the field effect transistor is improved.
Drawings
FIG. 1 is a cross-sectional view of a field effect transistor according to one embodiment of the present invention for mass production of an all-two-dimensional short channel field effect transistor;
fig. 2 is an electron microscope image of a channel obtained by an embodiment of the large-scale preparation of the full two-dimensional short channel field effect transistor according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in conjunction with the accompanying drawings.
As shown in fig. 1, the method for preparing the full two-dimensional short channel field effect transistor in scale in this embodiment includes the following steps:
1) 290nm thick SiO 2 Completely cover the surface of Si with 290nm thick SiO 2 As the global dielectric layer 2, si was used as the first substrate 1, and a plurality of single-layer graphene 3 was obtained by mechanically peeling bulk graphene, and the plurality of single-layer graphene was transferred to SiO 290nm thick 2 Forming a single-layer graphene array, covering the surface of a part of the global dielectric layer, and singly and adjacently forming two single-layer graphitesThe alkene spacing is only required to satisfy the requirement of reserving the position of the electrode of the full two-dimensional short channel field effect transistor, and in the embodiment, the spacing is 500 mu m;
2) Carrying out direct writing line scanning etching on each single-layer graphene 3 by utilizing a focused helium ion beam with the ion dose of 0.03pC/nm, so that a nano slit with the width of 5nm is formed on each single-layer graphene, penetrates through the upper surface and the lower surface of the single-layer graphene, and takes the nano slit formed in the single-layer graphene as a channel 4, wherein the width of the nano slit is the width of the channel, is a direct physical quantity, and can be characterized by an atomic force microscope or a scanning electron microscope;
3) Obtaining a single-layer two-dimensional semiconductor layer 5 by mechanical stripping method, wherein the two-dimensional semiconductor layer adopts 2H phase transition metal chalcogenide WSe 2 Transferring the two-dimensional semiconductor layer onto a second substrate of Si material; further, hexagonal boron nitride hBN having a thickness of 15nm was obtained as the local dielectric layer 6 by mechanical lift-off, and the local dielectric layer was transferred onto the third substrate of Si material;
4) A dry transfer process is adopted, a local dielectric layer 6 is covered on a corresponding two-dimensional semiconductor layer 5, then the two-dimensional semiconductor layer covered with the local dielectric layer is transferred to a corresponding single-layer graphene 3 etched with a channel at fixed points, the two-dimensional semiconductor layer covers the channel 4, at the moment, the local dielectric layer, the two-dimensional semiconductor layer and the single-layer graphene are used as Van der Waals materials to form a Van der Waals heterostructure, and the three are combined through Van der Waals force to enable the combination of the three to be more compact and stable; in the dry transfer process, the two-dimensional semiconductor layer is filled into the channel, the part of the two-dimensional semiconductor layer filled into the channel is used as a channel material, the area, which is in contact with the two sides of the two-dimensional semiconductor layer, of the upper surface of the single-layer graphene is used as a source electrode and a drain electrode, and compared with the metal electrode, the single-layer graphene has better electrical contact with the two-dimensional semiconductor, so that the power consumption of the field effect transistor is reduced, and the short channel effect of the single-layer graphene can be reduced;
5) Spin-coating photoresist, covering the surface of the local dielectric layer, the exposed surface of the single-layer graphene and the exposed surface of the global dielectric layer, forming a contact electrode pattern on the source and drain electrodes by using an electron beam exposure machine, forming a top gate electrode pattern on the local dielectric layer, then performing development and electron beam coating, evaporating metal electrodes, respectively forming a Ti/Au contact electrode 7 on the source and drain electrodes and a Ti/Au top gate 8 on the local dielectric layer, and finally removing the photoresist to complete the preparation of the field effect transistor.
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (8)
1. A method for large scale fabrication of an all-two-dimensional short channel field effect transistor, the method comprising the steps of:
1) Obtaining one or more pieces of single-layer graphene, transferring the one or more pieces of single-layer graphene onto a global dielectric layer formed on the surface of the first substrate, wherein the global dielectric layer covers the surface of the first substrate, and the single-layer graphene covers part of the surface of the global dielectric layer;
2) Performing direct-write line scanning etching on each single-layer graphene by utilizing a focused helium ion beam, so that a nano seam is formed on each single-layer graphene, the nano seam penetrates through the upper surface and the lower surface of the single-layer graphene, the nano seam formed in the single-layer graphene is used as a channel, the width of the nano seam is the width of the channel, is a direct physical quantity, and can be represented by an atomic force microscope or a scanning electron microscope;
3) Obtaining a single-layer two-dimensional semiconductor layer, and transferring the two-dimensional semiconductor layer onto a second substrate by adopting a 2H phase transition metal chalcogenide compound; obtaining a local dielectric layer, and transferring the local dielectric layer onto a third substrate;
4) A dry transfer process is adopted, a local dielectric layer is covered on a corresponding two-dimensional semiconductor layer, the two-dimensional semiconductor layer covered with the local dielectric layer is transferred to a corresponding single-layer graphene etched with a channel at fixed points, the two-dimensional semiconductor layer covers the channel, and at the moment, the local dielectric layer, the two-dimensional semiconductor layer and the single-layer graphene are used as Van der Waals materials to form a Van der Waals heterostructure, and the three are combined through Van der Waals force, so that the combination among the three is more compact and stable; in the dry transfer process, the two-dimensional semiconductor layer is filled into the channel, the part of the two-dimensional semiconductor layer filled into the channel is used as a channel material, the area, which is in contact with the two sides of the two-dimensional semiconductor layer, of the upper surface of the single-layer graphene is used as a source electrode and a drain electrode, and the single-layer graphene is well in electrical contact with the two-dimensional semiconductor, so that the power consumption of the field effect transistor is reduced, and the short channel effect of the single-layer graphene can be reduced;
5) Spin-coating photoresist, covering the surface of the local dielectric layer, the exposed surface of the single-layer graphene and the exposed surface of the global dielectric layer, forming a pattern of a contact electrode on a source electrode and a drain electrode by using an electron beam exposure machine, forming a pattern of a top gate electrode on the local dielectric layer, then performing development and electron beam coating, evaporating a metal electrode, respectively forming the contact electrode on the source electrode and the drain electrode and forming the top gate on the local dielectric layer, and finally removing the photoresist to complete the preparation of the field effect transistor.
2. The method according to claim 1, wherein in step 1), one or more single-layer graphene sheets are obtained by mechanically exfoliating bulk graphene or by direct deposition growth.
3. The method of claim 1, wherein in step 1), the global dielectric layer is formed of SiO 2 The thickness is 285-300 nm; the first substrate is Si.
4. The method of claim 1, wherein in step 2), the ion dose of the focused helium ion beam is 0.02-0.05 pc/nm.
5. The method of claim 1, wherein in step 2), the width of the channel is 3-5 nm.
6. The method according to claim 1, wherein in step 3), a single-layer two-dimensional semiconductor layer is obtained by a mechanical lift-off method or a direct growth method.
7. The method according to claim 1, wherein in step 3), the local dielectric layer is obtained by mechanical lift-off or direct growth, and the thickness of the local dielectric layer is 10-20 nm.
8. The method of claim 1, wherein in step 5), the material of the contact electrode and the top gate is Ti/Au or Cr/Au.
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| WO2019143664A1 (en) * | 2018-01-19 | 2019-07-25 | Northwestern University | Self-aligned short-channel electronic devices and fabrication methods of same |
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