CN115376930A - 一种半导体封装方法 - Google Patents

一种半导体封装方法 Download PDF

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Publication number
CN115376930A
CN115376930A CN202110557690.0A CN202110557690A CN115376930A CN 115376930 A CN115376930 A CN 115376930A CN 202110557690 A CN202110557690 A CN 202110557690A CN 115376930 A CN115376930 A CN 115376930A
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chip
carrier plate
semiconductor packaging
packaging method
packaged
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冯建青
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Hitech Semiconductor Wuxi Co Ltd
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Hitech Semiconductor Wuxi Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明提供本发明提供一种半导体封装方法,用于对半导体进行快速封装;包括一载板和一芯片;所述载板上表面形成凹陷的腔部;所述芯片上设有多个焊垫;所述芯片设有焊垫的一面设置有粘着层,将芯片粘合在所述接班的腔部;包括以下步骤:S1:待封装产品进行等离子体清洗处理;S2:将电镀金属层及至少一个待封装的芯片贴装于载板上,形成包封层;S3:剥离所述载板,露出所述芯片的一面;S4:再进行等离子体清洗处理;S5:载板下表面形成与所述电镀金属层连接的多个节距大于所述多个焊垫节距的金属凸点;本发明的有益效果:提高封装效率,节约成本。

Description

一种半导体封装方法
技术领域
本发明主要涉及半导体封装技术领域,尤其涉及一种半导体封装方法。
背景技术
半导体封装是指将通过测试的晶圆按照产品型号及功能需求加工得到独立芯片的过程。封装过程为:来自晶圆前道工艺的晶圆通过划片工艺后被切割为小的晶片(Die),然后将切割好的晶片用胶水贴装到相应的基板(引线框架)架的小岛上,再利用超细的金属(金锡铜铝)导线或者导电性树脂将晶片的接合焊盘(Bond Pad)连接到基板的相应引脚(Lead),并构成所要求的电路;然后再对独立的晶片用塑料外壳加以封装保护,塑封之后还要进行一系列操作,封装完成后进行成品测试,通常经过入检Incoming、测试Test和包装Packing等工序,最后入库出货。
发明内容
针对现有技术的上述缺陷,本发明提供一种半导体封装方法,用于对半导体进行快速封装。
一种半导体封装方法,包括一载板和一芯片;
所述载板上表面形成凹陷的腔部;所述芯片上设有多个焊垫;所述芯片设有焊垫的一面设置有粘着层,将芯片粘合在所述接班的腔部;
包括以下步骤:
S1:待封装产品进行等离子体清洗处理;
S2:将电镀金属层及至少一个待封装的芯片贴装于载板上,形成包封层;
S3:剥离所述载板,露出所述芯片的一面;
S4:再进行等离子体清洗处理;
S5:载板下表面形成与所述电镀金属层连接的多个节距大于所述多个焊垫节距的金属凸点。
优选的,所述电极包括靠近所述载板的第一表面及与所述第一表面相对的第二表面。
优选的,所述包封层覆盖在所述载板上。
优选的,S1中所述向等离子体清洗处理空间供给的处理气体中包含氧气,所述氧气的体积占比至少为70%。
优选的,所述电镀金属层的材质为抗氧化性金属。
优选的,S1中,在所述至少一个待封装芯片的正面形成保护层。
本发明的有益效果:提高封装效率,节约成本。
具体实施方式
下面对本实用进行详细描述,本部分的描述仅是示范性和解释性,不应对本发明的保护范围有任何的限制作用。
一种半导体封装方法,包括一载板和一芯片;
所述载板上表面形成凹陷的腔部;所述芯片上设有多个焊垫;所述芯片设有焊垫的一面设置有粘着层,将芯片粘合在所述接班的腔部;
包括以下步骤:
S1:待封装产品进行等离子体清洗处理;
S2:将电镀金属层及至少一个待封装的芯片贴装于载板上,形成包封层;
S3:剥离所述载板,露出所述芯片的一面;
S4:再进行等离子体清洗处理;
S5:载板下表面形成与所述电镀金属层连接的多个节距大于所述多个焊垫节距的金属凸点。
本实施例中优选的,所述电极包括靠近所述载板的第一表面及与所述第一表面相对的第二表面。
本实施例中优选的,所述包封层覆盖在所述载板上。
本实施例中优选的,S1中所述向等离子体清洗处理空间供给的处理气体中包含氧气,所述氧气的体积占比至少为70%。
本实施例中优选的,所述电镀金属层的材质为抗氧化性金属。
本实施例中优选的,S1中,在所述至少一个待封装芯片的正面形成保护层。
需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”、“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。
以上所述的本发明实施方式,并不构成对本发明保护范围的限定。任何在本发明的精神和原则之内所作的修改、等同替换和改进等,均应包含在本发明的权利要求保护范围之内。

Claims (6)

1.一种半导体封装方法,包括一载板和一芯片;
其特征在于,所述载板上表面形成凹陷的腔部;所述芯片上设有多个焊垫;所述芯片设有焊垫的一面设置有粘着层,将芯片粘合在所述接班的腔部;
包括以下步骤:
S1:待封装产品进行等离子体清洗处理;
S2:将电镀金属层及至少一个待封装的芯片贴装于载板上,形成包封层;
S3:剥离所述载板,露出所述芯片的一面;
S4:再进行等离子体清洗处理;
S5:载板下表面形成与所述电镀金属层连接的多个节距大于所述多个焊垫节距的金属凸点。
2.根据权利要求1所述的半导体封装方法,其特征在于:所述电极包括靠近所述载板的第一表面及与所述第一表面相对的第二表面。
3.根据权利要求2所述的半导体封装方法,其特征在于:所述包封层覆盖在所述载板上。
4.根据权利要求3所述的半导体封装方法,其特征在于:S1中所述向等离子体清洗处理空间供给的处理气体中包含氧气,所述氧气的体积占比至少为70%。
5.根据权利要求4所述的半导体封装方法,其特征在于:所述电镀金属层的材质为抗氧化性金属。
6.根据权利要求5所述的半导体封装方法,其特征在于:S1中,在所述至少一个待封装芯片的正面形成保护层。
CN202110557690.0A 2021-05-21 2021-05-21 一种半导体封装方法 Pending CN115376930A (zh)

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