CN115372793B - Circuit detection method for integrated circuit - Google Patents
Circuit detection method for integrated circuit Download PDFInfo
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- CN115372793B CN115372793B CN202210947188.5A CN202210947188A CN115372793B CN 115372793 B CN115372793 B CN 115372793B CN 202210947188 A CN202210947188 A CN 202210947188A CN 115372793 B CN115372793 B CN 115372793B
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- integrated circuit
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
- G01N2021/8887—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges based on image processing techniques
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30141—Printed circuit board [PCB]
Abstract
The invention discloses a circuit detection method for an integrated circuit, relates to the technical field of integrated circuit detection, and solves the technical problems that in the prior art, in the detection process of the integrated circuit, the quality hidden danger is judged only through the electrical parameters of the integrated circuit in a power-on state, the wiring problem of the integrated circuit cannot be accurately detected, the detection precision of the integrated circuit is low, and the position of the hidden danger cannot be efficiently and accurately positioned; the invention is provided with a plurality of image acquisition devices for acquiring the detection images of the integrated circuit, determining the target element according to the detection images, establishing the element connection map of the integrated circuit, comparing the element connection map with the circuit standard map, and accurately identifying the layout and wiring problems of the integrated circuit; according to the invention, when the element connection map is constructed, the target element is selected according to the rule, and the element connection map is obtained by expanding by taking the target element as the center, so that the construction efficiency of the element connection map is improved, and the detection efficiency of the integrated current is further improved.
Description
Technical Field
The invention belongs to the field of integrated circuit detection, relates to a circuit detection technology for an integrated circuit, and particularly relates to a circuit detection method for the integrated circuit.
Background
The printed circuit board is integrated with a plurality of different integrated circuits to realize a certain function, and the function of the printed circuit board is affected by the hidden quality trouble of any integrated circuit, so that the problem of carrying out efficient nondestructive testing on the integrated circuit is an urgent need to be solved.
The prior art (patent invention with application number 2015100529240) discloses an integrated circuit detection method, device and system, which realize the problem of detecting the electrical parameters of an integrated circuit on a printed circuit board in a power-on state by arranging a plurality of detection circuits. In the prior art, in the detection process of the integrated circuit, the quality hidden danger is judged only by the electrical parameters of the integrated circuit in the power-on state, and the wiring problem of the integrated circuit cannot be accurately detected, so that the detection precision of the integrated circuit is low, and the position of the hidden danger cannot be efficiently and accurately positioned; therefore, a circuit inspection method for an integrated circuit is needed.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art; therefore, the invention provides a circuit detection method for an integrated circuit, which is used for solving the technical problems that in the detection process of the integrated circuit, the quality hidden danger is judged only by the electrical parameters of the integrated circuit in the power-on state, the wiring problem of the integrated circuit cannot be accurately detected, the detection precision of the integrated circuit is low, and the position of the hidden danger cannot be efficiently and accurately positioned in the prior art.
According to the invention, the detection image of the integrated circuit is acquired from multiple angles through the arranged image acquisition device, and the element connection map is constructed and acquired by expanding the target element to the periphery, so that the accuracy of the element connection map is ensured, and the construction efficiency can be improved; and comparing the element connection map with the circuit standard map to obtain a layout evaluation tag, and evaluating the quality hidden danger of the integrated circuit by combining the circuit function tag.
To achieve the above object, a first aspect of the present invention provides a circuit detection method for an integrated circuit, comprising:
simultaneously carrying out multi-angle acquisition on the integrated circuit through a plurality of image acquisition devices to obtain a plurality of detection images; selecting at least two circuit elements from the integrated circuit as target elements;
establishing an element connection map based on a plurality of detection images by taking the target element as a center; setting a layout evaluation label according to the three-dimensional comparison result of the element connection map and the circuit standard map;
carrying out power-on test on the integrated circuit to obtain corresponding electrical parameters, and setting a circuit function label according to a comparison result of the electrical parameters and a parameter range;
evaluating whether the integrated circuit has hidden quality danger according to the layout evaluation tag and the circuit function tag; and when the integrated circuit has the quality hidden danger, the quality hidden danger is checked and eliminated.
Preferably, the integrated circuit is transmitted to a detection area, and a plurality of image acquisition devices are arranged around the detection area;
when the integrated circuit reaches the detection area, the image acquisition devices acquire data to acquire a plurality of detection images; wherein, the image acquisition device is a camera.
Preferably, selecting the target element from the integrated circuit based on a number of the inspection images comprises:
establishing a plane model of the integrated circuit according to the detection images;
setting a reference line according to the characteristic information of the plane model; the characteristic information comprises shape and size, and the midpoint or bisector of a line segment between the central point and the boundary point of the plane model is positioned on a reference line;
at least two circuit elements are uniformly selected as the target elements based on the reference line.
Preferably, the method for establishing the intermediate connection map by taking the target element as a center comprises the following steps:
screening out a detection image containing the target element, and marking the detection image as an image I;
and identifying circuit elements in the first image, which are in connection relation with the target elements, and expanding the first image to the periphery by taking the target elements as centers to establish the intermediate connection map.
Preferably, in the process of establishing the intermediate connection map based on the target element as a center extension, comparing a plurality of established intermediate connection maps;
analyzing whether the intermediate connection maps can be spliced into a complete element connection map or not according to the comparison result; when the complete component connection map can be spliced, no expansion is performed.
Preferably, the obtaining the layout evaluation label based on the circuit standard map includes:
acquiring the circuit standard map; wherein the circuit standard map is generated according to a principle design diagram of the integrated circuit;
comparing the details of the component connection map and the circuit standard map, and setting the layout evaluation tag to be 0 when the details of the component connection map and the circuit standard map are consistent; otherwise, the layout evaluation flag is set to 1.
Preferably, the integrated circuit is subjected to parameter testing to obtain corresponding electrical parameters; wherein the electrical parameters include circuit parameters and pin parameters;
when the electrical parameters are all in the corresponding parameter ranges, setting the circuit function label to be 0; otherwise, setting the circuit function label to be 1.
Preferably, when both the layout evaluation tag and the circuit function tag are 0, it is determined that no quality hidden danger exists in the corresponding integrated circuit; if not, then,
when the layout evaluation label is 1, carrying out hidden danger detection on the circuit layout of the integrated circuit; when the circuit function label is 1, carrying out hidden danger detection on the functions of circuit elements and circuit pins in the integrated circuit; wherein the circuit pins include a functional pin and a ground pin.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is provided with a plurality of image acquisition devices for acquiring the detection images of the integrated circuit, determining the target element according to the detection images, establishing the element connection map of the integrated circuit, and comparing the element connection map with the circuit standard map, thereby accurately identifying the layout and wiring problems of the integrated circuit.
2. According to the invention, when the element connection map is constructed, the target element is selected according to the rule, and the intermediate connection map is obtained by expanding with the target element as the center, so that the element connection map is obtained, the construction efficiency of the element connection map is improved, and the detection efficiency of the integrated current is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of the working steps of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, in the detection process of the integrated circuit, the quality hidden danger is judged only through the electrical parameters of the integrated circuit in the power-on state, the integrated circuit cannot be represented by normal functions, the quality requirements of the layout and wiring of the integrated circuit cannot be met, namely, the wiring problem of the integrated circuit cannot be accurately detected, so that the detection precision of the integrated circuit is low, and the position of the hidden danger cannot be efficiently and accurately positioned.
According to the invention, the corresponding element connection map is established through a plurality of detection images acquired from multiple angles, the problems of missing soldering, insufficient soldering and the like can be identified by changing the identification threshold value in the construction process, the constructed element connection map is compared with the standard circuit map, and whether the layout meets the requirements or not can be judged; the function test is carried out on the integrated power, and whether the functions of all modules are normal is judged; when the layout and the function meet the requirements, the integrated circuit is judged to pass the detection, and no potential quality hazard exists.
Referring to fig. 1, a first embodiment of the present invention provides a circuit detection method for an integrated circuit, including:
s101: simultaneously carrying out multi-angle acquisition on the integrated circuit through a plurality of image acquisition devices to obtain a plurality of detection images; selecting at least two circuit elements from the integrated circuit as target elements;
s102: establishing an element connection map based on a plurality of detection images by taking a target element as a center; setting a layout evaluation label according to a three-dimensional comparison result of the element connection map and the circuit standard map;
s103: carrying out power-on test on the integrated circuit to obtain corresponding electrical parameters, and setting a circuit function label according to a comparison result of the electrical parameters and the parameter range;
s104: evaluating whether the integrated circuit has hidden quality danger according to the layout evaluation tag and the circuit function tag; when the integrated circuit has the quality hidden danger, the quality hidden danger is checked and eliminated.
The invention adds the detection content of layout and wiring on the basis of only carrying out functional detection on the integrated circuit in the prior art; in the process of detecting the wiring of the integrated circuit, the wiring detection is generally realized by an image recognition technology, but the problems of wiring intersection, false soldering and the like cannot be detected by simple image recognition, so the problem is solved by a multi-angle detection image.
In the application of the invention, the integrated circuit is transmitted to the detection area, and the plurality of image acquisition devices are arranged at the periphery of the detection area; when the integrated circuit reaches the detection area, the image acquisition devices acquire data to acquire a plurality of detection images; wherein, the image acquisition device is a camera.
When the integrated circuit needs to be detected, the integrated circuit is conveyed to a detection area, and then image data of the integrated circuit is acquired through a plurality of image acquisition devices around the detection area, namely a plurality of detection images are acquired. It should be understood that the integrated circuit is stereoscopic in nature, and therefore the detected image also represents the stereoscopic characteristic as much as possible, that is, the image data acquired by the integrated circuit at 360 ° in the detection area needs to be guaranteed, and the detection area can be set to be transparent or the integrated circuit can be shot in a turning manner.
The invention discloses a method for selecting a target element from an integrated circuit based on a plurality of detection images, which comprises the following steps:
establishing a planar model of the integrated circuit according to the plurality of detection images; setting a reference line according to the characteristic information of the plane model; at least two circuit elements are uniformly selected as target elements based on the reference line.
The planar model may be understood as a planar image, and the target element is selected only to improve the efficiency of constructing the element connection map, so that the position of the target element in the entire integrated circuit is comprehensively considered. And setting a reference line according to the characteristic information of the plane model, and selecting the target element with the help of the reference line. It is understood that the feature information includes a shape and a size, and a midpoint or bisector of a line segment between the center point and the boundary point of the plane model is located on the reference line, and the bisector includes a trisection point or a quartesion point.
The setting of the reference line is illustrated:
if the plane model of the integrated circuit is square, connecting four corners or diagonal lines in the positive direction;
trisecting the diagonal lines can obtain two points on each diagonal line, and connecting the trisecting points on the diagonal lines can also obtain a square which is smaller than the plane model;
the side length of the smaller square can be used as a reference line, and several circuit elements on the reference line or on both sides can be selected as target elements.
The invention uses a target element as a center to establish a corresponding intermediate connection map, and the intermediate connection map comprises the following steps:
screening out a detection image containing a target element, and marking the detection image as an image I; and identifying circuit elements in the first image, which are in connection relation with the target elements, and expanding the first image to the periphery by taking the target elements as centers to establish a middle connection map.
Screening out the first image according to the target element, identifying the connection relations between the target element and other circuit elements in the first image and between the target element and other circuit elements, and establishing an intermediate connection map according to the connection relations, wherein the establishment method is similar to the establishment of a knowledge map.
In the process of expanding and establishing the intermediate connection maps based on the target element as the center, the established intermediate connection maps are compared; analyzing whether the plurality of intermediate connection maps can be spliced into a complete element connection map or not according to the comparison result; when the complete component connection map can be spliced, no expansion is performed.
The intermediate connection map is not a complete component connection map, and the component connection map needs to be spliced based on the intermediate connection maps established by a plurality of target components. Therefore, in the process of expanding and updating the intermediate connection maps to the periphery, whether repeated contents exist in the intermediate connection maps or not needs to be compared, if the repeated contents exist, the repeated contents do not need to be expanded continuously, and the element connection maps can be obtained after the plurality of element connection maps are spliced. It should be noted that, due to the three-dimensional nature of the integrated circuit, there may be more than one component connection pattern to clearly express the layout information.
The invention discloses a layout evaluation label obtained based on a circuit standard map, which comprises the following steps:
acquiring a circuit standard map; comparing the details of the element connection map and the circuit standard map, and setting a layout evaluation label as 0 when the details of the element connection map and the circuit standard map are consistent; otherwise, the layout evaluation flag is set to 1.
The circuit standard map is generated according to a principle design map of the integrated circuit, the element connection map and the circuit standard map are compared to identify whether the layout of the integrated circuit is reasonable or not, and the problems of insufficient solder, missing solder and the like can be identified through multi-angle comparison.
The invention applies to carry out parameter test on an integrated circuit to obtain corresponding electrical parameters; wherein the electrical parameters comprise circuit parameters and pin parameters; when the electrical parameters are all in the corresponding parameter ranges, setting the circuit function label to be 0; otherwise, the circuit function flag is set to 1. It should be noted that, for the related scheme of performing the functional test on the integrated circuit, reference may be made to the invention patent application No. 2015100529240.
When the layout evaluation tag and the circuit function tag are both 0, judging that the corresponding integrated circuit has no quality hidden trouble; otherwise, when the layout evaluation label is 1, carrying out hidden danger detection on the circuit layout of the integrated circuit; when the circuit function label is 1, carrying out hidden danger detection on the functions of circuit elements and circuit pins in the integrated circuit; the circuit pins comprise a functional pin and a grounding pin.
The working principle of the invention is as follows:
simultaneously carrying out multi-angle acquisition on the integrated circuit through a plurality of image acquisition devices to obtain a plurality of detection images; at least two circuit elements are selected from the integrated circuit as target elements.
Establishing an element connection map based on a plurality of detection images by taking a target element as a center; and setting a layout evaluation label according to the three-dimensional comparison result of the element connection map and the circuit standard map.
And carrying out power-on test on the integrated circuit to obtain corresponding electrical parameters, and setting a circuit function label according to a comparison result of the electrical parameters and the parameter range.
Evaluating whether the integrated circuit has hidden quality danger according to the layout evaluation tag and the circuit function tag; when the integrated circuit has the quality hidden trouble, the quality hidden trouble is eliminated by checking.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.
Claims (6)
1. A circuit detection method for an integrated circuit, comprising:
simultaneously carrying out multi-angle acquisition on the integrated circuit through a plurality of image acquisition devices to obtain a plurality of detection images; selecting at least two circuit elements from the integrated circuit as target elements;
establishing an element connection map based on a plurality of detection images by taking the target element as a center; setting a layout evaluation label according to the three-dimensional comparison result of the element connection map and the circuit standard map;
carrying out power-on test on the integrated circuit to obtain corresponding electrical parameters, and setting a circuit function label according to a comparison result of the electrical parameters and a parameter range;
evaluating whether the integrated circuit has hidden quality danger according to the layout evaluation tag and the circuit function tag; when the integrated circuit has the quality hidden trouble, the quality hidden trouble is checked and eliminated;
selecting the target element from the integrated circuit based on a number of the inspection images, including:
establishing a plane model of the integrated circuit according to a plurality of detection images;
setting a reference line according to the characteristic information of the plane model; the characteristic information comprises shape and size, and the midpoint or bisector of a line segment between the central point and the boundary point of the plane model is positioned on a reference line;
uniformly selecting at least two circuit elements as the target elements based on the reference line;
establishing a corresponding intermediate connection map with the target element as a center, wherein the intermediate connection map comprises the following steps:
screening out a detection image containing the target element, and marking the detection image as an image I;
identifying circuit elements in the first image, which are in connection relation with target elements, and expanding the first image to the periphery by taking the target elements as centers to establish the intermediate connection map.
2. The circuit inspection method of claim 1, wherein the integrated circuit is transported to an inspection area, and a plurality of image capturing devices are disposed around the inspection area;
when the integrated circuit reaches the detection area, the image acquisition devices acquire data to acquire a plurality of detection images; wherein, the image acquisition device is a camera.
3. The circuit inspection method of claim 1, wherein during the process of establishing the intermediate connection pattern based on the target element as a center extension, the established intermediate connection patterns are compared;
analyzing whether the intermediate connection maps can be spliced into a complete element connection map or not according to the comparison result; when the complete element connection map can be spliced, no expansion is performed.
4. A circuit inspection method for an integrated circuit according to claim 1 or 3, wherein obtaining the layout evaluation labels based on the circuit standard map comprises:
acquiring the circuit standard map; wherein the circuit standard map is generated according to a principle design diagram of the integrated circuit;
comparing the details of the component connection map and the circuit standard map, and setting the layout evaluation tag to be 0 when the details of the component connection map and the circuit standard map are consistent; otherwise, the layout evaluation flag is set to 1.
5. The circuit testing method of claim 1, wherein the integrated circuit is subjected to parameter testing to obtain corresponding electrical parameters; wherein the electrical parameters include circuit parameters and pin parameters;
when the electrical parameters are all in the corresponding parameter ranges, setting the circuit function label to be 0; otherwise, setting the circuit function label to be 1.
6. The circuit detection method for the integrated circuit as claimed in claim 5, wherein when both the layout evaluation tag and the circuit function tag are 0, it is determined that there is no quality risk in the corresponding integrated circuit; if not, then,
when the layout evaluation label is 1, carrying out hidden danger detection on the circuit layout of the integrated circuit; when the circuit function label is 1, carrying out hidden danger detection on the functions of circuit elements and circuit pins in the integrated circuit; wherein the circuit pins include a functional pin and a ground pin.
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| CN202210947188.5A CN115372793B (en) | 2022-08-09 | 2022-08-09 | Circuit detection method for integrated circuit |
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| CN202210947188.5A CN115372793B (en) | 2022-08-09 | 2022-08-09 | Circuit detection method for integrated circuit |
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| CN113238142A (en) * | 2021-06-07 | 2021-08-10 | 马鞍山骏展科技有限公司 | Method and system for integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2143944B (en) * | 1983-07-25 | 1986-12-03 | Lloyd Doyle Ltd | Inspection of printed wiring boards |
| JPH0766036B2 (en) * | 1985-02-28 | 1995-07-19 | 日本電信電話株式会社 | Integrated circuit test method and test apparatus |
| JPH06102328A (en) * | 1992-09-22 | 1994-04-15 | Nippon Steel Corp | Failure diagnosting device for semiconductor device and failure diagnostic method using it |
| JPH08285785A (en) * | 1995-04-14 | 1996-11-01 | Seiwa Denki Kk | Soldering inspection apparatus |
| CN114022407A (en) * | 2021-09-18 | 2022-02-08 | 国营芜湖机械厂 | Intelligent detection and diagnosis method for circuit board based on infrared thermal image and deep learning |
| CN114518526A (en) * | 2022-02-14 | 2022-05-20 | 深圳市微特精密科技股份有限公司 | Automatic testing machine control system suitable for PCB board ICT |
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| CN113238142A (en) * | 2021-06-07 | 2021-08-10 | 马鞍山骏展科技有限公司 | Method and system for integrated circuit |
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