CN113723039B - PCB file inspection method, device and equipment - Google Patents
PCB file inspection method, device and equipment Download PDFInfo
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- CN113723039B CN113723039B CN202010456107.2A CN202010456107A CN113723039B CN 113723039 B CN113723039 B CN 113723039B CN 202010456107 A CN202010456107 A CN 202010456107A CN 113723039 B CN113723039 B CN 113723039B
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- 238000007689 inspection Methods 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000013461 design Methods 0.000 claims abstract description 53
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 103
- 229910052802 copper Inorganic materials 0.000 claims description 103
- 239000010949 copper Substances 0.000 claims description 103
- 238000004590 computer program Methods 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 14
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 238000003466 welding Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000007480 spreading Effects 0.000 description 6
- 238000003892 spreading Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000012216 screening Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012850 discrimination method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The application provides a method, a device and equipment for checking a PCB file, wherein the method comprises the following steps: acquiring all patch pads with network attributes in a PCB file; determining the device type corresponding to the patch pad, and determining the connection mode of the patch pad; and executing corresponding inspection according to the device type and the connection mode so as to finish inspection of all the patch pads. The chip device is mainly at risk for processing due to heat dissipation problem generated during welding due to unqualified design in the PCB file, so that the bonding pads corresponding to all the chip devices are obtained, and the task amount is reduced; and corresponding inspection is executed according to the types of different device types and corresponding connection modes, so that the differential inspection of different devices is realized.
Description
Technical Field
The application relates to the technical field of PCB file inspection, in particular to a PCB file inspection method, a PCB file inspection device and PCB file inspection equipment.
Background
With the continuous increase of chip technology development and product research and development functional requirements, the application of closely spaced devices and miniaturized devices on a PCB is becoming wider and wider. The pitch of the conventional closely-spaced IC pins is 0.5mm, 0.4mm, 0.35mm and the like, and the common types of miniaturized type resistance-capacitance-sensing packages are 0402, 0201 and the like. The phenomenon that the wiring and copper laying of the device exceed the width of a bonding pad can occur frequently during PCB design, and then the problems of cold joint, tombstoning, short circuit and the like caused by too fast heat dissipation or uneven heat dissipation can be caused during single board processing, the single board processing yield is reduced, the problem of misjudgment of line AOI visual recognition can also occur, the processing efficiency is affected, the problem is difficult to cover comprehensively through self-checking and evaluation during PCB design, and the design modes of different devices are different (wiring, pattern bonding, copper laying, copper skin hole digging and the like), so that the device is designed reasonably according to actual application requirements and processing baselines.
At present, a main line width inspection tool is adopted for PCB design super-bonding pad inspection: the tool can only check a single connection mode of the single board wiring, can check whether the connection mode of the bonding pad is qualified or not by singly comparing the single board wiring with the bonding pad, and can not perform bonding pad check on other connection modes and design check on a differential device.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The purpose of the application is to provide a PCB file inspection method, a PCB file inspection device and a PCB file inspection equipment, which can execute corresponding inspection according to different device types and corresponding connection modes, and realize the differentiated inspection of different devices. The specific scheme is as follows:
the application provides a PCB file inspection method, which comprises the following steps:
acquiring all patch pads with network attributes in a PCB file;
determining the device type corresponding to the patch pad, and determining the connection mode of the patch pad;
and executing corresponding inspection according to the device type and the connection mode to finish inspection of all the patch pads.
Optionally, the determining the device type corresponding to the patch pad includes:
and judging whether the device type of the patch pad is a resistance-capacitance sensing device or a non-resistance-capacitance sensing patch device.
Optionally, the performing the corresponding checking according to the device type and the connection mode includes:
if the device type is the resistance-capacitance sensing device and the connection mode of the patch pad is a wiring, acquiring the line width of the wiring;
judging whether the line width meets the resistance-capacitance sensing wiring condition or not;
and if the resistance-capacitance sensing wiring condition is not met, determining that the resistance-capacitance sensing device is unqualified in design.
Optionally, the performing the corresponding checking according to the device type and the connection mode includes:
if the device type is the resistance-capacitance sensing device and the connection mode of the patch bonding pad is copper paving, judging whether a cavity exists on a copper sheet corresponding to the copper paving;
if the cavity exists, judging whether the cavity intersects with the patch pad or not;
if not, judging whether the copper sheet is fully paved on the patch bonding pad;
and if the patch pad is paved, determining that the resistance-capacitance sensing device is unqualified in design.
Optionally, if the cavity does not exist, judging whether the copper sheet is fully paved on the patch pad;
and if the patch pad is paved, determining that the resistance-capacitance sensing device is unqualified in design.
Optionally, the determining whether the cavity intersects the patch pad includes:
determining a corresponding cavity polygon according to the size and the position of the cavity;
determining a corresponding pad polygon according to the size and the position of the patch pad;
judging whether an intersection area exists between the cavity polygon and the bonding pad polygon;
and if the intersection area does not exist, determining that the cavity does not intersect with the patch pad.
Optionally, the performing the corresponding checking according to the device type and the connection mode includes:
if the device type is the non-resistance-capacitance-sensing patch device and the connection mode of the patch pad is a wiring, acquiring the line width of the wiring;
judging whether the line width exceeds the size of the patch pad;
if yes, determining that the non-resistance-capacitance-sensing patch device is unqualified in design.
Optionally, the performing the corresponding checking according to the device type and the connection mode includes:
if the device type is the non-resistance-capacitance-sensing patch device and the connection mode of the patch bonding pad is copper paving, acquiring the positions of other bonding pads within a preset range of the patch bonding pad;
determining a relative position according to the current position of the patch bonding pad and the positions of the other bonding pads;
judging whether copper sheets are paved on the vertex coordinate sides corresponding to the relative positions in the patch bonding pads or not;
if yes, determining that the non-resistance-capacitance-sensing patch device is unqualified in design.
Optionally, the acquiring the positions of other pads within the preset range of the patch pad includes:
determining a corresponding polygon according to the size and the position of the patch pad and a preset expansion range;
and selecting the other bonding pads intersected with the polygon, and determining the positions of the other bonding pads.
Optionally, the determining whether the copper sheet is laid on the vertex coordinate side corresponding to the relative position in the patch pad includes:
when the number of the other bonding pads is one, judging whether the copper sheet is laid on the vertex coordinate side adjacent to the other bonding pads in the patch bonding pad;
and when the number of the other bonding pads is two, judging whether the copper sheets are laid on the four vertex coordinate sides in the bonding pad.
The application provides a PCB file inspection device, include:
the patch pad acquisition module is used for acquiring all patch pads with network attributes in the PCB file;
the device type and connection mode determining module is used for determining the device type corresponding to the patch pad and determining the connection mode of the patch pad;
and the checking module is used for executing corresponding checking according to the device type and the connection mode so as to finish checking of all the surface mount pads.
The application provides a PCB file check-out set includes:
a memory for storing a computer program;
and a processor for implementing the steps of the PCB file inspection method as described above when executing the computer program.
The application provides a PCB file inspection method, which comprises the following steps: acquiring all patch pads with network attributes in a PCB file; determining the device type corresponding to the patch pad and determining the connection mode of the patch pad; and executing corresponding inspection according to the device type and the connection mode so as to complete inspection of all the patch pads.
Therefore, the chip devices are mainly at risk for processing due to heat dissipation problem generated during welding caused by unqualified design in the PCB file, and therefore, the bonding pads corresponding to all the chip devices are obtained, and screening accuracy and efficiency are improved; corresponding inspection can be executed according to different device types and corresponding connection modes, and differentiated inspection of different devices is realized.
The application also provides a PCB file inspection device and a PCB file inspection device, which have the beneficial effects and are not repeated here.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
Fig. 1 is a flowchart of a method for inspecting a PCB file according to an embodiment of the present disclosure;
FIG. 2 is a flowchart of a process for inspecting a resistive-capacitive sensing device according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a flow chart for determining intersection according to an embodiment of the present application;
fig. 4 is a flowchart of an inspection process of a non-resistive-capacitive sensing patch device according to an embodiment of the present application;
fig. 5 is a flowchart of a specific PCB file inspection method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a PCB document inspection apparatus according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a PCB document inspection apparatus according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
At present, the inspection of the super bonding pad of the PCB design mainly adopts a line width inspection tool: the tool can only check a single connection mode of the single board wiring, and can check whether the connection mode of the bonding pad is qualified or not by comparing the single board wiring with the bonding pad singly, and can not perform bonding pad check on other connection modes and design check on a differential device. Based on the technical problems, the embodiment provides a PCB file inspection method, which obtains all the patch pads with network attributes, and improves screening accuracy and efficiency; according to the types and the connection modes of different devices, corresponding inspection is performed, so that the differential inspection of the different devices is realized, referring specifically to fig. 1, fig. 1 is a flowchart of a PCB file inspection method provided in an embodiment of the present application, and specifically includes:
s101, acquiring all patch pads with network attributes in a PCB file;
specifically, the PCB file is a file in the design stage, and when the PCB file is qualified, the production of the PCB board is performed according to the PCB file. Many devices, many traces, etc. are included in the PCB file.
Due to the differences in device types, the corresponding pad types are different, including but not limited to: the patch pad device is subjected to design inspection in the embodiment, and all patch pads with network attributes in the PCB file are acquired in the embodiment, so that the task amount is reduced, and the screening accuracy and efficiency are improved.
S102, determining the device type corresponding to the patch pad, and determining the connection mode of the patch pad;
s103, corresponding inspection is executed according to the device type and the connection mode, so that inspection of all the surface mount pads is completed.
Among them, device types include, but are not limited to: a resistive-capacitive sensing device, a non-resistive-capacitive sensing patch device. The connection mode of the patch pad includes, but is not limited to: routing and copper laying. The processing mode mainly considers that in the conventional design, different design specifications exist between the resistance-capacitance sensing device and the closely-spaced device: conventional 0201 device routing does not exceed 10mil,0402 device routing does not exceed 12mil, and hole digging is performed for power network copper laying. For devices such as close-spaced ICs, the conventional design method is to ensure that the wiring and copper plating cannot exceed the width of the bonding pad.
The device type obtaining method can obtain the device type through a function mode; or acquiring the device type by acquiring parent item attribute of the patch pad, namely device attribute information when grabbing the patch pad object; the present embodiment is not limited, and the user may set the device according to actual needs, so long as the purpose of the present embodiment can be achieved.
Based on the technical scheme, the chip devices mainly exist in the PCB file, which are at risk of processing due to heat dissipation problem generated during welding due to unqualified design, so that bonding pads corresponding to all the chip devices are obtained, and screening accuracy and efficiency are improved; corresponding inspection can be executed according to different device types and corresponding connection modes, and differentiated inspection of different devices is realized.
Based on the above embodiment, when the device type is a resistive-capacitive sensing device, in order to accurately obtain the inspection result, please refer to fig. 2, fig. 2 is a flowchart of an inspection process of the resistive-capacitive sensing device according to an embodiment of the present application, which includes:
s201, judging whether the connection mode of the patch pad is wiring or copper laying;
the connection mode is specifically the connection mode between the current patch bonding pad and other bonding pads. In the resistive-capacitive sensing device, the main inspection is divided into two types, routing and copper laying. Wherein the resistive-capacitive sensing routing condition cannot be exceeded when routing, for example, for 0201 devices, the resistive-capacitive sensing routing condition is not more than 10mil, and the resistive-capacitive sensing routing condition of 0402 devices is not more than 12mil; when copper is paved, hole digging treatment is needed for power networks such as resistance-capacitance sensing devices, so that the processing and welding risks caused by too fast heat dissipation or uneven heat dissipation can be avoided.
If the connection mode of the patch pad is the routing, executing step S202; if the connection mode of the bonding pads is copper plating, step S205 is performed.
S202, acquiring the line width of the wiring;
s203, judging whether the line width meets the resistance-capacitance sensing wiring condition;
if the resistive-capacitive sensing wiring condition is not satisfied, executing step S204; and if the resistance-capacitance sensing wiring condition is met, determining that the resistance-capacitance sensing device is qualified in design.
S204, determining that the resistance-capacitance sensing device is unqualified in design;
s205, judging whether a cavity exists on the copper sheet corresponding to the copper laying;
specifically, the method for judging whether the holes exist on the copper sheet is to acquire the copper sheet voids attribute, and judge whether the holes exist from the voids attribute. The number of voids may be 0, 1, 2, or other values.
If there is a hole, executing step S206; if there is no hole, step S207 is performed.
S206, judging whether a cavity is intersected with the patch pad or not;
in particular, many devices are connected to the copper sheet, and thus, when the copper sheet has voids, the locations of the voids may be on pads of other devices. In this step, in order to determine whether there is an intersection with the cavity on the chip pad, if there is an intersection, the device design corresponding to the chip pad is qualified. If not, step S207 is performed.
Further, for the copper sheet hole-digging inspection of the 0402/0201 resistance-capacitance sensing device, on the SKILL grammar, the Voids attribute of the whole network copper sheet can be obtained only through a function, but in the PCB design, the whole copper sheet is likely to be connected with a plurality of resistance-capacitance sensing pads and chip pads, so that whether copper sheet holes exist on the traversed patch pad cannot be directly positioned through codes. Therefore, the present embodiment provides a way to convert two abstract attributes into similar objects capable of performing data operation, referring specifically to fig. 3, fig. 3 is a schematic flow diagram of determining intersection provided in the embodiment of the present application, which specifically includes:
s2061, determining a corresponding cavity polygon according to the size and the position of the cavity;
specifically, the hollow polygon is a polygonal object having a shape and a size corresponding to those of the hollow.
S2062, determining a corresponding pad polygon according to the size and the position of the patch pad;
specifically, the pad polygon is a polygonal object that is consistent with the shape and size of the patch pad. Obtaining the Voids attribute of the copper sheet and adding an array; a Polygon object is created for vois and traversed patch pads in turn, i.e. a hole Polygon and pad Polygon are determined, the Polygon positions being consistent with vois, patch pads. This way, two abstract properties are converted into homogeneous objects that can be subjected to a datamation operation.
S2063, judging whether an intersection area exists between the cavity polygon and the bonding pad polygon;
and carrying out logic operation on the data of the cavity polygon and the pad polygon, and judging whether an area intersection exists or not.
S2064, if there is no intersection region, determining that there is a void that does not intersect with the patch pad.
If the result is True, determining that the copper sheet on the patch pad has a cavity; if not, if False, then step S207 is performed.
S207, judging whether the copper sheet is fully paved with the patch bonding pads;
specifically, whether the copper sheet is fully paved with the patch pad is judged, specifically, whether the copper sheet attribute is detected on four vertexes of the patch pad is judged, and if the copper sheet attribute is detected on all four vertexes, the patch pad is fully paved with the copper sheet. It will be appreciated that when the copper sheet is regular, it may be detected whether the three vertices of the patch pad have copper sheet properties, and if so, it is determined that the copper sheet is full of the patch pad, otherwise, the copper sheet is not full of the patch pad. When the copper sheet is at the terminal unfilled corner of pad, then can only detect whether four summit of paster pad has the copper sheet attribute, if all have, confirm that the copper sheet is full of paster pad, otherwise, the copper sheet is not full of paster pad. If the bonding pads are fully paved, step S204 is executed, and if the bonding pads are not fully paved, the design of the resistance-capacitance sensing device is determined to be qualified.
Based on the above technical scheme, the embodiment provides an inspection method for a resistive-capacitive sensor, which can automatically inspect the design scheme of the resistive-capacitive sensor under two connection modes of wiring and copper laying, and the automatic inspection is quick and accurate, so that the manpower input is greatly saved, the inspection is supported along with the change, and the omission is avoided.
Based on the above embodiment, when the device type is a non-resistive-capacitive-sensing patch device, in order to accurately obtain the inspection result, please refer to fig. 4, fig. 4 is a flowchart of an inspection process of the non-resistive-capacitive-sensing patch device according to the embodiment of the present application, which includes:
s301, judging whether the connection mode of the patch pad is wiring or copper laying;
specifically, non-resistive-capacitive sensing chip devices such as closely spaced IC devices need to ensure that the traces and copper plating cannot exceed the chip pad width. When the wiring and copper laying exceed the width of the bonding pad, the problems of cold joint, short circuit and the like caused by too fast heat dissipation or uneven heat dissipation during the processing of the single board can be further caused, the processing yield of the single board is reduced, and the problem of misjudgment of the visual identification of the production line AOI can be also caused, so that the processing efficiency is affected.
Specifically, if the wiring is performed, step S302 is executed; if copper is to be plated, step S305 is performed.
S302, acquiring the line width of the wiring;
s303, judging whether the line width exceeds the size of the patch pad;
if the size of the bonding pad is exceeded, executing step S304; and if the size of the chip bonding pad is not exceeded, determining that the non-resistance-capacitance chip device is qualified in design.
S304, determining that the design of the non-resistance-capacitance-sensing patch device is unqualified;
s305, acquiring positions of other bonding pads within a preset range of the bonding pad;
the preset range may be 9 mils, that is, the preset range is a range of 9 mils above and below and around the patch pad, the preset range is greater than the center-to-center spacing of two adjacent patch pads in a closely spaced device, and the determined other pads are closest pads to the patch pad. It will be appreciated that when the patch pad corresponds to a conventional dense device such as an IC device, the patch pad is located in two relative positions, one being a four corner position, the other pad includes 1, and the other pad is located in an intermediate position, the other pad includes 2.
The purpose of this step is to obtain the positions of other pads, and the specific positions can be determined according to the vertex coordinates of other pads.
Specifically, step S305 may include: determining a corresponding polygon according to the size, the position and the preset range of the patch pad; and selecting other bonding pads intersected with the polygon by a frame, and determining the positions of the other bonding pads. For example, an initial polygon having the same size as the patch pad is first obtained, and then the initial polygon is obtained by expanding the preset range in a preset range (for example, 9 mil) in the vertical direction and the horizontal direction of the initial polygon.
S306, determining the relative positions according to the current positions of the bonding pads and the positions of other bonding pads;
wherein the current position is determined according to the vertex coordinates of the patch pad.
S307, judging whether copper sheets are paved on the vertex coordinate sides corresponding to the relative positions in the patch bonding pads;
correspondingly, S307 specifically includes: when the number of other bonding pads is one, judging whether copper sheets are paved on the vertex coordinate sides adjacent to the other bonding pads in the bonding pads; when the number of other bonding pads is two, judging whether copper sheets are paved on four vertex coordinate sides in the bonding pad.
Specifically, when the number of other bonding pads is one, determining that the network bonding pad is located at four corners, and judging whether copper spreading exists on the vertex coordinate side of the bonding pad relative position through the relative position (namely, copper spreading on the bonding pad side cannot exceed the bonding pad size of the bonding pad, and copper spreading on the bonding pad-free side).
If copper sheets are paved, executing step S304; if no copper sheet is laid, the non-resistance-capacitance-sense patch device is determined to be qualified in design.
Specifically, when the device type is a non-resistance-capacitance-sensing patch device, a dense-spacing device bonding pad is screened out by acquiring Polygon and a relative position discrimination method, and the non-resistance-capacitance-sensing patches with different angles and different positions are inspected, wherein the thought is as follows:
1. and sequentially acquiring the position coordinates and angles of four vertexes of one non-resistive-capacitive-inductive patch in all non-resistive-capacitive-inductive patches, and creating a Polygon (initial Polygon) according to the position coordinates and angles.
2. And expanding the Polygon by 9mil and storing the Polygon into a variable P to obtain a Polygon, wherein the Polygon is used as the judgment distance of the closely-spaced device.
3. Selecting other bonding pads intersected with the P in a frame mode, counting an array B, deducing the current positions of the bonding pads in all devices according to the number of array elements, and obtaining vertex coordinates of the other bonding pads in the B;
4. (1) when the number is equal to 0, the device is not a closely spaced device. (2) When the number is equal to 1, the non-resistance-capacitance-sensing patch devices are positioned at four corners of the device, and the relative positions of the non-resistance-capacitance-sensing patch devices and other bonding pads are judged through the coordinates of the non-resistance-capacitance-sensing patch devices, so that whether copper spreading exists on the vertex coordinate side of the relative positions of the non-resistance-capacitance-sensing patch devices (namely, copper spreading on the bonding pad side cannot exceed the size of the bonding pad of the non-resistance-capacitance-sensing patch devices, and copper spreading on the bonding pad-free side) is judged. (3) When the number is equal to 2, the non-resistance-capacitance-sensing patch is positioned at the middle position of the device, and the position directly judges whether copper is paved at the four vertexes of the non-resistance-capacitance-sensing patch.
Based on the above technical scheme, the embodiment provides an inspection method for a non-resistance-capacitance-sensing chip device, which can automatically inspect the design scheme of the non-resistance-capacitance-sensing chip device under two connection modes of wiring and copper laying, and automatically inspect the chip device quickly and accurately, thereby greatly saving labor input, supporting follow-up inspection and avoiding omission.
In summary, the above two device types are distinguished and inspected, and the design scheme of all devices under two connection modes of wiring and copper laying can be automatically inspected, so that the automatic inspection is quick and accurate, the labor investment is greatly saved, the follow-up inspection is supported, and omission is avoided; the method meets the differential inspection of different types of devices, and the program algorithm inspection basically covers all conventional design modes, so that the single board processing risk is reduced, and the product yield is improved; and the parameter customization can be used for changing and judging the definition value of the close-spacing device according to the design requirement of the product and the processing baseline of the board factory.
Based on any one of the foregoing embodiments, the present embodiment provides a specific method for inspecting a PCB file, referring to fig. 5, fig. 5 is a schematic flow chart of the specific method for inspecting a PCB file provided in the embodiment of the present application, which includes:
grabbing all the patch bonding pads with network attributes, and putting the patch bonding pads into an array A;
traversing the array to obtain vertex coordinates on the patch pad;
grabbing the attribute of the patch pad, and judging whether the device type of the patch pad is a resistance-capacitance sensing device or a non-resistance-capacitance sensing patch device;
if the chip is a resistance-capacitance sensing device, judging whether a wiring line connected with the chip bonding pad is a copper-plated shape;
if the wiring is performed, acquiring the line width of the wiring, and judging whether the line width meets the resistance-capacitance sensing wiring condition; if the resistance-capacitance sensing wiring condition is not met, determining that the design of the resistance-capacitance sensing device is unqualified;
if the copper is paved, judging whether a cavity exists on the copper sheet corresponding to the copper paving;
if the cavity exists, judging whether the cavity intersects with the patch pad; if the bonding pads are not intersected, judging whether the bonding pads are paved with the copper sheets or not; if the copper sheet is paved with the patch bonding pads, determining that the resistance-capacitance sensing device is unqualified in design;
if the holes do not exist, judging whether the copper sheet is paved with the patch bonding pads or not; if the copper sheet is paved with the patch bonding pads, determining that the resistance-capacitance sensing device is unqualified in design;
if the chip device is a non-resistance-capacitance-sensing chip device, judging whether wiring connected with a chip bonding pad or copper paving;
if the wiring is performed, acquiring the line width of the wiring, and judging whether the line width exceeds the size of the patch pad; if yes, determining that the design of the non-resistance-capacitance-sensing patch device is unqualified;
if copper is paved, selecting other bonding pads in 9mil around the non-resistance-capacitance-sensing patch as an array B;
traversing the array B to obtain vertex coordinates (namely, positions of other bonding pads in a preset range of the bonding pads);
acquiring the relative positions of bonding pads in the array A and the array B (determining the relative positions according to the current positions of bonding pads and the positions of other bonding pads); judging whether copper sheets exist on the vertex coordinates of the bonding pad in the A according to the relative positions (judging whether copper sheets are paved on the vertex coordinate sides corresponding to the relative positions in the bonding pad); if yes, determining that the non-resistance-capacitance-sensing patch device is unqualified in design.
The following describes a PCB document inspection apparatus according to an embodiment of the present application, and the PCB document inspection apparatus described below and the PCB document inspection method described above may be referred to correspondingly, and referring to fig. 6, fig. 6 is a schematic structural diagram of the PCB document inspection apparatus according to an embodiment of the present application, including:
a patch pad acquisition module 401, configured to acquire all patch pads with network attributes in the PCB file;
a device type and connection mode determining module 402, configured to determine a device type corresponding to the patch pad, and determine a connection mode of the patch pad;
and the checking module 403 is configured to perform corresponding checking according to the device type and the connection mode, so that checking of all the patch pads is completed.
Optionally, the device type and connection mode determining module 402 includes:
and the device type determining unit is used for judging whether the device type of the patch pad is a resistance-capacitance sensing device or a non-resistance-capacitance sensing patch device.
Optionally, the checking module 403 includes:
the first line width acquisition unit is used for acquiring the line width of the wiring if the device type is a resistance-capacitance sensing device and the connection mode of the patch pad is the wiring;
the line width judging unit is used for judging whether the line width meets the resistance-capacitance sensing wiring condition;
and the first checking result determining unit is used for determining that the resistive-capacitive sensing device is unqualified in design if the resistive-capacitive sensing wiring condition is not met.
Optionally, the checking module 403 includes:
the cavity judging unit is used for judging whether a cavity exists on the copper sheet corresponding to the copper laying if the device type is a resistance-capacitance sensing device and the connection mode of the patch bonding pad is copper laying;
the intersection judging unit is used for judging whether the cavity is intersected with the patch pad if the cavity is present;
the judging unit is used for judging whether the copper sheet is paved with the patch pad or not if the copper sheet is not intersected;
and the second checking result determining unit is used for determining that the resistance-capacitance sensing device is unqualified in design if the surface mount pad is paved.
Optionally, the checking module 403 further includes:
the full judging unit is used for judging whether the copper sheet is full of the patch bonding pad if no cavity exists;
and the third checking result determining unit is used for determining that the resistance-capacitance sensing device is unqualified in design if the surface mount pad is paved.
Optionally, the intersection judgment unit includes:
a cavity polygon determining subunit, configured to determine a corresponding cavity polygon according to the size and position of the cavity;
a pad polygon determining subunit, configured to determine a corresponding pad polygon according to the size and the position of the patch pad;
a judging subunit, configured to judge whether an intersection area exists between the hole polygon and the pad polygon;
and the determining subunit is used for determining that the cavity is disjoint with the patch pad if the intersection area does not exist.
Optionally, the checking module 403 includes:
the second line width obtaining unit is used for obtaining the line width of the wiring if the device type is a non-resistance-capacitance patch device and the connection mode of the patch pad is the wiring;
a size judging unit for judging whether the line width exceeds the size of the patch pad;
and the fourth checking result determining unit is used for determining that the non-resistance-capacitance-sensing patch device is unqualified in design if the non-resistance-capacitance-sensing patch device is qualified.
Optionally, the checking module 403 includes:
the position acquisition unit is used for acquiring the positions of other bonding pads within a preset range of the bonding pads if the device type is a non-resistance-capacitance sensing bonding device and the bonding pads are connected in a copper paving mode;
a relative position determining unit for determining a relative position according to the current position of the patch pad and the positions of other pads;
the copper sheet judging unit is used for judging whether copper sheets are paved on the vertex coordinate sides corresponding to the relative positions in the patch bonding pads;
and a fifth checking result determining unit, configured to determine that the non-resistive-capacitive sensing patch device is not qualified in design if the non-resistive-capacitive sensing patch device is qualified.
Optionally, the position acquisition unit includes:
a polygon determining subunit, configured to determine a corresponding polygon according to the size, the position and the preset range of the patch pad;
and the position determining subunit is used for framing other bonding pads intersected with the polygon and determining the positions of the other bonding pads.
Optionally, the copper sheet judging unit includes:
the first copper sheet judging subunit is used for judging whether copper sheets are paved on the vertex coordinate sides adjacent to other bonding pads in the bonding pads when the number of the other bonding pads is one;
and the second copper sheet judging subunit is used for judging whether copper sheets are paved on four vertex coordinate sides in the patch bonding pad or not when the number of other bonding pads is two.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
The following describes an electronic device provided in an embodiment of the present application, and the electronic device described below and the method for inspecting a PCB file described above may be referred to correspondingly, please refer to fig. 7, fig. 7 is a schematic structural diagram of a PCB file inspection device provided in an embodiment of the present application, which includes:
a memory 501 for storing a computer program;
a processor 502 for implementing the steps of the PCB file inspection method as above when executing a computer program.
Since the embodiment of the electronic device part corresponds to the embodiment of the PCB file inspection method part, the embodiment of the electronic device part is referred to the description of the embodiment of the PCB file inspection method part, and is not repeated herein.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above describes in detail a PCB document inspection method, a PCB document inspection apparatus, and a PCB document inspection device provided in the present application. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
Claims (10)
1. A method for inspecting a PCB document, comprising:
acquiring all patch pads with network attributes in a PCB file; the PCB file is a file in a design stage;
determining the device type corresponding to the patch pad, and determining the connection mode of the patch pad; the connection mode is the connection mode between the current patch bonding pad and other bonding pads;
corresponding inspection is executed according to the device type and the connection mode so as to complete inspection of all the patch pads;
wherein, the performing the corresponding check according to the device type and the connection mode includes: if the device type is a resistance-capacitance sensing device and the connection mode of the patch pad is a wiring, acquiring the line width of the wiring; judging whether the line width meets the resistance-capacitance sensing wiring condition or not; if the resistance-capacitance sensing wiring condition is not met, determining that the resistance-capacitance sensing device is unqualified in design;
the corresponding checking is executed according to the device type and the connection mode, and the method comprises the following steps: if the device type is the resistance-capacitance sensing device and the connection mode of the patch bonding pad is copper paving, judging whether a cavity exists on a copper sheet corresponding to the copper paving; if the cavity exists, judging whether the cavity intersects with the patch pad or not; if not, judging whether the copper sheet is fully paved on the patch bonding pad; and if the patch pad is paved, determining that the resistance-capacitance sensing device is unqualified in design.
2. The method of inspecting a PCB file according to claim 1, wherein determining the device type corresponding to the patch pad includes:
and judging whether the device type of the patch pad is a resistance-capacitance sensing device or a non-resistance-capacitance sensing patch device.
3. The method of claim 1, wherein if the void is not present, determining whether the copper sheet is full of the patch pad;
and if the patch pad is paved, determining that the resistance-capacitance sensing device is unqualified in design.
4. The PCB file inspection method of claim 1, wherein the determining whether there is the void intersecting the patch pad includes:
determining a corresponding cavity polygon according to the size and the position of the cavity;
determining a corresponding pad polygon according to the size and the position of the patch pad;
judging whether an intersection area exists between the cavity polygon and the bonding pad polygon;
and if the intersection area does not exist, determining that the cavity does not intersect with the patch pad.
5. The PCB file inspection method of claim 2, wherein the performing the corresponding inspection according to the device type and the connection method includes:
if the device type is the non-resistance-capacitance-sensing patch device and the connection mode of the patch pad is a wiring, acquiring the line width of the wiring;
judging whether the line width exceeds the size of the patch pad;
if yes, determining that the non-resistance-capacitance-sensing patch device is unqualified in design.
6. The PCB file inspection method of claim 2, wherein the performing the corresponding inspection according to the device type and the connection method includes:
if the device type is the non-resistance-capacitance-sensing patch device and the connection mode of the patch bonding pad is copper paving, acquiring the positions of other bonding pads within a preset range of the patch bonding pad;
determining a relative position according to the current position of the patch bonding pad and the positions of the other bonding pads;
judging whether copper sheets are paved on the vertex coordinate sides corresponding to the relative positions in the patch bonding pads or not;
if yes, determining that the non-resistance-capacitance-sensing patch device is unqualified in design.
7. The PCB file inspection method of claim 6, wherein the obtaining the positions of other pads within the predetermined range of the patch pad includes:
determining a corresponding polygon according to the size and the position of the patch pad and a preset expansion range;
and selecting the other bonding pads intersected with the polygon, and determining the positions of the other bonding pads.
8. The method of inspecting a PCB document according to claim 7, wherein the determining whether the copper sheet is laid on the vertex coordinate side corresponding to the relative position in the patch pad includes:
when the number of the other bonding pads is one, judging whether the copper sheet is laid on the vertex coordinate side adjacent to the other bonding pads in the patch bonding pad;
and when the number of the other bonding pads is two, judging whether the copper sheets are laid on the four vertex coordinate sides in the bonding pad.
9. A PCB document inspection apparatus, comprising:
the patch pad acquisition module is used for acquiring all patch pads with network attributes in the PCB file; the PCB file is a file in a design stage;
the device type and connection mode determining module is used for determining the device type corresponding to the patch pad and determining the connection mode of the patch pad; the connection mode is the connection mode between the current patch bonding pad and other bonding pads;
the checking module is used for executing corresponding checking according to the device type and the connection mode so as to finish checking of all the surface mount pads;
the inspection module is specifically configured to obtain a line width of a trace if the device type is a resistive-capacitive device and the connection mode of the patch pad is the trace; judging whether the line width meets the resistance-capacitance sensing wiring condition or not; if the resistance-capacitance sensing wiring condition is not met, determining that the resistance-capacitance sensing device is unqualified in design;
the inspection module is specifically configured to determine whether a hole exists in a copper sheet corresponding to copper laying if the device type is the resistive-capacitive sensing device and the connection mode of the patch pad is copper laying; if the cavity exists, judging whether the cavity intersects with the patch pad or not; if not, judging whether the copper sheet is fully paved on the patch bonding pad; and if the patch pad is paved, determining that the resistance-capacitance sensing device is unqualified in design.
10. A PCB document inspection apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the PCB file inspection method according to any one of claims 1 to 8 when executing the computer program.
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| CN202010456107.2A CN113723039B (en) | 2020-05-26 | 2020-05-26 | PCB file inspection method, device and equipment |
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| CN202010456107.2A CN113723039B (en) | 2020-05-26 | 2020-05-26 | PCB file inspection method, device and equipment |
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| CN101398861A (en) * | 2007-09-28 | 2009-04-01 | 英业达股份有限公司 | Layout detection method in electron component welding region |
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| WO2020000948A1 (en) * | 2018-06-28 | 2020-01-02 | 郑州云海信息技术有限公司 | Method, apparatus and device for generating route keep out region for differential pair pad, and medium |
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| CN101398861A (en) * | 2007-09-28 | 2009-04-01 | 英业达股份有限公司 | Layout detection method in electron component welding region |
| CN102338854A (en) * | 2010-07-27 | 2012-02-01 | 迈普通信技术股份有限公司 | Circuit board test case generation system and method thereof |
| CN102636741A (en) * | 2012-04-27 | 2012-08-15 | 北京星河康帝思科技开发有限公司 | Method and system for testing circuit board |
| WO2020000948A1 (en) * | 2018-06-28 | 2020-01-02 | 郑州云海信息技术有限公司 | Method, apparatus and device for generating route keep out region for differential pair pad, and medium |
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