CN115365173A

CN115365173A - Chip capacitance testing device and testing and packaging device using same

Info

Publication number: CN115365173A
Application number: CN202110540281.XA
Authority: CN
Inventors: 熊焰明; 李世斌
Original assignee: Jiangsu Eeest Advanced Technology Co ltd
Current assignee: Jiangsu Eeest Advanced Technology Co ltd
Priority date: 2021-05-18
Filing date: 2021-05-18
Publication date: 2022-11-22

Abstract

The invention provides a chip capacitance testing device and a testing and packaging device using the testing device, which can carry out batch testing on chip capacitance and has high testing efficiency. The automatic packaging machine comprises a material taking station, a packaging station and a transfer mechanism, wherein a testing station is also arranged between the material taking station and the packaging station; the carrying box is used for storing more than one chip capacitor and comprises a pore plate and a circuit board which are sequentially arranged from top to bottom, an upper electrode is uniformly arranged above the circuit board, a vacuumizing hole is formed in the position of the circuit board corresponding to the chip capacitor, a containing hole for placing the chip capacitor is formed in the pore plate corresponding to the upper electrode, and the upper electrode is also connected with a lower electrode positioned below the circuit board through a conductive through hole; the test station comprises an upper probe card and a lower probe card, more than one probe is respectively arranged on the upper probe card and the lower probe card, the probe of the upper probe card is used for pressing and covering the chip capacitor, and the probe of the lower probe card is used for pressing and covering the lower electrode.

Description

Chip capacitance testing device and testing and packaging device using same

Technical Field

The invention relates to the technical field of capacitance testing devices, in particular to a chip capacitance testing device and a testing and packaging device using the same.

Background

A chip capacitor, also called a single-layer capacitor, is a micro capacitor in which capacitor electrodes are respectively formed on two planes of a thin planar medium. In actual production, a capacitor needs to be taken down from a blue film for scribing, the capacitor is subjected to electrical performance tests of 4 items such as a withstand voltage test (which lasts for more than 5 seconds after a specified voltage is added), an insulation resistance test (which needs a certain charging time if the test is accurate), a capacity test, a loss test and the like, then electrode appearance inspection is carried out, the capacitor with unqualified performance and appearance is removed, and finally the capacitor is put into another blue film or a packaging box. All these items must be handled as far as possible without damaging the entire surface and the corner appearance of the capacitor.

In the prior art, only capacitors in aliasing accumulation form an integrated machine by adopting a vibration disc feeding device, a rotary multi-station testing and appearance detecting device and a boxing or braiding device which are commonly used by conventional electronic components. In addition, the rotary multi-station testing and appearance inspection device adopted in the prior art is in a continuous rotary transposition state when working, each capacitor is sequentially charged and measured, the charging time allocated to each capacitor is very short and is far less than 1 second, so that the accurate insulation resistance test cannot be carried out, and only a prediction method can be adopted for estimation. More seriously, the duration of the voltage application of the withstand voltage test project usually needs several seconds, for example, more than 5 seconds, and if the conventional common method stays for each capacitor for more than 5 seconds at each station, the efficiency is extremely low, the cost is extremely high, and the requirements of high efficiency and low cost of mass production cannot be met.

Disclosure of Invention

The invention provides a chip capacitor testing device, which can test chip capacitors in batches and has high testing efficiency and also provides a testing and packaging device using the testing device.

The technical scheme is as follows: chip electric capacity testing arrangement, it includes the probe card, its characterized in that: the probe card comprises an upper probe card and a lower probe card, more than one probe is arranged on the upper probe card and the lower probe card respectively, a carrying box is arranged between the upper probe card and the lower probe card and used for storing more than one chip capacitor, the carrying box comprises a pore plate and a circuit board which are sequentially arranged from top to bottom, upper electrodes are uniformly arranged above the circuit board, vacuumizing holes are formed in the positions, corresponding to the chip capacitors, of the circuit board, the vacuumizing holes are used for being connected with a vacuumizing mechanism, accommodating holes used for positioning the chip capacitors are formed in the pore plate and corresponding to the upper electrodes, the upper electrodes are further connected with lower electrodes located below the circuit board through conductive through holes, the probes of the upper probe card are used for pressing the chip capacitors, and the probes of the lower probe card are used for pressing the lower electrodes.

It is further characterized in that:

the carrying box also comprises a vacuum bottom plate positioned below the circuit board, a vacuum groove is formed in the vacuum bottom plate, the vacuumizing hole is communicated with the vacuum groove, and the vacuumizing hole is connected with the vacuumizing mechanism through the vacuum bottom plate; and an avoiding groove is formed in the position, corresponding to the lower electrode, of the vacuum bottom plate and is used for avoiding the lower probe.

Chip capacitance test packing plant, it includes gets material station, packing station and transfer mechanism, its characterized in that: get the material station with still be equipped with test station between the packing station, test station is equipped with foretell chip electric capacity testing arrangement, it is used for placing chip electric capacity in carrying the box to get the material station, the packing station is arranged in carrying the box with chip electric capacity and takes out and put on blue membrane or put into the packing carton, it passes through to carry the box the transfer mechanism is in get the material station packing station shift between the test station.

It is further characterized in that:

the material taking station comprises a material taking mechanical arm and a blue film lower thimble, a suction head is mounted on the material taking mechanical arm, the blue film lower thimble is used for ejecting the chip capacitor from the blue film, and the material taking mechanical arm adsorbs the chip capacitor through the suction head and places the chip capacitor into the loading box; the packaging station comprises a blanking mechanical arm and a loading position, wherein a suction head is mounted on the blanking mechanical arm, and a blue film or a packaging box is placed on the loading position;

the testing station comprises a capacitance voltage-withstanding/insulation resistance testing platform and a capacity loss testing platform, and the capacitance voltage-withstanding/insulation resistance testing platform and the capacity loss testing platform are respectively provided with the chip capacitance testing device;

the test station further comprises a chip capacitor upper surface appearance inspection table, and a camera is mounted on the chip capacitor upper surface appearance inspection table;

the capacitance voltage-withstanding/insulation resistance test bench and the capacity loss test bench are respectively provided with the vacuumizing mechanism; the capacitance voltage-withstanding/insulation resistance test bench comprises a direct-current upper probe card and a direct-current lower probe card, and probes on the direct-current upper probe card and probes on the direct-current lower probe card are respectively connected into a voltage-withstanding/insulation resistance test circuit; the capacitance loss test bench comprises an AC upper probe card and an AC lower probe card, and probes of the AC upper probe card and probes of the AC lower probe card are connected with the capacitance test meter;

the alternating current upper probe card or the alternating current lower probe card is provided with a multi-way switch switching channel device, and a probe of the alternating current upper probe card and a probe of the alternating current lower probe card are connected with a capacitance test meter through the multi-way switch switching channel device.

After having adopted such structure, a year box has a plurality of chip electric capacities, chip electric capacity lower extreme electrode and circuit board on electrode contact, thereby can be with the lower extreme electrode and the circuit board bottom electrode connection of chip electric capacity, go up on the probe card a plurality of probes press on the upper end electrode of chip electric capacity simultaneously, a plurality of probes press simultaneously on the lower electrode of carrying the box on the lower probe card, thereby can insert the chip electric capacity and add voltage, the test in the pressurization test circuit, once can pressurize a plurality of electric capacities of test, thereby can realize the batched test of chip electric capacity, the efficiency of software testing is high. When using, can take off chip electric capacity from blue membrane through getting the material station and put into and carry the box, later carry the box and remove to test station through transfer mechanism, test through test station's testing arrangement, rethread transfer mechanism removes packing station department after the test is accomplished, puts qualified electric capacity on blue membrane or puts into the packing carton and packs, unqualified electric capacity is rejected to accomplish chip electric capacity test packaging process, whole process is efficient.

Drawings

FIG. 1 is a schematic top view of a cassette;

FIG. 2 is an enlarged top view of the cassette;

FIG. 3 is a schematic bottom view of the carrier;

FIG. 4 is an enlarged bottom view of the carriage;

FIG. 5 is a schematic diagram of a capacitance voltage/insulation resistance test station;

fig. 6 is a schematic diagram of a capacity loss test stand.

Detailed Description

The chip capacitor testing and packaging device comprises a material taking station, a packaging station and a transferring mechanism, wherein the material taking station is used for placing a chip capacitor in a carrier box, the packaging station is used for taking the chip capacitor out of the carrier box and placing the chip capacitor on a blue film or a packaging box, a testing station is further arranged between the material taking station and the packaging station, and the carrier box is transferred among the material taking station, the packaging station and the testing station through the transferring mechanism. Specifically, chip capacitors are generally positioned on a blue film when not entering the device, the chip capacitors on the blue film are taken out and placed into a loading box through a material taking station, the material taking station can be manually operated, but in order to realize automatic testing, the material taking station preferably comprises a material taking mechanical arm and a blue film lower thimble, the material taking mechanical arm can move up and down and rotate, a suction head is mounted on the material taking mechanical arm, the blue film lower thimble is used for ejecting the chip capacitors from the blue film, and the material taking mechanical arm adsorbs the ejected chip capacitors through the suction head and places the chip capacitors into the loading box; the transfer mechanism can be manually realized, but in order to improve automation, an automatic transfer mechanism can also be adopted, namely, the carrying box is placed on the electric track to be transferred through the electric track, but it needs to be noted that an opening for avoiding a lower probe needs to be formed in the middle of the track, the edge of the carrying box can be connected to a lifting rope to be lifted to a test station through a lifting mechanism, and the carrying box can be clamped to the test station through a mechanical arm; the packaging station can also manually take out the chip capacitor from the carrier box and place the chip capacitor in the blue film or the packaging box, but in order to improve the automation degree, the packaging station preferably comprises a blanking mechanical arm and a loading position, wherein the blanking mechanical arm can move up and down and rotate, a suction head is arranged on the blanking mechanical arm, the blue film or the packaging box is placed on the loading position, and the chip capacitor is taken out from the carrier box and placed on the blue film or the packaging box through the suction head of the blanking mechanical arm.

As shown in fig. 1, 2, 3, and 4, the carrier 1 is used for storing more than one chip capacitor 100, the carrier 1 includes a hole plate 11 and a circuit board 12 that are sequentially disposed from top to bottom, the hole plate 11 is only used for positioning the capacitor and can be replaced with other structures having positioning holes, an array of planar upper electrodes 121 that are independent of each other is uniformly disposed above the circuit board 12, a vacuuming hole 122 is disposed at a position of the circuit board 12 corresponding to the chip capacitor, the vacuuming hole 122 is used for connecting with a vacuuming mechanism (such as a vacuum pump, etc.), the hole plate 11 is made of an insulating material, and has a receiving hole 111 corresponding to the upper electrode 121 for placing the chip capacitor 100 thereon, the upper electrode 121 is further connected with a lower electrode 124 located below the circuit board 12 through a conductive through hole 123, and the lower electrode 124 is used for contacting with a lower probe. The vacuum-pumping mechanism can be directly connected with the vacuum-pumping hole 122 through a pipeline to absorb capacitance, it should be noted that the vacuum-pumping hole 122 and the conductive through hole 123 are avoided from each other to ensure normal operation, the vacuum-pumping hole 122 can be directly opened at the center of the upper electrode 121, and the upper electrode 121 can be connected to the conductive through hole on one side through a circuit. In the above structure, because each vacuuming hole 122 needs to be correspondingly provided with a vacuuming pipeline, the structure is complex, preferably, in order to simplify the structure, the carrying box 1 further comprises a vacuum bottom plate 13 located below the circuit board, a vacuum groove is formed on the vacuum bottom plate 13, the vacuuming hole 131 is communicated with the vacuum groove, and the vacuuming hole 131 is connected with a vacuuming mechanism through the vacuum bottom plate 13; an avoiding groove 131 is formed in the position, corresponding to the lower electrode 124, on the vacuum bottom plate 13, the avoiding groove 131 is used for avoiding the lower probe and exposing the lower electrode 124, the structure is adopted, the vacuum groove is formed in the vacuum bottom plate 13, the vacuumizing hole 131 can be converged into the vacuum groove, then the vacuum groove is connected to a vacuum pump through a pipeline, meanwhile, the vacuum groove needs to be separated from the avoiding groove 131 to avoid influencing vacuumizing, the structure can be simplified, meanwhile, a sealing structure (a sealing ring, sealant coating and the like) can be arranged between the vacuum bottom plate 13 and the circuit board 12 to increase the sealing performance, and the influence of the gap between the two plates on vacuumizing is prevented.

Referring to fig. 5 and 6, the testing apparatus of the testing station includes an upper probe card 2 and a lower probe card 3, wherein more than one probe 4 is respectively disposed on the upper probe card 2 and the lower probe card 3, the probe 4 of the upper probe card 2 is used for pressing on the chip capacitor 100, and the probe 4 of the lower probe card 3 is used for pressing on the lower electrode 124. Specifically, test station can include the withstand voltage of electric capacity insulation resistance testboard, capacity loss testboard, chip electric capacity upper surface outward appearance inspection bench, and chip electric capacity upper surface outward appearance is examined and is installed the camera on the bench.

The capacitance voltage-withstanding/insulation resistance test board and the capacity loss test board are respectively provided with a vacuumizing mechanism; the capacitance voltage-resistance/insulation resistance test bench comprises a direct current upper probe card and a direct current lower probe card, wherein probes on the direct current upper probe card and probes on the direct current lower probe card are respectively connected into a voltage-resistance/insulation resistance test circuit; the capacity loss test bench comprises an AC upper probe card and an AC lower probe card, wherein probes of the AC upper probe card and probes of the AC lower probe card are connected with a capacitance test meter; preferably, the alternating current upper probe card or the alternating current lower probe card is provided with a multi-way switch switching channel device, probes of the alternating current upper probe card and probes of the alternating current lower probe card are connected with a capacitance test meter through the multi-way switch switching channel device, the probes are pressed on the surfaces of a plurality of chip capacitors in the carrying box in a static mode through the array plane probe to carry out withstand voltage, insulation resistance, capacity and loss parameter tests, and then the appearance inspection is carried out on a camera for the chip capacitors in the carrying box at another station.

When the device is used for testing the chip capacitance, when the suction head is moved to the position above the chip capacitance on the blue film by the material taking mechanical arm, the thimble jacks up one chip capacitance slightly from the blue film, so that the chip capacitance is separated from the blue film to the maximum extent, the material taking mechanical arm descends to enable the suction head to be close to the chip capacitance, then the suction head sucks up the chip capacitance, then the material taking mechanical arm ascends and rotates to the loading position of the chip capacitance testing loading box, and the material taking mechanical arm descends to load the capacitance on the suction head into the loading box. And the material taking mechanical arm is lifted again and rotates to the position above the blue film to suck the next chip capacitor. The loading box is displaced by a capacitor slot position, and an empty slot position is used for preparing to receive the next chip capacitor to be loaded into the box.

After the loading of the loading box is finished, transferring the loading box to a testing station through an automatic transfer mechanism, sequentially arranging a capacitance voltage-withstanding/insulation resistance testing table, a capacity loss testing table and a chip capacitance upper surface appearance inspection table, wherein the first two testing tables are respectively provided with a vacuum workpiece table which is provided with a vacuum pipeline and communicated with the end part of a vacuum groove at the bottom of the capacitance loading box arranged on the vacuum workpiece table, and negative pressure is generated at all vacuuming holes 122 at the upper part of the loading box through the vacuum groove in a vacuum bottom plate at the lower part of the loading box so as to adsorb the chip capacitance arranged on an upper electrode 121 on the upper electrode; a direct current upper probe card and a direct current lower probe card are respectively arranged above and below the capacitance voltage-resistant/insulation resistance test platform, wherein the diameter of a lower probe on the lower probe card 3 is smaller than that of the avoidance groove 131 on the vacuum bottom plate 13 of the loading box. When the lower probe passes through the avoiding groove 131 to contact the lower electrode 124, the probe 4 does not touch the wall of the avoiding groove 131. Thus, the lower probe is connected with the lower electrode of the chip capacitor through the probe contact electrode, and the upper probe card moves downwards before the lower probe card rises to contact the lower electrode at the bottom of the loading box, so that the probe is pressed on the upward surface of each chip capacitor in the loading box. At this point, all capacitors in the carrier can be tested one by simultaneously loading a plurality of capacitors with the voltage required for the withstand voltage test for a desired time, such as 5 seconds or more, then loading all capacitors with the charging voltage required for the insulation resistance test until the capacitors are substantially full, and then testing the insulation resistance of each chip capacitor in the carrier one by one. The testing speed achieved by the method is far higher than that of the prior testing mode.

The probe card is internally provided with a multi-way switch switching channel device which is connected with a capacitance test meter capable of measuring the capacity/loss. Thus, after the upper and lower probe arrays are connected with the chip capacitors in the carrier box, the test meter will sequentially test the capacity and loss of each chip capacitor in the carrier box. Because each chip capacitor in the loading box is sucked on the capacitor contact electrode of the loading box by negative pressure on the vacuum workpiece table, when the probe rises after the test is finished, the chip capacitor cannot be adhered by the probe and is carried away from the loading box.

When carrying the box and being moved to chip electric capacity upper surface outward appearance inspection bench, carry the box top and be equipped with the camera that can two-dimentional plane remove, the camera will be to carrying each chip electric capacity in the box upward surface to observe the inspection one by one.

Afterwards can accomplish the test to carry the box and remove to the packing station, including a plurality of chip classification packing platforms, every packing platform has a unloading arm and loads the position, loads and has placed blue membrane or packing carton on the position. The loading box is moved to each packaging table, chip capacitors in the type in the loading box are sucked up one by one from the loading box by the blanking mechanical arm according to the appointed type of the packaging table, the chip capacitors are moved to corresponding loading positions and placed on a blue film or in a packaging box, and unqualified capacitors are removed and enter a defective product collecting box.

Chip capacitance test packagine machine of this scheme of use preparation, can be under the condition that does not harm chip capacitance surface electrode, get the material from blue membrane with higher speed completion, need withstand voltage and the insulation resistance test of charging more than 5 seconds, the loss test, the outward appearance is examined and categorised packing, realize 3 to 4 chip capacitance's per second intermediate speed test equipment for packing more easily, also can realize 6 to 8 chip capacitance's per second high-speed equipment, the same functional equipment of prior art is adopted far away, higher performance has been realized with reasonable cost, actual production demand has been satisfied betterly.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. Chip electric capacity testing arrangement, it includes the probe card, its characterized in that: the probe card comprises an upper probe card and a lower probe card, more than one probe is arranged on the upper probe card and the lower probe card respectively, a carrying box is arranged between the upper probe card and the lower probe card and used for storing more than one chip capacitor, the carrying box comprises a pore plate and a circuit board which are sequentially arranged from top to bottom, upper electrodes are uniformly arranged above the circuit board, vacuumizing holes are formed in the positions, corresponding to the chip capacitors, of the circuit board, the vacuumizing holes are used for being connected with a vacuumizing mechanism, accommodating holes used for positioning the chip capacitors are formed in the pore plate and corresponding to the upper electrodes, the upper electrodes are further connected with lower electrodes located below the circuit board through conductive through holes, the probes of the upper probe card are used for pressing the chip capacitors, and the probes of the lower probe card are used for pressing the lower electrodes.

2. The chip capacitance test device according to claim 1, wherein: the carrying box also comprises a vacuum bottom plate positioned below the circuit board, a vacuum groove is formed in the vacuum bottom plate, the vacuumizing hole is communicated with the vacuum groove, and the vacuumizing hole is connected with the vacuumizing mechanism through the vacuum bottom plate; and an avoiding groove is formed in the position, corresponding to the lower electrode, of the vacuum bottom plate and is used for avoiding the lower probe.

3. Chip capacitance test packing plant, it includes gets material station, packing station and shifts mechanism, its characterized in that: the chip capacitor testing device is characterized in that a testing station is further arranged between the material taking station and the packaging station, the testing station is provided with the chip capacitor testing device according to any one of claims 1-2, the material taking station is used for placing a chip capacitor in a loading box, the packaging station is used for taking the chip capacitor out of the loading box and placing the chip capacitor on a blue film or a packaging box, and the loading box is transferred among the material taking station, the packaging station and the testing station through the transferring mechanism.

4. The chip capacitance test packaging apparatus of claim 3, wherein: the material taking station comprises a material taking mechanical arm and a blue film lower thimble, a suction head is mounted on the material taking mechanical arm, the blue film lower thimble is used for ejecting the chip capacitor from the blue film, and the material taking mechanical arm adsorbs the chip capacitor through the suction head and places the chip capacitor into the carrying box; the packaging station comprises a blanking mechanical arm and a loading position, the blanking mechanical arm is provided with a suction head, and the loading position is provided with a blue film or a packaging box.

5. The chip capacitance test packaging apparatus of claim 3, wherein: the testing station comprises a capacitor voltage-withstanding/insulation resistance testing platform and a capacity loss testing platform, and the capacitor voltage-withstanding/insulation resistance testing platform and the capacity loss testing platform are respectively provided with the chip capacitor testing device.

6. The chip capacitance test packaging apparatus of claim 5, wherein: the test station further comprises a chip capacitor upper surface appearance inspection table, and a camera is mounted on the chip capacitor upper surface appearance inspection table.

7. The chip capacitance test packaging apparatus of claim 5, wherein: the capacitance voltage-withstanding/insulation resistance test bench and the capacity loss test bench are respectively provided with the vacuumizing mechanism; the capacitance voltage-withstanding/insulation resistance test bench comprises a direct-current upper probe card and a direct-current lower probe card, and probes on the direct-current upper probe card and probes on the direct-current lower probe card are respectively connected into a voltage-withstanding/insulation resistance test circuit; the capacity loss test bench comprises an AC upper probe card and an AC lower probe card, and probes of the AC upper probe card and probes of the AC lower probe card are connected with the capacitance test meter.

8. The chip capacitance test packaging apparatus of claim 7, wherein: the alternating-current upper probe card or the alternating-current lower probe card is provided with a multi-way switch switching channel device, and a probe of the alternating-current upper probe card and a probe of the alternating-current lower probe card are connected with the capacitance test meter through the multi-way switch switching channel device.