CN115348725A - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure comprises a reconfiguration circuit structure layer, an additional layer circuit structure layer and a connection structure layer. The reconfiguration line structure layer comprises a plurality of first connection pads. The build-up circuit structure layer is configured at one side of the reconfiguration circuit structure layer and comprises a plurality of second connecting pads. The line width and the line distance of the reconfiguration line structure layer are smaller than those of the build-up line structure layer. The connection structure layer is configured between the reconfiguration circuit structure layer and the build-up circuit structure layer and comprises a base material and a plurality of conductive adhesive columns penetrating through the base material. The first connecting pads are electrically connected with the second connecting pads through the conductive adhesive columns respectively. The first connecting pad and the second connecting pad are respectively embedded into two opposite surfaces of the substrate. The circuit board structure of the invention does not need to use solder and primer, can reduce the cost and has better structure reliability.

Description

Circuit board structure and manufacturing method thereof

Technical Field

The present disclosure relates to circuit boards, and particularly to a circuit board structure and a method for fabricating the same.

Background

Generally, two circuit boards with wires or conductive structures are connected by solder joints (solder joints), and underfill is used to fill the space between the two substrates to seal the solder joints. However, in the high-temperature reflow process of the solder, the circuit board with a larger area size cannot release stress, and is easy to warp greatly, thereby reducing the assembly yield between the two circuit boards.

Disclosure of Invention

The invention aims at a circuit board structure, does not need to use solder and primer, can reduce the cost and has better structure reliability.

The invention also aims at a manufacturing method of the circuit board structure, which is used for manufacturing the circuit board structure.

According to an embodiment of the present invention, a circuit board structure includes a reconfiguration line structure layer, a build-up line structure layer, and a connection structure layer. The reconfiguration line structure layer comprises a plurality of first connection pads. The build-up circuit structure layer is configured at one side of the reconfiguration circuit structure layer and comprises a plurality of second connecting pads. The line width and the line distance of the reconfiguration line structure layer are smaller than those of the build-up line structure layer. The connection structure layer is configured between the reconfiguration circuit structure layer and the build-up circuit structure layer and comprises a base material and a plurality of conductive adhesive columns penetrating through the base material. The first connecting pads are electrically connected with the second connecting pads through the conductive adhesive columns respectively. The first connecting pad and the second connecting pad are respectively embedded into two opposite surfaces of the substrate.

In the circuit board structure according to an embodiment of the present invention, the redistribution layer further includes a plurality of dielectric layers, at least one redistribution, a plurality of conductive vias, and a plurality of chip pads. The dielectric layer and the at least one redistribution line are alternately arranged. The first connecting pad, the redistribution circuit and the chip connecting pad are electrically connected through the conductive through hole. The outermost dielectric layers are the first dielectric layer and the second dielectric layer. The chip bonding pad is embedded in the first dielectric layer, the first bonding pad is located on the second dielectric layer, and the second dielectric layer directly contacts with the substrate of the connection structure layer.

In the circuit board structure according to the embodiment of the present invention, the material of the dielectric layer includes a photosensitive dielectric material or Ajinomoto Build-up Film (ABF).

In the circuit board structure according to an embodiment of the present invention, the circuit board structure further includes a surface treatment layer disposed on the chip pad of the redistribution structure layer. The material of the surface treatment layer includes Nickel palladium Immersion Gold (ENEPIG), organic solder resist (OSP) or Electroless Nickel Immersion Gold (ENIG).

In the circuit board structure according to an embodiment of the invention, the circuit board structure further includes a solder mask layer disposed on a surface of the build-up circuit structure layer relatively far from the connection structure layer, and covering a portion of the build-up circuit structure layer to define a plurality of solder ball pads.

According to an embodiment of the invention, a method of manufacturing a circuit-board structure comprises the following steps. A redistribution layer including a plurality of first connection pads is provided. Providing a connection structure layer comprising a substrate and a plurality of conductive adhesive posts penetrating through the substrate, wherein the connection structure layer is in a B-stage state. And providing a build-up circuit structure layer comprising a plurality of second connecting pads, wherein the line width and the line distance of the reconfiguration circuit structure layer are smaller than those of the build-up circuit structure layer. And laminating the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer so that the connection structure layer is positioned between the reconfiguration circuit structure layer and the build-up circuit structure layer. The first connecting pads are electrically connected with the second connecting pads through the conductive adhesive columns respectively, the first connecting pads and the second connecting pads are embedded into two opposite surfaces of the substrate respectively, and the connecting structure layer formed by the substrate and the conductive adhesive columns is changed from a B-stage state to a C-stage state.

In the method for manufacturing a circuit board structure according to an embodiment of the present invention, the step of providing the redistribution structure layer including the first connection pad includes the following steps. A temporary substrate and a release film on the temporary substrate are provided. An insulating layer is formed on the release film. A core substrate is provided on the insulating layer. The core substrate comprises a core layer, a first copper foil layer and a second copper foil layer, wherein the first copper foil layer and the second copper foil layer are positioned on two opposite sides of the core layer. The second copper foil layer is located between the core layer and the insulating layer. And forming a plurality of chip bonding pads on the first copper foil layer. A first dielectric layer is formed on the first copper foil layer. The first dielectric layer covers the chip pad and has a plurality of first openings, and the first openings expose a portion of the chip pad. At least one redistribution line and a plurality of first conductive vias are formed. The redistribution circuit is disposed on the first dielectric layer, and the first conductive through holes are respectively located in the first openings and electrically connect the redistribution circuit and the chip bonding pads. Forming a second dielectric layer on the redistribution circuit. The second dielectric layer has a plurality of second openings exposing portions of the redistribution lines. And forming a first connecting pad and a plurality of second conductive through holes. The first connecting pad is disposed on the second dielectric layer, and the second conductive through holes are respectively disposed in the second openings and electrically connect the redistribution circuit and the first connecting pad. The temporary substrate and the release film are removed to expose the insulating layer.

In the method for fabricating a circuit board structure according to an embodiment of the present invention, the material of the first dielectric layer and the material of the second dielectric layer include a photosensitive dielectric material or an amortism stacked film.

In the method for manufacturing a circuit board structure according to an embodiment of the present invention, after the laminating the reconfiguration circuit structure layer, the connection structure layer, and the build-up circuit structure layer, the method further includes: the insulating layer and the core substrate are removed to expose the first dielectric layer of the redistribution layer. Forming a surface treatment layer on the chip bonding pad of the re-configuration circuit structure layer. The material of the surface treatment layer comprises nickel palladium immersion gold, organic solderability preservative or electroless nickel immersion gold.

In the method for manufacturing a circuit board structure according to an embodiment of the present invention, before the step of laminating the reconfiguration circuit structure layer, the connection structure layer, and the build-up circuit structure layer, a solder mask layer is formed on a surface of the build-up circuit structure layer relatively far from the connection structure layer. The solder mask layer covers a part of the build-up circuit structure layer to define a plurality of solder ball pads.

Based on the above, in the method for manufacturing a circuit board structure of the present invention, the circuit board structure is formed by laminating the reconfiguration circuit structure layer, the connection structure layer, and the build-up circuit structure layer, wherein the first connection pads of the reconfiguration circuit structure layer are electrically connected to the second connection pads of the build-up circuit structure layer through the conductive adhesive posts of the connection structure layer, and the first connection pads and the second connection pads are embedded in the two opposite surfaces of the substrate of the connection structure layer. Therefore, the manufacturing method of the circuit board structure of the invention does not need to use solder and primer, and can effectively reduce the manufacturing cost of the circuit board structure. In addition, because no solder is used, the joint yield among the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer can be effectively improved, and the structural reliability of the circuit board structure is further improved.

Drawings

Fig. 1A to fig. 1P are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention;

fig. 2 is a schematic cross-sectional view of a chip disposed on the circuit board structure of fig. 1P.

Description of the reference numerals

10: a temporary substrate;

12, a release film;

20, an insulating layer;

30 a core substrate;

32, a core layer;

34 a first copper foil layer;

36 a second copper foil layer;

110, reconfiguring the circuit structure layer;

112, chip connecting pad;

114 a first dielectric layer;

reconfiguration circuitry 116;

118 a second dielectric layer;

119 first connecting pad;

120, connecting the structural layers;

122, a base material;

125, conductive adhesive columns;

130, adding a layer circuit structure layer;

131, a surface;

132, a second connecting pad;

140, a surface treatment layer;

150, a solder mask layer;

200, a chip;

210, solder;

300, a chip packaging structure;

h1, a first opening;

h2, a second opening;

m is a metal layer;

p1, P2, patterning the photoresist layer;

s, a seed layer;

t1, a first conductive through hole;

t2, a second conductive through hole;

and SP is a solder ball connecting pad.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1A to fig. 1P are schematic cross-sectional views illustrating a method for manufacturing a circuit board structure according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view of a chip disposed on the circuit board structure of fig. 1P. Referring to fig. 1A, a temporary substrate 10 and a releasing film 12 on the temporary substrate 10 are provided. Here, the temporary substrate 10 is made of, for example, glass or plastic, which is a substrate without a circuit.

Next, referring to fig. 1B, an insulating layer 20 is formed on the releasing film 12, wherein the material of the insulating layer 20 is, for example, an ajinomoto stacked film (ABF), but not limited thereto.

Next, referring to fig. 1B, a core substrate 30 is provided on the insulating layer 20, wherein the core substrate 30 includes a core layer 32, and a first copper foil layer 34 and a second copper foil layer 36 located at two opposite sides of the core layer 32. In one embodiment, the surface of the first copper foil layer 34 may be subjected to a Chemical-mechanical polishing (Chemical-mechanical polishing) process to planarize the surface. Here, the second copper foil layer 36 is located between the core layer 32 and the insulating layer 20.

Next, referring to fig. 1C, a patterned photoresist layer P1 is formed on the first copper foil layer 34, wherein the patterned photoresist layer P1 exposes a portion of the first copper foil layer 34.

Next, referring to fig. 1D, a plurality of chip pads 112 are formed on the first copper foil layer 34, wherein the chip pads 112 are located on the first copper foil layer 34 exposed by the patterned photoresist layer P1. Here, a method of forming the chip pad 112 is, for example, electroplating.

Next, referring to fig. 1D and fig. 1E, the patterned photoresist layer P1 is removed to expose the first copper foil layer 34.

Next, referring to fig. 1F, a first dielectric layer 114 is formed on the first copper foil layer 34, wherein the first dielectric layer 114 covers the chip pad 112 and has a plurality of first openings H1, and a portion of the chip pad 112 is exposed by the first openings H1. Here, the material of the first dielectric layer 114 is, for example, a photosensitive dielectric material or an ajinomoto stacked film (ABF).

Next, referring to fig. 1G, a seed layer S is formed on the first dielectric layer 114, wherein the seed layer S covers the first dielectric layer 114 and the inner wall of the first opening H1 and is connected to the chip pad 112.

Next, referring to fig. 1H, a patterned photoresist layer P2 is formed on the seed layer S, wherein the patterned photoresist layer P2 exposes a portion of the seed layer S.

Next, referring to fig. 1I, a metal layer M is formed on the seed layer S exposed by the patterned photoresist layer P2, wherein the metal layer M is formed by, for example, electroplating.

Next, referring to fig. 1J, the patterned photoresist layer P2 and the seed layer S thereunder are removed to form the redistribution line 116 and the first conductive via T1. Here, the redistribution circuit 116 is disposed on the first dielectric layer 114, and the first conductive vias T1 are disposed in the first openings H1 and electrically connect the redistribution circuit 116 and the chip pads 112, respectively.

Then, the steps shown in fig. 1F to fig. 1J may be repeated to form the desired number of layers of the redistribution lines 116 and the first conductive vias T1, wherein the number of times of repetition may be determined according to the user's requirements.

Next, referring to fig. 1K, a second dielectric layer 118 is formed on the redistribution circuit 116, wherein the second dielectric layer 118 has a plurality of second openings H2, and the second openings H2 expose a portion of the redistribution circuit 116. Here, the material of the second dielectric layer 118 is, for example, a photosensitive dielectric material or an ajinomoto stacked film (ABF).

Next, referring to fig. 1K again, in the same steps as fig. 1G to fig. 1J, a first connection pad 119 and a plurality of second conductive vias T2 are formed. Here, the first connection pads 119 are disposed on the second dielectric layer 118, and the second conductive vias T2 are respectively located in the second openings H2 and electrically connect the redistribution lines 116 and the first connection pads 119. At this point, the redistribution structure layer 110 including the first connection pad 119 is completed. Here, the rcf layer 110 is embodied as a rcf layer with fine lines.

Next, referring to fig. 1K and fig. 1L, the temporary substrate 10 and the release film 12 are removed to expose the insulating layer 20.

Next, referring to fig. 1M, a connection structure layer 120 including a substrate 122 and a plurality of conductive adhesive pillars 125 penetrating through the substrate 122 is provided, wherein the connection structure layer 120 is in a B-stage state. Here, the material of the substrate 122 is, for example, prepreg (PP), and the material of the conductive adhesive pillar 125 is, for example, conductive metal adhesive, and is manufactured by coating with a printing method (printing), so that the conductive adhesive has the effects of electrical conductivity and thermal conductivity, and is suitable for bonding with any metal material.

Next, referring to fig. 1M again, a build-up circuit structure layer 130 including a plurality of second connection pads 132 is provided, wherein the line width and the line distance of the redistribution structure layer 110 are smaller than those of the build-up circuit structure layer 130. At this time, the solder mask layer 150 is formed on the surface 131 of the build-up circuit structure layer 130 relatively far from the connection structure layer 120. The solder mask layer 150 covers a portion of the build-up circuit structure layer 130 to define a plurality of solder ball pads SP. Here, the build-up line structure layer 130 is embodied as a multilayer circuit board.

It should be noted that the order of providing the redistribution structure layer 110, the connection structure layer 120, and the build-up circuit structure layer 130 is not limited in this embodiment.

Next, referring to fig. 1N, the redistribution structure layer 110, the connection structure layer 120, and the build-up circuit structure layer 130 are pressed together by a hot press, so that the connection structure layer 120 is located between the redistribution structure layer 110 and the build-up circuit structure layer 130. At this time, the insulating layer 20 and the core substrate 30 are still on the redistribution layer 110. In particular, the first connecting pads 119 are electrically connected to the second connecting pads 132 through the conductive adhesive pillars 125, and the first connecting pads 119 and the second connecting pads 132 are embedded in two opposite surfaces of the substrate 122, respectively. During the thermal compression, the redistribution structure layer 110 and the build-up circuit structure layer 130 directly contact the substrate 122 of the connection structure layer 120 and press the conductive adhesive pillar 125 to deform. At this time, the substrate 122 and the conductive adhesive pillar 125 are not completely cured and have flexibility and adhesion, so that the redistribution circuit structure layer 110 and the build-up circuit structure layer 130 can be bonded, and the first connection pad 119 and the second connection pad 132 are respectively extruded into the substrate 122 and embedded into the substrate 122. After the pressing and curing, the substrate 122 and the conductive adhesive pillar 125 of the connection structure layer 120 are transformed from the B-stage state to the C-stage state.

Then, referring to fig. 1N and fig. 1O, the insulating layer 20 and the core substrate 30 are removed to expose the first dielectric layer 112 of the redistribution layer 110.

Finally, referring to fig. 1P, a surface treatment layer 140 is formed on the chip pad 112 of the redistribution structure layer 110. Here, the material of the surface treatment layer 140 is, for example, nickel palladium immersion gold (ENEPIG), organic Solderability Preservative (OSP), or Electroless Nickel Immersion Gold (ENIG). Thus, the circuit board structure 100 is completed.

Structurally, referring to fig. 1P again, in the present embodiment, the circuit board structure 100 includes a redistribution structure layer 110, a build-up circuit structure layer 130, and a connection structure layer 120. The redistribution layer 110 includes a first connection pad 119. The build-up circuit structure layer 130 is disposed on one side of the redistribution structure layer 110 and includes a second connecting pad 132. The line width and line distance of the reconfiguration line structure layer 110 are smaller than those of the build-up line structure layer 130. The connection structure layer 120 is disposed between the redistribution structure layer 110 and the build-up circuit structure layer 130, and includes a substrate 122 and a conductive adhesive pillar 125 penetrating through the substrate 122. The first connecting pads 119 are electrically connected to the second connecting pads 132 through the conductive adhesive pillars 125, respectively. The first connecting pad 119 and the second connecting pad 132 are respectively embedded into two opposite surfaces of the substrate 122.

In detail, the redistribution structure layer 110 of the embodiment further includes a chip pad 112, a first dielectric layer 114, a redistribution 116, a second dielectric layer 118, a first conductive via T1, and a second conductive via T2. The first dielectric layer 114, the redistribution line 116, and the second dielectric layer 118 are in an alternating stacked configuration. The first connection pad 119, the redistribution circuit 116 and the chip pad 112 are electrically connected through the first conductive via T1 and the second conductive via T2. The chip pad 112 is embedded in the first dielectric layer 114, and the first connection pad 119 is located on the second dielectric layer 118, and the second dielectric layer 118 directly contacts the substrate 122 of the connection structure layer 120.

In addition, the circuit board structure of the present embodiment further includes a surface treatment layer 140 and a solder mask layer 150. The surface treatment layer 140 is disposed on the chip pad 112 of the redistribution structure layer 110, wherein the material of the surface treatment layer 140 is nickel palladium immersion gold (ENEPIG), organic Solderability Preservative (OSP), or Electroless Nickel Immersion Gold (ENIG). The solder mask layer 150 is disposed on the surface 131 of the build-up circuit structure layer 130 relatively far from the connection structure layer 120, and covers a portion of the build-up circuit structure layer 130 to define the solder ball pad SP.

In short, since the circuit board structure 100 is formed by laminating the redistribution structure layer 110, the connection structure layer 120 and the build-up circuit structure layer 130, solder and underfill are not required, and the manufacturing cost of the circuit board structure 100 can be effectively reduced. In addition, since no solder joints (solder joints) are used, the joint yield among the redistribution structure layer 110, the connection structure layer 120, and the build-up circuit structure layer 130 can be effectively improved, thereby improving the structural reliability of the circuit board structure 100 of the embodiment.

In application, referring to fig. 2, the chip 200 may be electrically connected to the chip pad 112 of the redistribution structure layer 110 through the solder 210 to form the chip package structure 300.

In summary, in the method for manufacturing a circuit board structure of the present invention, the circuit board structure is formed by laminating the redistribution structure layer, the connection structure layer, and the build-up circuit structure layer, wherein the first connection pads of the redistribution structure layer are electrically connected to the second connection pads of the build-up circuit structure layer through the conductive adhesive posts of the connection structure layer, and the first connection pads and the second connection pads are embedded in two opposite surfaces of the substrate of the connection structure layer. Therefore, the manufacturing method of the circuit board structure of the invention does not need to use solder joints (solder joints) and primer, and can effectively reduce the manufacturing cost of the circuit board structure. In addition, because no solder is used, the joint yield among the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer can be effectively improved, and the structural reliability of the circuit board structure is further improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A circuit board structure, comprising:

the reconfiguration line structure layer comprises a plurality of first connecting pads;

the build-up circuit structure layer is configured at one side of the reconfiguration circuit structure layer and comprises a plurality of second connecting pads, wherein the line width and the line distance of the reconfiguration circuit structure layer are smaller than those of the build-up circuit structure layer; and

and the connecting structure layer is configured between the reconfiguration circuit structure layer and the build-up circuit structure layer and comprises a substrate and a plurality of conductive adhesive columns penetrating through the substrate, wherein the plurality of first connecting pads are electrically connected with the plurality of second connecting pads through the plurality of conductive adhesive columns respectively, and the plurality of first connecting pads and the plurality of second connecting pads are embedded into two opposite surfaces of the substrate respectively.

2. The circuit board structure of claim 1, wherein the redistribution layer further comprises a plurality of dielectric layers, at least one redistribution trace, a plurality of conductive vias, and a plurality of chip pads, the dielectric layers and the at least one redistribution trace are alternately disposed, the first connection pads, the at least one redistribution trace, and the chip pads are electrically connected through the conductive vias, the outermost dielectric layers of the dielectric layers are a first dielectric layer and a second dielectric layer, the chip pads are embedded in the first dielectric layer, the first connection pads are located on the second dielectric layer, and the second dielectric layer directly contacts the substrate of the redistribution layer.

3. The circuit board structure of claim 2, wherein the material of the plurality of dielectric layers comprises a photosensitive dielectric material or an ajinomoto stacked film.

4. The circuit board structure according to claim 1, further comprising:

and the surface treatment layer is configured on the chip connection pads of the reconfiguration circuit structure layer, wherein the material of the surface treatment layer comprises nickel palladium immersion gold, organic solderability preservative or electroless nickel immersion gold.

5. The circuit board structure according to claim 1, further comprising:

and the solder mask layer is configured on the surface of the layer-adding circuit structure layer relatively far away from the connecting structure layer, and covers part of the layer-adding circuit structure layer to define a plurality of solder ball connecting pads.

6. A method for manufacturing a circuit board structure is characterized by comprising the following steps:

providing a reconfiguration line structure layer comprising a plurality of first connecting pads;

providing a connecting structure layer comprising a substrate and a plurality of conductive adhesive posts penetrating through the substrate, wherein the connecting structure layer is in a B-stage state;

providing a build-up circuit structure layer comprising a plurality of second connecting pads, wherein the line width and the line distance of the reconfiguration circuit structure layer are smaller than those of the build-up circuit structure layer; and

and pressing the reconfiguration circuit structure layer, the connection structure layer and the build-up circuit structure layer to enable the connection structure layer to be positioned between the reconfiguration circuit structure layer and the build-up circuit structure layer, wherein the plurality of first connection pads are electrically connected with the plurality of second connection pads through the plurality of conductive adhesive columns respectively, the plurality of first connection pads and the plurality of second connection pads are embedded into two opposite surfaces of the substrate respectively, and the connection structure layer is converted into a C-stage state from the B-stage state.

7. The method of claim 6, wherein the step of providing the rcf structure layer including the first connection pads comprises:

providing a temporary substrate and a release film on the temporary substrate;

forming an insulating layer on the release film;

providing a core substrate on the insulating layer, the core substrate including a core layer and a first copper foil layer and a second copper foil layer on opposite sides of the core layer, the second copper foil layer being between the core layer and the insulating layer;

forming a plurality of chip bonding pads on the first copper foil layer;

forming a first dielectric layer on the first copper foil layer, wherein the first dielectric layer covers the chip pads and is provided with a plurality of first openings, and the chip pads are partially exposed by the first openings;

forming at least one redistribution circuit and a plurality of first conductive vias, wherein the at least one redistribution circuit is disposed on the first dielectric layer, and the plurality of first conductive vias are respectively located in the plurality of first openings and electrically connect the at least one redistribution circuit and the plurality of chip pads;

forming a second dielectric layer on the at least one redistribution line, the second dielectric layer having a plurality of second openings exposing a portion of the at least one redistribution line;

forming a plurality of first connection pads and a plurality of second conductive vias, wherein the plurality of first connection pads are disposed on the second dielectric layer, and the plurality of second conductive vias are respectively located in the plurality of second openings and electrically connect the at least one redistribution line and the plurality of first connection pads; and

removing the temporary substrate and the release film to expose the insulating layer.

8. The method as claimed in claim 7, wherein the material of the first dielectric layer and the material of the second dielectric layer comprise photosensitive dielectric material or ajinomoto stacked film.

9. The method of fabricating a circuit board structure according to claim 7, further comprising, after the laminating the reconfiguration line structure layer, the connection structure layer, and the build-up line structure layer:

removing the insulating layer and the core substrate to expose the first dielectric layer of the redistribution layer; and

forming a surface treatment layer on the chip bonding pads of the reconfiguration line structure layer, wherein the material of the surface treatment layer comprises nickel palladium immersion gold, organic solder resist or electroless nickel immersion gold.

10. The method as claimed in claim 6, further comprising, before laminating the redistribution structure layer, the connection structure layer and the build-up circuit structure layer:

and forming a solder mask layer on the surface of the build-up circuit structure layer relatively far away from the connecting structure layer, wherein the solder mask layer covers part of the build-up circuit structure layer to define a plurality of solder ball pads.

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