CN115346946A - Stack package structure and manufacturing method thereof - Google Patents

Stack package structure and manufacturing method thereof Download PDF

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Publication number
CN115346946A
CN115346946A CN202211124804.3A CN202211124804A CN115346946A CN 115346946 A CN115346946 A CN 115346946A CN 202211124804 A CN202211124804 A CN 202211124804A CN 115346946 A CN115346946 A CN 115346946A
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solder
substrate
initial
connection
bonding
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CN202211124804.3A
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Chinese (zh)
Inventor
吕开敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211124804.3A priority Critical patent/CN115346946A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175—Material
    • H01L2224/17505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

Abstract

The embodiment of the disclosure provides a stacked package structure and a manufacturing method thereof, wherein the stacked package structure comprises: a substrate and a plurality of device layers stacked on the substrate; the first connecting part comprises first solder connecting parts arranged among the device layers and between the substrate and the device layers, and the first solder connecting parts are electrically connected with the device layers and the substrate; and the second connecting part comprises second solder connecting parts which are arranged between the device layers and between the substrate and the device layers and are not electrically connected with the device layers and the substrate, wherein the connecting part of at least one layer has a first doping element, and the content of the first doping element in the first solder connecting part is less than that of the first doping element in the second solder connecting part, so that the melting temperature of the first solder connecting part is greater than that of the second solder connecting part, and thus, the problem of poor bonding of at least part of the connecting parts can be solved.

Description

Stack package structure and manufacturing method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor packaging, and in particular relates to a stacked package structure and a manufacturing method of the stacked package structure.
Background
With the development of semiconductor technology, the size of a semiconductor device tends to be high in integration level and multifunctional, the existing 2D packaging is difficult to meet the technical requirements, and the 3D packaging has the characteristics of small size and light weight, can meet the development requirements of the semiconductor technology and is widely applied. Bonding is a key process for realizing 3D packaging, wherein the bonding technology currently applied to 3D packaging includes a Thermal Compression Bonding (TCB) process, the bonding effect of the Thermal Compression bonding process is affected by the uniformity of temperature distribution when chips are stacked, and the non-uniform temperature distribution between the chips during bonding directly leads to poor bonding.
Disclosure of Invention
The embodiment of the disclosure provides a stacked package structure and a manufacturing method of the stacked package structure, which are at least beneficial to solving the problem of poor bonding of partial regions.
According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a package on package structure, including: a substrate and a plurality of device layers stacked on the substrate; the connecting part comprises a first connecting part and a second connecting part, the first connecting part comprises first solder connecting parts arranged between the device layers and between the substrate and the device layers, the first solder connecting parts are electrically connected with the device layers and the substrate, the second connecting part comprises second solder connecting parts arranged between the device layers and between the substrate and the device layers, the second solder connecting parts are not electrically connected with the device layers and the substrate, the first solder connecting parts and the second solder connecting parts of at least one layer have first doping elements, and the content of the first doping elements in the first solder connecting parts is smaller than that of the first doping elements in the second solder connecting parts.
In some embodiments, the first connection portion further comprises an electrical connection structure extending through at least one of the device layers, the electrical connection structure being connected to the first solder connection portion, the electrical connection structure having a melting temperature greater than a melting temperature of the first solder connection portion.
In some embodiments, the plurality of device layers stacked on the substrate include a bottom device layer, and the second solder connection portion disposed between the bottom device layer and the substrate has a content of the first doping element greater than a content of the first doping element of the second solder connection portion between the other device layers.
In some embodiments, the device layer further comprises a top device layer in the connection portion disposed between the top device layer and the adjacent device layer, and the content of the first doping element in the first solder connection portion and the content of the first doping element in the second solder connection portion are the same or different.
In some embodiments, a content of the first doping element of the second solder connection is greater than a content of the first doping element of the first solder connection in the plurality of layers of the connection adjacent to the substrate.
In some embodiments, a content of the first doping element of the second solder connection is greater than a content of the first doping element of the first solder connection for the connections of all layers.
In some embodiments, a difference between the content of the first doping element of the first solder connection and the content of the first doping element of the second solder connection ranges from-5.5% to-1.5%.
In some embodiments, the first doping element content of the first solder connection is 0.5% to 2%, and the first doping element content of the second solder connection is 3.5% to 6%.
In some embodiments, the first solder connection has a largest first dimension and the second solder connection has a largest second dimension in a direction parallel to the substrate, the first dimension being smaller than the second dimension.
In some embodiments, the first doping element comprises one or more of silver, bismuth, indium, palladium.
In some embodiments, the first doping element is silver; the content of the first doping element in the first solder connection part is 0.5% -2%, and the content of the first doping element in the second solder connection part is 3.5% -6%.
According to some embodiments of the present disclosure, there is also provided in another aspect of the embodiments of the present disclosure a method for manufacturing a package on package structure, including: providing a substrate and a plurality of device layers which are arranged on the substrate in a stacking mode, wherein initial connecting parts are formed between the device layers of adjacent layers, the initial connecting parts of the same layer comprise first initial connecting parts and second initial connecting parts, the first initial connecting parts comprise first initial solder connecting parts between the device layers and between the substrate and the device layers, the second initial connecting parts comprise second initial solder connecting parts arranged between the device layers and between the substrate and the device layers, in the initial connecting parts of at least one layer, the first initial solder connecting parts and the second initial solder connecting parts are provided with first doping elements, and the content of the first doping elements in the second initial solder connecting parts is larger than that of the first doping elements in the first initial solder connecting parts; and carrying out thermocompression bonding treatment on the initial connecting part by adopting a thermocompression bonding process so as to convert the first initial solder connecting part into a first solder connecting part and convert the second initial solder connecting part into a second solder connecting part, wherein the first solder connecting part is used for electrically connecting the device layer and the substrate which are adjacent to each other and the device layer adjacent to the substrate, and the second solder connecting part is used for supporting the adjacent device layer and the device layer adjacent to the substrate.
In some embodiments, the step of forming the first initial connection comprises: forming electrical connections through the device layer in the device layer; forming first conductive columns at positions opposite to the electric connection parts, forming first initial solder balls on the surfaces of the first conductive columns, wherein the first initial solder balls corresponding to the device layers in adjacent layers are opposite to each other, and the electric connection parts, the first conductive columns and the first initial solder balls form first initial connection parts; the step of forming the second initial connection portion includes: and forming second conductive columns on the surfaces of the adjacent device layers, forming second initial welding balls on the surfaces of the second conductive columns, wherein the second initial welding balls corresponding to the device layers in the adjacent layers are opposite to each other, and the second conductive columns and the second initial welding balls form second initial connecting parts.
In some embodiments, before the thermocompression bonding process step, the method further includes: an adhesive layer is formed between the substrate and the device layer adjacent to the substrate, and between the adjacent device layers.
In some embodiments, the thermocompression bonding process includes a first bonding stage, a second bonding stage, and a third bonding stage, wherein the first bonding stage includes: employing a constant first temperature to cause the adhesive layer to bond the device layer at an adjacent layer and the substrate and the device layer adjacent to the substrate; the second bonding stage comprises: increasing the first temperature to a second temperature to transform the initial connection into a molten state; the third bonding stage comprises: reducing the second temperature to the first temperature to transform the initial connection portion in a molten state to a solid state to bond the device layer at an adjacent layer and the substrate and the device layer adjacent to the substrate.
In some embodiments, a first device layer, a second device layer, and a third device layer are sequentially stacked on the substrate; the thermocompression bonding processing step includes: bonding the substrate and the first device layer by adopting a first bonding temperature; bonding the first device layer and the second device layer bonded with the substrate with a second bonding temperature; bonding the second device layer and the third device layer that have been bonded to the first device layer using a third bonding temperature, wherein the first bonding temperature is less than the second bonding temperature, and the second bonding temperature is less than the third bonding temperature.
In some embodiments, the thermocompression bonding process step comprises: pre-bonding the initial connection parts of all the layers by adopting a fourth bonding temperature so as to preliminarily bond the substrate, the device layer adjacent to the substrate and a plurality of adjacent device layers; and bonding the initial connection parts of all the layers by adopting a fifth bonding temperature so as to enable the substrate, the device layer adjacent to the substrate and the plurality of adjacent device layers to be completely bonded, wherein the fourth bonding temperature is lower than the fifth bonding temperature.
The technical scheme provided by the embodiment of the disclosure at least has the following advantages:
in the stacked package structure provided by the embodiment of the disclosure, a plurality of device layers are stacked on a substrate, wherein a first connection portion and a second connection portion are arranged between the adjacent device layers and the substrate and the device layer adjacent to the substrate, the first connection portion includes a first solder portion capable of electrically connecting the adjacent device layers and the substrate and the device layer adjacent to the substrate, the second connection portion includes a second solder portion capable of supporting the adjacent device layers, and the first solder portion and the second solder portion of at least one layer have a first doping element, the melting temperature of the solder portions is adjusted by adjusting the content of the first doping element in the solder portions, and the content of the first doping element of the first solder connection portion is less than the content of the first doping element of the second solder connection portion, so that there is a temperature difference between the melting temperature of the first solder connection portion and the melting temperature of the second solder connection portion, and the temperature difference can balance the uneven thermocompression bonding conduction temperature during the bonding process of the connection portions to form the stacked package structure.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and which are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a diagram illustrating a package on package structure;
fig. 2 is a schematic structural diagram of a package on package structure according to an embodiment of the present disclosure;
fig. 3 and fig. 4 are schematic structural diagrams illustrating steps of a method for manufacturing a package on package structure according to another embodiment of the disclosure.
Detailed Description
As can be seen from the background, the performance of the current package on package structure needs to be further improved, and the performance of the package on package structure is related to the structure thereof.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a package on package structure 100. The package on package structure 100 includes: a substrate 101 and a plurality of device layers 102 stacked on the substrate 101; a first connection portion 103, the first connection portion 103 including first solder connections 104 and an electrical connection structure 105 penetrating at least one of the device layers 102, wherein the first solder connections 104 are disposed between the device layers 102 and between the substrate 101 and the device layers 102, the first solder connections 104 electrically connect the device layers 102 to the substrate 101 and the device layers 102 adjacent to the substrate 101, and the electrical connection structure 105 is connected to the first solder connections 104; a second connection 106, the second connection 106 including second solder connections 107 disposed between the device layers 102 and between the substrate 101 and the device layer 102 adjacent to the substrate 101, the second solder connections 107 may include second solder connections 107 disposed between the substrate 101 and the device layer 102 adjacent to the substrate 101 and between the adjacent device layers 102, and the second solder connections 107 are not electrically connected to the device layers 102 and the substrate 101.
In some embodiments, the device layer 102 has a first surface 102a and a second surface 102b opposite to each other, and the device layer 102 may further include a redistribution layer 108 disposed on the first surface 102a, and the first solder connection 104 penetrates the redistribution layer 108.
Bonding the connecting parts by using a thermocompression bonding process to form a stacked package structure 100, wherein a bonding head (not shown) is arranged above all the device layers 102, and bonding heat is conducted from the device layers 102 close to the bonding head to the substrate 101, and when the first connecting part 103 is bonded, the heat is directly conducted to the first solder connecting part 104 through the electrical connecting structure 105; when the second connection part 106 is bonded, heat is conducted to the second solder connection part 107 through the adjacent device layer 102 and the redistribution layer 108 on the adjacent device layer 102 in sequence, so that the thermal resistance of the heat transfer path of the first connection part 103 is smaller than that of the heat transfer path of the second connection part 106, and the heat obtained by the first solder connection part 104 is higher than that obtained by the second solder connection part 107 in the same bonding time. When the number of stacked device layers 102 is small, the difference between the amount of heat obtained by the first solder connection 104 and the amount of heat obtained by the second solder connection 107 is relatively small, and the difference between the amount of heat obtained by a connection adjacent to the substrate 101 and the amount of heat obtained by a connection distant from the substrate 101 is relatively small, so that the bonding effect between adjacent device layers 102 and the bonding effect between the device layers 102 and the substrate 101 are relatively good; when the number of stacked layers of the device layer 102 is large, the difference between the heat acquired by the first solder connection portion 104 and the heat acquired by the second solder connection portion 107 is relatively large, and the difference between the heat acquired by the connection portion close to the substrate 101 and the heat acquired by the connection portion far from the substrate 102 is relatively large, so that the problem that the first solder connection portion 104 and the second solder connection portion 107 fail to be bonded or the first solder connection portion 104 fails to be bonded and the second solder connection portion 107 fails to be bonded in the device layer 102 close to the substrate 101 is likely to occur.
The present disclosure provides a stack package structure, which changes a melting temperature of a solder connection by changing a content of a first doping element of the solder connection in a connection portion disposed between a substrate and a device layer adjacent to the substrate and an adjacent device layer, wherein the content of the first doping element of the first solder connection is less than the content of the first doping element of a second solder connection, so that the melting temperature of the first solder connection is higher than the melting temperature of the second solder connection, and in a subsequent bonding process step, a temperature difference exists between the melting temperature of the first solder connection and the melting temperature of the second solder connection, and the temperature difference can balance a portion where a bonding heat obtained by the first solder connection is higher than a bonding heat obtained by the second solder connection, so that a problem of poor bonding of a portion of the device layer or a portion of the same device layer can be solved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter of the present disclosure can be practiced without these specific details and with various changes and modifications based on the following examples.
Fig. 2 is a schematic structural diagram of a package on package structure according to an embodiment of the disclosure.
Referring to fig. 2, an embodiment of the present disclosure provides a package on package structure 200, including: a substrate 201 and a plurality of device layers 202 stacked on the substrate 201; the connections include first connections 203 and second connections 204, the first connections 203 include first solder connections 205 disposed between the device layers 202 and between the substrate 201 and the device layers 202, the first solder connections 205 electrically connect the device layers 202 and the substrate 201, the second connections 204 include second solder connections 206 disposed between the device layers 202 and between the substrate 201 and the device layers 202, and the second solder connections 206 are not electrically connected to the device layers 202 and the substrate 201, wherein the first solder connections 205 and the second solder connections 206 of at least one layer have a first doping element, and a content of the first doping element in the first solder connections 205 is less than a content of the first doping element in the second solder connections 206.
Because the content of the first doping element in the first solder connection portion 205 is less than the content of the first doping element in the second solder connection portion 206, the melting temperature of the first solder connection portion 205 is less than the melting temperature of the second solder connection portion 206, and the heat obtained by the first solder connection portion 205 is greater than the heat obtained by the second solder connection portion 206 during the bonding process of the connection portions, the bonding morphology of the connection portions in the formed stacked package structure 200 is not greatly different, the connection between the connection portions and the adjacent device layer 202 and the substrate 201 is stable, the structures of the stacked package structure 200 have good reliability, and the performance and yield of the stacked package structure 200 are improved.
Specifically, the package on package structure 200 may include a Memory package structure, which may be a Dynamic Random Access Memory (DRAM) package structure, a Static Random Access Memory (SRAM) package structure, or a Magnetic Random Access Memory (MRAM) package structure.
The plurality of device layers 202 may be chips, in some embodiments, the plurality of device layers 202 may be the same kind of chips, and the device layers 202 may be memory chips, for example, each device layer 202 is a dynamic random access memory chip, a static random access memory chip, or a magnetoresistive random access memory chip. In other embodiments, the plurality of device layers 202 may include different kinds of chips. For example, some of the plurality of device layers 202 may be logic chips and other device layers 202 may be memory chips. For example, each of the logic chips may be a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, or an Application Processor (AP) chip.
The substrate 201 may be a Printed Circuit Board (PCB), a flexible substrate, a tape substrate, etc., and the substrate 201 may also be a multi-Circuit Board having through holes and various Circuit elements therein. The substrate 201 may also be a carrier board for carrying the device layer 202 and the connection portion.
In the connection portions of the same layer, the first connection portion 203 may be disposed in a middle region of the layer, and the second connection portion 204 may be disposed in an edge region of the layer; in other embodiments, in the connection portions of the same layer, each two connection portions of the layer include at least one first connection portion 203 and one second connection portion 204. The first connection portion 203 is used for supporting the device layer 202 and the substrate 201 of the adjacent layer, and the second connection portion 204 is used for electrically connecting the adjacent device layer 202 and the substrate 201.
It is understood that, in the bonding process of the connection portions to form the stacked package structure 200, in the connection portions of the same layer, the bonding heat is conducted to the first connection portion 203 at a speed higher than that of the second connection portion 204, and thus the first connection portion 203 obtains heat more than that of the second connection portion 204 in the same bonding time.
The first solder connection portion 205 may include a first solder ball 210 and two first conductive pillars 211, where the first solder ball 210 is located between the two first conductive pillars 211, the first solder ball 210 connects the two first conductive pillars 211, and the two first conductive pillars 211 are respectively disposed on opposite surfaces of adjacent device layers 202; the second solder connection portion 206 may include a second solder ball 212 and two second conductive pillars 213, where the second solder ball 212 is located between the two second conductive pillars 213, the second solder ball 212 connects the two second conductive pillars 213, and the two second conductive pillars 213 are respectively disposed on opposite surfaces of the adjacent device layer 202.
The material types of the first solder connections 205 and the second solder connections 206 may be: tin-silver-copper, tin-bismuth-copper, or the like, and accordingly, the material of the first solder ball 210 and the second solder ball 212 may be tin-silver-copper, tin-silver, or tin-bismuth, and the material of the first conductive pillar 211 and the second conductive pillar 213 may be copper. The first solder connection 205 and the second solder connection 206 have a first doping element, and the first doping element may be one or more of silver, bismuth, indium, and palladium. By increasing the content of the first doping element, the melting temperature of the connection portion can be reduced. The content of the first doping element in the first solder connection 205 is set smaller than the content of the first doping element in the second solder connection 206 so that the melting temperature of the first solder connection 205 is higher than the melting temperature of the second solder connection 206 to balance the part of the heat acquired by the first solder connection 205 that is higher than the second solder connection 206.
Specifically, the material type of the first solder connection 205 and the second solder connection 206 is tin-silver-copper, and the melting temperature of the first solder connection 205 is adjusted to be higher than that of the second solder connection 206 by increasing the content of silver in the first solder connection 205 and reducing the content of silver in the second solder connection 206, so as to match the part of the first solder connection 205 where the heat obtained is higher than that of the second solder connection 206, thereby ensuring the bonding success rate of the connections; the material type of the first solder connection 205 and the second solder connection 206 is tin-bismuth-copper, and the content of bismuth in the first solder connection 205 and the second solder connection 206 is adjusted, or silver is doped in the first solder connection 205 and the second solder connection 206, so as to adjust the melting temperature of the first solder connection 205 and the melting temperature of the second solder connection 206, so as to match the part of the first solder connection 205, which obtains heat larger than that of the second solder connection 206, thereby improving the bonding success rate of the connections, and the formed stacked package structure 200 has better performance.
In some embodiments, the difference between the content of the first doping element of the first solder connection 205 and the content of the first doping element of the second solder connection 206 may range from-5.5% to-1.5%, in some embodiments, the difference between the content of the first doping element of the first solder connection 205 and the content of the first doping element of the second solder connection 206 may be relatively small when the number of stacked device layers 202 in the stacked package structure 200 is small, the difference may be-1.5%, -2%, or-2.5%, in other embodiments, the difference between the content of the first doping element of the first solder connection 205 and the content of the first doping element of the second solder connection 206 may be relatively large when the number of stacked device layers 202 in the stacked package structure 200 is large, the difference may be-4.5%, -5%, or-5.5%. With such an arrangement, on one hand, the content of the first doping element in different connection portions is set according to the number of stacked device layers 202, so that the success rate of bonding of the connection portions is ensured, and thus the yield and the performance of the formed stacked package structure 200 are improved.
In some embodiments, the first doping element may be silver; the content of the first doping element in the first solder connection 205 may be 0.5% to 2%, for example, the content of the first doping element in the first solder connection 205 may be 0.5%, 1%, or 2%, the content of the first doping element in the second solder connection 206 may be 3.5% to 6%, for example, the content of the first doping element in the second solder connection 206 may be 3.5%, 4%, or 6%. In other embodiments, the material of the first solder connection 205 may also be pure tin, and the content of the first doping element in the second solder connection 206 may be 3.5% to 6%.
The first connection 203 may further include an electrical connection structure 207 extending through the at least one device layer 202, the electrical connection structure 207 being connected to the first solder connection 205, a melting temperature of the electrical connection structure 207 being greater than a melting temperature of the first solder connection 205. Due to the arrangement of the electrical connection structure 207, during the bonding process to form the stacked package structure 200, the first solder connection 205 directly obtains heat through conduction of the electrical connection structure 207, and the second solder connection 206 obtains heat through conduction of the adjacent device layer 202, compared with the thermal resistance of the heat transfer path of the second solder connection 206, the thermal resistance of the heat transfer path of the first solder connection 205 is smaller, so that the first solder connection 205 obtains heat more quickly, and therefore, the first solder connection 205 obtains more heat in the same bonding time, so that in the case of more stacked device layers 202, bonding of part of the second solder connection 206 fails, thereby affecting the yield of the stacked package structure 200. Wherein the material of the electrical connection structure 207 may be copper, tungsten, polysilicon, or the like, in some embodiments, the electrical connection structure 207 may include a plurality of electrical connection structures 207 penetrating through the device layer 202. In other embodiments, the electrical connection structure 207 may also include a plurality of electrical connection structures 207 that extend through portions of the device layer 202.
In some embodiments, the device layers 202 may include a top device layer 202a, the top device layer 202a being the device layer 202 that is the farthest distance from the substrate 201.
In some embodiments, the plurality of device layers 202 stacked on the substrate 201 may further include a bottom device layer 202b, the bottom device layer 202b being adjacent to the substrate 201.
It is understood that during the bonding process of the connections to form the stacked package structure 200, the bond head is disposed above the top device layer 202a and is in contact with the top device layer 202a, the bond head generates heat, and the heat is transferred from the top device layer 202a to the rest of the device layers 202 below the top device layer 202a, and the heat is gradually consumed during the transfer, so that the heat obtained by the connections of different layers is gradually decreased from the top device layer 202a to the substrate 201, and on the other hand, the heat obtained by the second solder connection 206 between the substrate 201 and the bottom device layer 202b is minimized because the heat conduction path of the first solder connection 205 is faster than the heat conduction path of the second solder connection 206.
In some embodiments, the content of the first doping element in the second solder connection 206 disposed between the bottom device layer 202b and the substrate 201 is greater than the content of the first doping element in the second solder connection 206 disposed between the other device layers 202, so that the first doping element content of the second solder connection 206 disposed between the bottom device layer 202b and the substrate 201 is highest and the melting temperature of the second solder connection 206 is lowest in all the solder connections of the layers to match the lower heat obtained by the second solder connection 206, thereby ensuring that the second solder connection 206 is well bonded and ensuring that the solder connection 206 has a small difference in the bonding morphology from the other solder connections 206.
In some embodiments, in the connection provided between the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, the first doping element content of the first solder connection 205 is the same as the first doping element content in the second solder connection 206.
Specifically, in the connection between the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, the electrical connection structure 207 may include an electrical connection structure 207 penetrating through the device layer 202 adjacent to the top device layer 202a, and the electrical connection structure 207 does not penetrate through the top device layer 202a, since in forming the stacked package structure 200, the bond head is disposed above the top device layer 202a, in the connection between the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, the electroless connection 207 assists the first solder connection 205 in gaining heat, and the heat conducted to the first solder connection 205 is not different from the heat conducted to the second solder connection 206, wherein, in the connection disposed between the top device layer 202a and the adjacent device layer 202, all connections have the same first doping element content, i.e., all solder connections have the same melting temperature, so as to reduce the possibility of a difference in the soldering morphology between the first solder connection 205 and the second solder connection 206.
In other embodiments, in the connections provided between the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, the first doping element content of the first solder connections 205 and the first doping element content in the second solder connections 206 are different.
Specifically, in the connection between the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, the electrical connection structure 207 may include an electrical connection structure 207 that penetrates through the top device layer 202a and the device layer 202 adjacent to the top device layer 202a, and due to the arrangement of the electrical connection structure 207, in the connection arranged between the top device layer 202a and the adjacent device layer 202, the first solder connection 202 obtains a higher amount of heat than the second solder connection 206, wherein in the connection arranged between the top device layer 202a and the adjacent device layer 202, the first solder connection 205 has a lower content of the first doping element than the second solder connection 206 to balance a portion of the heat obtained at the first solder connection 205 than the second solder connection 206 during heat transfer.
In some embodiments, in the multi-layer connection portion adjacent to the substrate 201, the content of the first doping element of the second solder connection portion 206 is greater than the content of the first doping element of the first solder connection portion 205, that is, in the multi-layer connection portion adjacent to the substrate 201, the melting temperature of the second solder connection portion 206 is higher than the melting temperature of the first solder connection portion 205, so as to match the situation that the heat obtained by the first solder connection portion 205 is higher than the heat obtained by the second solder connection portion 206 in the multi-layer connection portion adjacent to the substrate 201 during the heat transfer process with thermocompression bonding, and still ensure that all connection portions have a higher bonding success rate.
In some embodiments, the content of the first doping element of the second solder connections 206 is greater than the content of the first doping element of the first solder connections 205 for all layer connections. Compared with the previous embodiment in which some of the connections have different first doping element contents, in this embodiment, all of the second solder connections 206 and all of the first solder connections 205 have different first doping element contents, that is, the melting temperature of the second solder connections 206 is lower than that of the first solder connections 205 in all layers, which further improves the bonding success probability of all connections.
In some embodiments, an Adhesive layer 208 may be further disposed between the substrate 201 and the bottom device layer 202b and between the adjacent device layers 202 to fix each device layer 202 and the substrate 201, and the Adhesive layer may be an NCF (Non-Conductive Adhesive Film) layer, a DAF (Die Attach Film) layer. In the process of forming the stacked package structure 200, the adhesive layer 208 is heated to be converted into a flowable state, and in an area where the obtained heat is higher, the adhesive layer 208 is more likely to flow, and the connection portion flows along with the flow of the adhesive layer 108, and the heat obtained by the first solder connection portion 205 is relatively more than that obtained by the second solder connection portion 206, so as to avoid coupling due to relative flow of the adjacent first solder connection portions 205 caused by relatively higher obtained heat, in some embodiments, in a direction parallel to the substrate 201, the first solder connection portion 205 has a maximum first size, and the second solder connection portion 206 has a maximum second size, and the first size is smaller than the second size. As such, by controlling the size of the first solder connections 205, the likelihood of coupling adjacent first solder connections 205 due to flow of the first solder connections 205 that acquire more heat is reduced.
In some embodiments, the surface of the device layer 202 facing the substrate 201 may be further provided with a redistribution layer 209, the first solder connection 205 penetrates the redistribution layer 209, and the second connection 204 is provided on the redistribution layer 209.
The stacked package structure 200 provided by the embodiment of the disclosure is provided with connections between the substrate 201 and the device layers 202 and the adjacent device layers 202, the connections include a first connection 203 and a second connection 204, the first connection 203 includes a first solder connection 205 disposed between the device layers 202 and between the substrate 201 and the device layers 202, the first connection 203 further includes an electrical connection structure 207 penetrating through at least one of the device layers 202, and the electrical connection structure 207 is in contact with the first solder connection 205, the second connection 204 includes a second solder connection 206 disposed between the device layers 202 and between the substrate 201 and the device layers 202, wherein the first solder connection 205 and the second solder connection 206 of at least one layer have a first doping element, the melting temperature of the connection can be adjusted by adjusting the content of the first doping element in the connections, the content of the first doping element in the first solder connection 205 is smaller than the content of the doping element in the second solder connection 206, that is, the melting temperature of the first solder connection 205 is higher than the melting temperature of the second solder connection 206, so as to adapt to the stacked package structure 200 processed, the stacked package structure 200 has a higher heat bonding yield and a higher reliability of the stacked package structure 200.
Accordingly, another embodiment of the present disclosure further provides a method for manufacturing a package on package structure, in which the package on package structure provided in the foregoing embodiment can be formed, and a semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the drawings. Fig. 3 and fig. 4 are schematic structural diagrams corresponding to steps of a method for manufacturing a package on package structure according to another embodiment of the disclosure.
Referring to fig. 3, a substrate 301 and a plurality of device layers 302 stacked on the substrate 301 are provided, and initial connection portions are formed between the device layers 302 in adjacent layers, the initial connection portions in the same layer include a first initial connection portion 303 and a second initial connection portion 304, wherein the first initial connection portion 303 includes a first initial solder connection portion 305 between the device layers 302 and between the substrate 301 and the device layers 302, the second initial connection portion 304 includes a second initial solder connection portion 306 disposed between the device layers 302 and between the substrate 301 and the device layers 302, in the initial connection portions in at least one layer, the first initial solder connection portion 305 and the second initial solder connection portion 306 have a first doping element, and the content of the first doping element in the second initial solder connection portion 306 is greater than the content of the first doping element in the first initial solder connection portion 305. So configured, the melting temperature of the second initial solder connection 306 is less than the melting temperature of the first initial solder connection 305.
In some embodiments, the first doping element may be one or more of silver, bismuth, indium, palladium.
The step of forming the first preliminary connection part 303 may include: forming electrical connections 309 through device layer 302 in device layer 302; forming first conductive columns 310 at positions opposite to the electrical connection portions 309, forming first initial solder balls 311 on the surfaces of the first conductive columns 310, wherein the first initial solder balls 311 corresponding to the device layer 302 in the adjacent layer are opposite to each other, and the electrical connection portions 309, the first conductive columns 310 and the first initial solder balls 311 form first initial connection portions 303; the step of forming the second preliminary connection portion 304 includes: second conductive pillars 312 are formed on the surfaces of the adjacent device layers 302, second initial solder balls 313 are formed on the surfaces of the second conductive pillars 312, and the second initial solder balls 313 corresponding to the device layers 302 in the adjacent layers are opposite to each other, wherein the second conductive pillars 312 and the second initial solder balls 313 form second initial connection portions 304.
In some embodiments, the first initial connection portion 303 may include two first conductive pillars 310, and the first initial solder ball 311 is formed between the two first conductive pillars 310, where the two first conductive pillars 310 are the third conductive pillar 310a and the fourth conductive pillar 310b; the second initial connecting portion 304 may include two second conductive pillars 312, and the second initial solder ball 313 is formed between the two second conductive pillars 312, which are the fifth conductive pillar 312a and the sixth conductive pillar 312b.
Referring to fig. 4, the initial connection portions are subjected to a thermocompression bonding process 11 using a thermocompression bonding process such that the first initial solder connection portions 305 are converted into first solder connection portions 307 and the second initial solder connection portions 306 are converted into second solder connection portions 308, the first solder connection portions 307 are used to electrically connect the device layer 302 and the substrate 301 at adjacent layers and the device layer 302 adjacent to the substrate 301, and the second solder connection portions 308 are used to support the adjacent device layer 302 and the device layer 302 adjacent to the substrate 301.
In some embodiments, the surface of the device layer 302 facing the substrate 301 may also be formed with a redistribution layer 314, and the second conductive pillars 312 are disposed through the redistribution layer 314.
Before the step of thermocompression bonding 11, the method further comprises: an adhesive layer 315 is formed between the substrate 301 and the device layer 302 adjacent to the substrate 301, and between the adjacent device layers 302.
The thermocompression bonding process 11 includes a first bonding stage, a second bonding stage, and a third bonding stage, wherein the first bonding stage includes: a constant first temperature is adopted so that the adhesive layer 315 bonds the device layer 302 at the adjacent layer and the substrate 301 and the device layer 302 adjacent to the substrate 301; the second bonding stage comprises: raising the first temperature to a second temperature to transform the initial connection portion into a molten state; the third bonding stage comprises: the second temperature is lowered to the first temperature to transform the initial connection portion in a molten state into a solid state to bond the device layer 302 and the substrate 301 and the device layer 302 adjacent to the substrate 301 at adjacent layers.
It is understood that in the thermocompression bonding process 11, the bond head 316 is disposed above the device layer 302 farthest from the substrate 301 and in contact with the device layer 302, so that heat generated by the bond head 316 is conducted from the device layer 302 to the substrate 301, and the bonding temperature of each initial connection portion gradually decreases from the device layer 302 adjacent to the bond head 316 to the substrate 301.
In some embodiments, thermocompression bonding process 11 may include bonding initial connections between substrate 301 and device layers 302 adjacent to substrate 301 and at least 2 cycles, wherein each cycle includes: stacking a device layer 302 on the bonded device layer 302, and bonding the initial connection portion between the two device layers 302, so that the thermocompression bonding process 11 can be performed at relatively low bonding temperature, time, and pressure for each step of bonding, and each device layer 302 can be stacked to a desired position more precisely by stacking one device layer 302 and bonding the device layer 302 to the adjacent device layer 302. In some embodiments, a first device layer, a second device layer, and a third device layer may be sequentially stacked on the substrate 301; the thermocompression bonding process 11 includes: bonding the substrate 301 and the first device layer with a first bonding temperature; bonding the first device layer and the second device layer bonded to the substrate 301 with a second bonding temperature; and bonding the second device layer and the third device layer which are bonded with the first device layer by using a third bonding temperature, wherein the first bonding temperature is lower than the second bonding temperature, and the second bonding temperature is lower than the third bonding temperature.
Specifically, each bonding stage may include a first bonding stage, a second bonding stage, and a third bonding stage, where the first bonding stage may be preceded by a pre-bonding stage, and process parameters of the pre-bonding stage include: the bonding temperature may range from 100 to 150 deg.c, for example, the bonding temperature may range from 100 deg.c, 125 deg.c, 130 deg.c, or 145 deg.c, the bonding time may range from 3s to 10s, for example, the bonding time may range from 3s, 5s, or 10s, so that the adhesive layer 315 may flow, and the process parameters of the first bonding stage include: the first temperature may range from 150 ℃ to 180 ℃, for example, the first temperature may range from 155 ℃, 175 ℃, or 180 ℃, and the bonding time may range from 8s to 15s, for example, the bonding time may be 9s, 10s, or 11s, to cause the adhesive layer 315 to flow and bond the adjacent device layer 302 and substrate 301; the process parameters of the second bonding stage include: the second temperature range may be 200 ℃ to 235 ℃, for example, the second temperature may be 215 ℃, 230 ℃ or 235 ℃, and the bonding time may be 5s to 8s, for example, the bonding time may be 5s, 6s or 8s, so as to ensure that the first initial connection portion 303 and the second initial connection portion 304 are both transformed into a molten state; the process parameters of the third bonding stage include: the third temperature may be in a range of 60 c to 80 c, for example, the third temperature may be 60 c, 70 c or 80 c, so that the adhesive layer 315, the initial connection portion are transformed into a solid state, thereby fixedly connecting the substrate 301 and the device layer 302.
The thermocompression bonding process 11 may also be a step of pre-bonding the initial connection portions of all the layers by using a fourth bonding temperature, so as to perform preliminary bonding between the substrate 301 and the device layer 302 adjacent to the substrate 301 and between the adjacent device layers 302; and bonding the initial connection parts of all the layers at a fifth bonding temperature so as to completely bond the substrate 301 and the device layer 302 adjacent to the substrate 301 and the plurality of adjacent device layers 302, wherein the fourth bonding temperature is lower than the fifth bonding temperature. In this way, the spacing between adjacent layers can be better controlled.
Specifically, the process parameters of the initial connection portions of all the layers to be pre-bonded include that the fourth bonding temperature range may be 100 ℃ to 125 ℃, for example, the fourth bonding temperature may be 100 ℃, 110 ℃ or 120 ℃, and the bonding time range may be 0.5s to 2s, for example, the bonding temperature may be 0.7s, 0.8s or 1.5s, so that all the initial connection portions initially connect the adjacent device layers 302 and the substrate 301; before the device layer 302 and the substrate 301 are bonded by using the fifth bonding temperature, a pre-bonding stage may be further included, and process parameters of the pre-bonding stage include: the bonding temperature may range from 120 ℃ to 155 ℃, for example, the bonding temperature may range from 125 ℃, 150 ℃, or 155 ℃, the bonding time may range from 3s to 5s, for example, the bonding time may range from 3s, 4s, or 5s, so that the adhesive layer 315 may flow; the step of bonding the initial connection portions of all the layers by using the fifth bonding temperature may include a first bonding stage, a second bonding stage and a third bonding stage, and the process parameters of the first bonding stage include: the first temperature may range from 180 ℃ to 200 ℃, e.g., the first temperature may be 185 ℃, 190 ℃ or 200 ℃, and the bonding time may range from 10s to 15s, e.g., the bonding time may be 10s, 12s or 15s, to cause the adhesive layer 315 to flow and bond the adjacent device layer 302 and substrate 301; the process parameters of the second bonding stage include: the second temperature range may be 220 ℃ to 255 ℃, for example, the second temperature may be 225 ℃, 250 ℃ or 255 ℃, and the bonding time may be 5s to 10s, for example, the bonding time may be 5s, 8s or 10s, so as to ensure that the first initial connection portion 303 and the second initial connection portion 304 are both transformed into a molten state; the process parameters of the third bonding stage include: the third temperature may be in the range of 60 c to 80 c, for example, the third temperature may be 65 c, 70 c, or 75 c, so that the adhesive layer 315, the initial connection portion are transformed into a solid state, thereby fixedly connecting the substrate 301 and the device layer 302.
The manufacturing method of the stacked package structure provided by the embodiment of the disclosure forms a first initial connection 303 and a second initial connection 304 between the substrate 301 and the device layer 302 adjacent to the substrate 301 and between the device layers 302, the first initial connection 303 can include a first initial solder connection 305 between the device layers 302 and between the substrate 301 and the device layers 302, the second initial connection 304 can include a second initial solder connection 306 between the device layers 302 and between the substrate 301 and the device layers 302, wherein the first initial solder connection 305 and the second initial solder connection 306 have a first doping element, and the content of the first doping element of the first initial solder connection 305 is less than that of the second initial solder connection 306, so that the melting temperature of the first initial solder connection 305 is higher than that of the second initial solder connection 306; the initial connection parts are subjected to thermocompression bonding, the melting temperature of the first initial solder connection part 305 is matched with the relatively high bonding heat obtained by the first initial solder connection part, so that the first initial solder connection part 305 is converted into a first solder connection part 307, and the melting temperature of the second initial solder connection part 306 is matched with the relatively low bonding heat obtained by the second initial solder connection part, so that the second initial solder connection part 306 is converted into a second solder connection part 308.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of the practice of the disclosure, and that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and the scope of the present disclosure should be defined only by the appended claims.

Claims (17)

1. A package on package structure, comprising:
a substrate and a plurality of device layers stacked on the substrate;
the connecting part comprises a first connecting part and a second connecting part, the first connecting part comprises first solder connecting parts arranged between the device layers and between the substrate and the device layers, the first solder connecting parts are electrically connected with the device layers and the substrate, the second connecting part comprises second solder connecting parts arranged between the device layers and between the substrate and the device layers, the second solder connecting parts are not electrically connected with the device layers and the substrate, the first solder connecting parts and the second solder connecting parts of at least one layer have first doping elements, and the content of the first doping elements in the first solder connecting parts is smaller than that of the first doping elements in the second solder connecting parts.
2. The package on package structure of claim 1, wherein the first connection further comprises an electrical connection structure through at least one of the device layers, the electrical connection structure being connected to the first solder connection, the electrical connection structure having a melting temperature greater than a melting temperature of the first solder connection.
3. The package on package structure of claim 1, wherein the plurality of device layers stacked on the substrate include a bottom device layer, and wherein a content of the first doping element in the second solder connection between the bottom device layer and the substrate is greater than a content of the first doping element in the second solder connection between the other device layers.
4. The package on package structure of claim 1, wherein the device layer further comprises a top device layer, the top device layer being in the connection with an adjacent device layer, the first solder connection having a same or different first doping element content than the second solder connection.
5. The package on package structure of claim 1, wherein a content of the first doping element of the second solder connection is greater than a content of the first doping element of the first solder connection in the plurality of layers of the connection adjacent to the substrate.
6. The package on package structure of claim 1, wherein a content of the first doping element of the second solder connection is greater than a content of the first doping element of the first solder connection for the connections of all layers.
7. The package on package structure of any one of claims 1 to 6, wherein a difference between a content of the first doping element of the first solder connection and a content of the first doping element of the second solder connection ranges from-5.5% to-1.5%.
8. The package on package structure of any one of claims 1 to 6, wherein the first doping element content of the first solder connection is 0.5% to 2%, and the first doping element content of the second solder connection is 3.5% to 6%.
9. The package on package structure of claim 1, wherein the first solder connection has a largest first dimension and the second solder connection has a largest second dimension in a direction parallel to the substrate, the first dimension being smaller than the second dimension.
10. The package on package structure of claim 1, wherein the first doping element comprises one or more of silver, bismuth, indium, palladium.
11. The package on package structure of claim 10, wherein the first doping element is silver; the content of the first doping element in the first solder connection part is 0.5% -2%, and the content of the first doping element in the second solder connection part is 3.5% -6%.
12. A method for manufacturing a package on package structure includes:
providing a substrate and a plurality of device layers which are arranged on the substrate in a stacking mode, wherein initial connecting parts are formed between the device layers of adjacent layers, the initial connecting parts of the same layer comprise first initial connecting parts and second initial connecting parts, the first initial connecting parts comprise first initial solder connecting parts between the device layers and between the substrate and the device layers, the second initial connecting parts comprise second initial solder connecting parts arranged between the device layers and between the substrate and the device layers, in the initial connecting parts of at least one layer, the first initial solder connecting parts and the second initial solder connecting parts are provided with first doping elements, and the content of the first doping elements in the second initial solder connecting parts is larger than that of the first doping elements in the first initial solder connecting parts;
and carrying out thermocompression bonding treatment on the initial connecting part by adopting a thermocompression bonding process so as to convert the first initial solder connecting part into a first solder connecting part and convert the second initial solder connecting part into a second solder connecting part, wherein the first solder connecting part is used for electrically connecting the device layer and the substrate which are adjacent to each other and the device layer adjacent to the substrate, and the second solder connecting part is used for supporting the adjacent device layer and the device layer adjacent to the substrate.
13. The method of manufacturing a package on package structure according to claim 12, wherein the step of forming the first initial connection portion comprises: forming electrical connections through the device layer in the device layer; forming first conductive columns at positions opposite to the electric connection parts, forming first initial solder balls on the surfaces of the first conductive columns, wherein the first initial solder balls corresponding to the device layers in adjacent layers are opposite to each other, and the electric connection parts, the first conductive columns and the first initial solder balls form first initial connection parts; the step of forming the second initial connection portion includes: and forming second conductive columns on the surfaces of the adjacent device layers, forming second initial welding balls on the surfaces of the second conductive columns, wherein the second initial welding balls corresponding to the device layers in the adjacent layers are opposite to each other, and the second conductive columns and the second initial welding balls form second initial connecting parts.
14. The method for manufacturing a package on package structure according to claim 12, further comprising, before the thermocompression bonding step: an adhesive layer is formed between the substrate and the device layer adjacent to the substrate, and between the adjacent device layers.
15. The method of manufacturing the package on package structure according to claim 12 or 14, wherein the thermocompression bonding process comprises a first bonding stage, a second bonding stage, and a third bonding stage, wherein the first bonding stage comprises: applying a constant first temperature to cause the adhesive layer to bond the device layer at an adjacent layer and the substrate and the device layer adjacent to the substrate; the second bonding stage comprises: increasing the first temperature to a second temperature to transform the initial connection into a molten state; the third bonding stage comprises: reducing the second temperature to the first temperature to transform the initial connection portion in a molten state to a solid state to bond the device layer at an adjacent layer and the substrate and the device layer adjacent to the substrate.
16. The method for manufacturing a package on package structure according to claim 12, wherein a first device layer, a second device layer, and a third device layer are sequentially stacked on the substrate; the thermocompression bonding processing step includes: bonding the substrate and the first device layer using a first bonding temperature; bonding the first device layer and the second device layer bonded with the substrate using a second bonding temperature; bonding the second device layer and the third device layer bonded with the first device layer using a third bonding temperature, wherein the first bonding temperature is less than the second bonding temperature, and the second bonding temperature is less than the third bonding temperature.
17. The method of claim 12, wherein the thermocompression bonding process comprises: pre-bonding the initial connection parts of all the layers by adopting a fourth bonding temperature so as to preliminarily bond the substrate, the device layer adjacent to the substrate and a plurality of adjacent device layers; and bonding the initial connection parts of all the layers by adopting a fifth bonding temperature so as to enable the substrate, the device layer adjacent to the substrate and the plurality of adjacent device layers to be completely bonded, wherein the fourth bonding temperature is lower than the fifth bonding temperature.
CN202211124804.3A 2022-09-15 2022-09-15 Stack package structure and manufacturing method thereof Pending CN115346946A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116313946A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Temperature adjusting system and adjusting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116313946A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Temperature adjusting system and adjusting method
CN116313946B (en) * 2023-05-24 2023-10-17 长鑫存储技术有限公司 Temperature adjusting system and adjusting method

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