CN115425015A - Stack package structure and manufacturing method thereof - Google Patents

Stack package structure and manufacturing method thereof Download PDF

Info

Publication number
CN115425015A
CN115425015A CN202211159597.5A CN202211159597A CN115425015A CN 115425015 A CN115425015 A CN 115425015A CN 202211159597 A CN202211159597 A CN 202211159597A CN 115425015 A CN115425015 A CN 115425015A
Authority
CN
China
Prior art keywords
conductive
substrate
chip
solder
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211159597.5A
Other languages
Chinese (zh)
Inventor
刘莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202211159597.5A priority Critical patent/CN115425015A/en
Publication of CN115425015A publication Critical patent/CN115425015A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding

Abstract

The embodiment of the disclosure provides a stacked package structure and a manufacturing method thereof, wherein the stacked package structure comprises: the chip comprises a substrate and a plurality of chips which are stacked on the substrate, wherein each chip comprises a first surface and a second surface which are opposite, a device layer is arranged on the second surface, and a conductive through hole which penetrates through the chip is formed in each chip; the first conductive part and the second conductive part are arranged on the first surface, and the first conductive part is contacted with the conductive through hole; a heat conduction part arranged on the first surface and contacting the second conductive part; a first solder part located between the adjacent chips and contacting the first conductive part to electrically connect the adjacent chips; a second solder part located between adjacent chips and contacting the second conductive part; the first solder part and the second solder part are positioned on the surface of the device layer of the second surface. The embodiment of the disclosure is at least beneficial to improving the bonding success rate of the second welding flux part so as to improve the reliability of the stacked packaging structure.

Description

Package on package structure and method for manufacturing the same
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a stacked package structure and a manufacturing method of the stacked package structure.
Background
With the development of semiconductor technology, the size of a semiconductor device tends to be high in integration level and multifunctional, the existing 2D packaging is difficult to meet the technical requirements, and the 3D packaging has the characteristics of small size and light weight, can meet the development requirements of the semiconductor technology and is widely applied. Bonding is a key process for realizing 3D packaging, wherein the bonding technology currently applied to 3D packaging includes a Thermal Compression Bonding (TCB) process, when a Thermal Compression bonding process is used for stacking semiconductor device layers, the Thermal conduction of the Thermal Compression bonding is relatively uniform when the number of stacked layers is relatively low, the bonding effect is relatively good, and when the number of stacked layers is relatively high, the Thermal conduction of the Thermal Compression bonding is non-uniform and the bonding effect is relatively poor.
Therefore, the performance of the stack package structure still needs to be improved.
Disclosure of Invention
The embodiment of the disclosure provides a stacked package structure and a manufacturing method of the stacked package structure, which are at least beneficial to solving the problem that bonding of part of chips fails when bonding processing is performed on a plurality of layers of chips.
According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a package on package structure, including: the chip comprises a substrate and a plurality of chips which are stacked on the substrate, wherein the chips comprise a first surface and a second surface which are opposite, the second surface is provided with a device layer, and the chips are internally provided with conductive through holes which penetrate through the chips; the first conductive part and the second conductive part are arranged on the first surface, and the first conductive part is in contact with the conductive through hole; a heat conduction portion disposed on the first surface and contacting the second conductive portion; a first solder part located between the adjacent chips, and contacting the first conductive part to electrically connect the adjacent chips; a second solder part located between the adjacent chips, and the second solder part is in contact with the second conductive part; the first solder part and the second solder part are positioned on the surface of the device layer of the second surface of the chip.
In some embodiments, the heat conducting portion is disposed around an edge of the first surface, the heat conducting portion includes a first end and a second end at a fore end and an aft end, and the first end is adjacent to the second end.
In some embodiments, the heat conducting portion comprises: a plurality of linear parts arranged at intervals; each bent part is connected between the adjacent linear parts and bent towards the edge direction close to the first surface.
In some embodiments, the bent shape of the bent portion includes a dogleg shape or an arc shape.
In some embodiments, the first surface of the same chip has a plurality of the second conductive portions, and the same thermal conductive portion is in contact with the plurality of the second conductive portions.
In some embodiments, the material of the heat conducting portion comprises a metal material that provides resistive heat.
In some embodiments, the material of the first conductive portion is the same as the material of the second conductive portion.
In some embodiments, a surface of the substrate facing the chip is provided with the device layer, and the first conductive portion and the second conductive portion are also located on the surface of the substrate facing the chip; the heat conduction part is also positioned on the surface of the substrate facing the chip and contacts the second conductive part on the substrate; the first solder portion is also located between the substrate and the chip adjacent to the substrate and in contact with the first conductive portion on the substrate and the device layer adjacent to the substrate to electrically connect the substrate and the chip; the second initial solder portion is also located between the substrate and the chip adjacent to the substrate and in contact with the second conductive portion on the substrate and the device layer adjacent to the substrate.
In some embodiments, the material of the first solder portion is the same as the material of the second solder portion.
In some embodiments, a plurality of through holes are disposed in the substrate and the chip, the through holes penetrating through the substrate, the chip, and the device layer.
In some embodiments, the second side of each of the chips is provided with a plurality of the device layers.
According to some embodiments of the present disclosure, there is also provided in another aspect of the embodiments of the present disclosure a method for manufacturing a package on package structure, including: providing a substrate and a plurality of chips stacked on the substrate, wherein the chips are provided with a first surface and a second surface which are opposite, a device layer is formed on the second surface, and a conductive through hole penetrating through the chips is formed in each chip; forming a first conductive part and a second conductive part on the first surface, wherein the first conductive part is in contact with the conductive via hole; forming a heat conduction portion which is located on the first surface and contacts the second conductive portion; forming a first initial solder portion and a second initial solder portion between adjacent ones of the chips, the first initial solder portion being in contact with the first conductive portion and the device layer, the second initial solder portion being in contact with the second conductive portion and the device layer; performing a bonding process to convert the first initial solder portion into a first solder portion secured to the first conductive portion and the device layer and to convert the second initial solder portion into a second solder portion secured to the second conductive portion and the device layer, and in the bonding process step, supplying an electric current to the heat conductive portion to cause the heat conductive portion to generate heat.
In some embodiments, the process of forming the thermally conductive portion is the same as the process of forming the first and second electrically conductive portions.
In some embodiments, further comprising: forming the first conductive part and the second conductive part on a surface of the substrate facing the chip; forming the heat conduction portion on a surface of the substrate facing the chip, the heat conduction portion contacting the second conductive portion on the substrate; forming the first initial solder portion and a second initial solder portion between the substrate and the chip adjacent to the substrate, the first initial solder portion being in contact with the first conductive portion on the substrate and the device layer adjacent to the substrate, the second solder portion being in contact with the second conductive portion on the substrate and the device layer adjacent to the substrate.
In some embodiments, a first chip, a second chip, a third chip and a fourth chip are sequentially stacked on the substrate, wherein in the bonding processing step, the heat conduction portion on the first chip generates more heat than the heat conduction portion on the second chip, and the heat conduction portion on the second chip generates more heat than the heat conduction portion on the third chip.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
in the stacked package structure provided by the embodiment of the disclosure, a plurality of chips are stacked on a substrate, the plurality of chips have opposite first and second surfaces, wherein a device layer is disposed on the second surface, a first conductive portion and a second conductive portion are disposed on the first surface, a conductive through hole penetrating through the chips is further disposed in each chip, the first solder portion is in contact with the conductive through hole, the first conductive portion is in contact with the first solder portion to electrically connect adjacent chips, and the second conductive portion is in contact with the second solder portion, so that when the semiconductor structure is subjected to bonding processing, compared with the second solder portion, the arrangement of the conductive through hole enables the speed of bonding heat to be relatively fast in conducting to the first solder bonding portion, the heat conducting portion is further disposed on the first surface, and the heat conducting portion is in contact with the second conductive portion, so that the heat conducting portion generates heat and conducts to the second conductive portion, the heat quantity difference between the first solder portion and the second solder portion is balanced, the bonding of the solder portion is increased, the bonding success rate of the first solder portion and the second solder portion is reduced, and the performance and yield of the formed semiconductor structure are improved.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a cross-sectional view of a package on package structure;
fig. 2 is a schematic cross-sectional structure diagram of a package on package structure according to an embodiment of the disclosure;
fig. 3 is a schematic top view of a chip in a package on package structure according to an embodiment of the disclosure;
fig. 4 is a schematic top view of a chip in another package on package structure according to an embodiment of the disclosure;
fig. 5 is a schematic top view illustrating a chip in a package on package structure according to another embodiment of the disclosure;
fig. 6 is a schematic top view illustrating a chip in a package on package structure according to another embodiment of the present disclosure;
fig. 7 is a schematic top view illustrating a chip in a package on package structure according to an embodiment of the disclosure;
fig. 8 and 9 are schematic cross-sectional views corresponding to steps of a method for manufacturing a package on package structure according to another embodiment of the disclosure.
Detailed Description
As is known in the art, the performance of the stacked package structure still needs to be improved.
The performance of the stacked package structure is closely related to its structure. Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a package on package structure. The package on package structure 100 includes: the chip-on-chip packaging structure comprises a substrate 101 and a plurality of chips 102 stacked on the substrate 101, wherein the chips 102 comprise a first surface 102a and a second surface 102b which are opposite to each other, a device layer 103 is arranged on the second surface 102b, and conductive through holes 104 penetrating through the chips 102 are formed in the chips 102; first connection portions 105 located between the adjacent chips 102, and the first connection portions 105 are in contact with the conductive vias 104 to electrically connect the adjacent chips 102; and a second connection portion 106 between adjacent chips 102.
In the process of forming the stacked package structure 100, a bond head (not shown) is disposed above all the chips 102, and bonding heat is conducted from the chip 102 close to the bond head to the substrate 101, wherein when the first connection portion 105 is bonded, the heat is directly conducted to the first connection portion 105 through the conductive via 104; when the second connection part 106 is bonded, heat is conducted to the second connection part 106 through the adjacent chip 102 and the device layer 103 on the adjacent chip 102 in sequence, so that the thermal resistance of the heat conduction path of the first connection part 105 is smaller than that of the heat conduction path of the second connection part 106, the heat conduction speed at the first connection part 105 is higher than that at the second connection part 106, and therefore the heat obtained by the first connection part 105 is higher than that obtained by the second connection part 106 within the same bonding time. For example, when the number of stacked layers of the chips 102 is small, the difference between the amount of heat acquired by the first connection portion 105 and the amount of heat acquired by the second connection portion 106 is relatively small, and the difference between the amount of heat acquired by the connection portion adjacent to the substrate 101 and the amount of heat acquired by the connection portion distant from the substrate 101 is relatively small, so that the bonding effect between the adjacent chips 102 and the bonding effect between the chips 102 and the substrate 101 are relatively good; when the number of stacked layers of the chip 102 is large, the difference between the heat acquired by the first connection portion 105 and the heat acquired by the second connection portion 106 is relatively large, and the difference between the heat acquired by the connection portion close to the substrate 101 and the heat acquired by the connection portion far from the substrate 102 is relatively large, so that the problems that the first connection portion 105 and the second connection portion 106 fail to be bonded or the first connection portion 105 fails to be bonded and the second connection portion 106 fails to be bonded in the chip 102 close to the substrate 101 are likely to occur.
The utility model provides a stack packaging structure, stack packaging structure includes the base plate and a plurality of chips that set up on the base plate, wherein, have the electrically conductive through-hole that runs through the chip in the chip, the chip includes relative first face and second face, the second face is provided with the device layer, be provided with first solder part, second solder part between adjacent chip, be provided with first conductive part, second conductive part and heat conduction portion at the first face, wherein, first conductive part and first solder part, in order to connect adjacent chip electrically, second conductive part is with second solder part contact, and heat conduction portion and second conductive part contact, heat conduction portion is used for producing heat and conducts to the second conductive part, thereby in the bonding process, the temperature difference of first solder part and second solder part bonding is less, the contact between the second solder part that the bonding formed and the second conductive part is more firm, the form difference of first solder part and the second solder part that the bonding formed is less, stack packaging structure's performance can improve.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the following embodiments.
Fig. 2 is a schematic cross-sectional structure diagram of a package on package structure provided in an embodiment of the disclosure, fig. 3 is a schematic top-view structure diagram of a chip in a package on package structure provided in an embodiment of the disclosure, fig. 4 is a schematic top-view structure diagram of a chip in another package on package structure provided in an embodiment of the disclosure, fig. 5 is a schematic top-view structure diagram of a chip in another package on package structure provided in an embodiment of the disclosure, fig. 6 is a schematic top-view structure diagram of a chip in another package on package structure provided in an embodiment of the disclosure, and fig. 7 is a schematic top-view structure diagram of a chip in another package on package structure provided in an embodiment of the disclosure.
Referring to fig. 2, the package on package structure 200 includes: the chip-on-chip packaging structure comprises a substrate 201 and a plurality of chips 202 stacked on the substrate 201, wherein the chips 202 comprise a first surface 202a and a second surface 202b which are opposite to each other, a device layer 203 is arranged on the second surface 202b, and a conductive through hole 204 penetrating through the chips 202 is formed in each chip 202; a first conductive portion 205 and a second conductive portion 206, wherein the first conductive portion 205 and the second conductive portion 206 are disposed on the first surface 202a, and the first conductive portion 205 is in contact with the conductive through hole 204; a heat conduction portion 207, the heat conduction portion 207 being disposed on the first surface 202a and contacting the second conductive portion 206; a first solder portion 208 located between adjacent chips 202, and the first solder portion 208 is in contact with the first conductive portion 205 to electrically connect the adjacent chips 202; a second solder portion 209 located between adjacent chips 202, the second solder portion 209 being in contact with the second conductive portion 206; the first solder part 208 and the second solder part 209 are located on the surface of the device layer 203 of the second surface 202 b.
It can be understood that, since the bond head (not shown) is located above all the chips 202 and is in contact with the chip 202 farthest from the substrate 201, in the process of forming the stacked package structure 200, heat generated by the bond head is conducted from the chip 202 farthest from the substrate 201 to the substrate 201, since both ends of the conductive through hole 204 are in contact with the first solder portion 208 and the first conductive portion 205, respectively, the heat is directly conducted to the first solder portion 208 through the adjacent conductive through hole 204 and the adjacent first conductive portion 205, while the second solder portion 209 obtains heat through the adjacent chip 202, the adjacent device layer 203 and the second conductive portion 206, and the thermal resistance of the first solder portion 208 is smaller than that of the second solder portion 209, so that, in the same bonding time, the heat obtained by the bond head is larger for the first solder portion 208 than for the second solder portion 209, since the conductive portion 207 is in contact with the second conductive portion 206, and the second conductive portion 206 is in contact with the second solder portion 209, so that the difference between the heat generated by the bond portion 207 and the second conductive portion 206, and the solder portion 209, can be compensated by the difference between the stacked package structure 200 and the solder portion 209, and the solder portion 207.
The stack package structure 200 may include a Memory package structure, which may be a Dynamic Random Access Memory (DRAM) package structure, a Static Random Access Memory (SRAM) package structure, or a Magnetic Random Access Memory (MRAM) package structure.
The substrate 201 may be a Printed Circuit Board (PCB), a flexible substrate, a tape substrate, or the like, and in some embodiments, the substrate 201 may also be a multi-Circuit board having through holes and various Circuit elements therein. In other embodiments, the substrate 201 may also be a carrier board for carrying the chip 202 and the solder part.
In some embodiments, the plurality of chips 202 may be the same kind of chip 201, and the chips 202 may be memory chips, for example, each chip 202 is a dynamic random access memory chip, a static random access memory chip, or a magnetoresistive random access memory chip. In other embodiments, plurality of chips 202 may include different kinds of chips 201. For example, some of the plurality of chips 202 may be logic chips, and other chips 202 may be memory chips. For example, each of the logic chips may be a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, or an Application Processor (AP) chip. In other embodiments, a plurality of through holes may be disposed in each of the substrate 201 and the chip 202, and the through holes penetrate through the substrate 201, the chip 202, and the device layer 203, wherein the device layer 203 may be a redistribution layer, conductive materials may be filled in the through holes, and the through holes may electrically connect each of the chip 202 and the substrate 201 through wires.
The conductive via 204 may penetrate through the device layer 203 on the chip 202 and the second surface 202b, and the conductive via 204 is in contact with the first conductive portion 205, and the first conductive portion 205 is in contact with the first solder portion 208 to electrically connect the chips 202.
The material of the first conductive portion 205 and the material of the second conductive portion 206 may be the same, and the material of the first conductive portion 205 and the material of the second conductive portion 206 may be a metal material such as copper, gold, or aluminum. It is understood that in other embodiments, the material of the first conductive portion 205 and the material of the second conductive portion 206 may be different.
The material of the first solder part 208 and the material of the second solder part 209 may be the same such that the melting temperature of the first solder part 208 is the same as the melting temperature of the second solder part 209, wherein the material type of the first solder part 208 and the material type of the second solder part 209 may be tin-copper, lead-copper, tin-silver-copper, tin-lead-copper, tin-bismuth-copper, or the like.
It is understood that in other embodiments, the material of the first solder part 208 and the material of the second solder part 209 may be different, and the first solder part 208 may adopt a material with a melting temperature higher than that of the second solder part 209, so as to adapt to a phenomenon that the heat conducted by the bond head to the first solder part 208 is greater than that conducted to the second solder part 209 during the process of forming the first solder part 208 and the second solder part 209, thereby reducing the difference in form between the formed first solder part 208 and the formed second solder part 209, and reducing the heat required by the heat conduction part 207 to supply the heat for forming the second solder part 209 during the process of forming the stacked package structure 200, which saves cost.
The first solder portion 208 may include a first solder 210 and a first conductive bump 211, the first solder 210 is disposed between the first conductive bump 211 and the first conductive portion 205, the first conductive bump 211 is disposed on the surface of the device layer 203 on the second surface 202b, and the first solder 210 connects the first conductive portion 205 and the first conductive bump 211. The material of the first solder 210 may be tin, lead, tin-silver-copper, tin-lead, or tin-bismuth, etc., and the material of the first conductive bump 211 may be copper.
The second solder portion 209 may include a second solder 212 and a second conductive bump 213, the second solder 212 is disposed between the second conductive portion 206 and the second conductive bump 213, and the second conductive bump 213 is disposed on the surface of the device layer 203 on the second side 202 b. The material of the second solder 212 may be tin, lead, tin-silver-copper, tin-lead, or tin-bismuth, etc., and the material of the second conductive bump 213 may be copper.
In some embodiments, the material of the first solder 210 and the material of the second solder 212 may be the same, and may be, for example, tin, lead, tin-silver-copper, tin-lead, tin-bismuth, or the like.
In some embodiments, the material of the first conductive bump 211 and the material of the second conductive bump 213 may be the same, for example, copper.
Referring to fig. 3 to 6, the heat conduction portion 207 is disposed around an edge of the first surface 202a, and the heat conduction portion 207 may include a first end 207a and a second end 207b at the end and the first end 207a is adjacent to the second end 207 b.
Specifically, referring to fig. 3, the thermal conduction portion 207 of the same layer may be disposed on the periphery of all solder portions of the same layer, and compared to the solder portions of the same layer, the thermal conduction portion 207 may be located at an edge portion of the first surface 202a to prevent the thermal conduction portion 207 from affecting arrangement of the solder portions, on the other hand, the thermal conduction portion 207 of the same layer may be square, and have a length and a width, and the head and the tail of the thermal conduction portion 207 may have a first end 207a and a second end 207b opposite to each other, so that during forming the stacked package structure 200, the first end 207a and the second end 207b may contact probes of a current source device (not shown) to enable the thermal conduction portion 207 to obtain current and generate resistance heat, and assist the second solder portion 209 to be bonded to the second conductive portion 206 to improve bonding success rate of the second solder portion 209 and the second conductive portion 206, which is beneficial for improving reliability of the formed stacked package structure 200. The material of the thermal conductive portion 207 may include a metal material providing resistance heat, and the metal material may be at least one of silver, copper, nickel, aluminum, or cobalt.
It is understood that the heat conduction portion 207 of the same layer may be segmented, each segmented heat conduction portion 207 has a first end 207a and a second end 207b, and referring to fig. 4, in some embodiments, the heat conduction portion 207 of the same layer may have a first heat conduction portion 217 and a second heat conduction portion 218, wherein the first heat conduction portion 217 and the second heat conduction portion 218 have opposite openings, the first heat conduction portion 217 and the second heat conduction portion 218 have a first end 207a and a second end 207b, the first ends 207a of the first heat conduction portion 217 and the second end 207b of the second heat conduction portion 218 are adjacent, so that in the process of forming the stacked package structure 200, the difference of heat generated by the heat conduction portion 207 is smaller for the solder portions of the same layer in different areas of the second solder portion 209, and the difference of morphology of the plurality of second solder portions 209 formed is reduced.
Referring to fig. 5, the heat conducting portion 207 may further include a plurality of linear portions 214 arranged at intervals and a plurality of bent portions 215, wherein each bent portion 215 is connected between adjacent linear portions 214, and the bent portion 215 is bent toward the edge direction close to the first surface 202a, so that the heat conducting portion 207 has a larger resistance value, and thus the heat conducting portion 207 may generate more heat.
The bending shape of the bending portion 215 may be a zigzag shape, so that the thermal conductive portion 207 has a larger resistance value, and the thermal conductive portion 207 can provide more heat. Referring to fig. 5, in some embodiments, the bending shape of the bending portion 215 may be a dogleg shape having a square protrusion; referring to fig. 6, in other embodiments, the bending shape of the bending portion 215 may be a dogleg shape having a "V" shaped protrusion.
Referring to fig. 7, the bent shape of the bent portion 215 may also be an arc shape, so that the heat conduction portion 207 has a larger resistance value, and thus the heat conduction portion 207 may generate more heat.
In some embodiments, the thermal conduction portion 207 may further include a connection portion 216, and the thermal conduction portion 207 contacts the second conductive portion 206 through the connection portion 216.
The first surface 202a of the same chip 202 may have a plurality of second conductive portions 206, and the same thermal conductive portion 207 is in contact with the plurality of second conductive portions 206.
In some embodiments, the same layer of conductive portions, the first conductive portion 205 may be disposed in the middle area of the first surface 202a, the second conductive portion 206 may be disposed in the edge area of the first surface 202a, and the second conductive portion 206 is disposed adjacent to the thermal conductive portion 207, in some embodiments, the same layer of conductive portions, the first conductive portion 205 may be disposed in the middle area of the first surface 202a, the second conductive portion 206 is located in the edge area of the first surface 202a compared to the position of the first conductive portion 205, and all of the second conductive portions 206 may be disposed between the thermal conductive portion 207 and the first conductive portion 205, and the second conductive portion 206 is close to the thermal conductive portion 207.
In some embodiments, the same chip 202 first side 202a, the second conductive portion 206 may include a plurality of third conductive portions 206a, a plurality of fourth conductive portions 206b, the third conductive portions 206a being disposed between the first conductive portion 205 and the fourth conductive portions 206b, the third conductive portions 206a being in contact with the conductive portions 207 through the connection portions 216, and the fourth conductive portions 206b being in contact with the third conductive portions 206a through the connection portions 216.
It is understood that the thermal conductive portion 207 may also directly contact all of the second conductive portions 206 on the first surface 202a of the same chip 202.
In some embodiments, in the same layer of conductive portions, the first conductive portion 205 may be disposed in a middle region of the first surface 202a3, compared with the position of the first conductive portion 205, the second conductive portion 206 is disposed in an edge region of the first surface 202a, a part of the second conductive portion 206 may be disposed on a side of the thermal conductive portion 207 close to the first conductive portion 205, the rest of the second conductive portion 206 may be disposed on a side of the thermal conductive portion 207 facing away from the first conductive portion 205, and all the second conductive portions 206 are disposed close to the thermal conductive portion 207, so that materials for contact portions of the second conductive portion 206 and the thermal conductive portion 207 may be reduced, and cost may be saved.
It is also understood that the first conductive portion 205 may not be disposed in the middle region of the first surface 202a, the second conductive portion 206 may not be disposed in the edge region of the first surface 202a, each two conductive portions disposed on the device layer 203 may include one first conductive portion 205 and one second conductive portion 206, and the conductive portion 207 contacts the second conductive portion 206.
In some embodiments, the second side 202b of each chip 202 may be provided with a plurality of device layers 203, wherein a plurality of device layers 203, first solders 208 and second solders 209 on the same chip 202, and the first solders 208 and the second solders 209 may be located on the surface of the device layers 203 farthest from the second side 202 b.
The first and second conductive portions 205 and 206 may also be located on the surface of the substrate 201 facing the chip 202; the thermal conductive portion 207 may also be located on the surface of the substrate 201 facing the chip 202, and contact the second conductive portion 206 on the substrate 201; the first solder portion 208 may also be located between the substrate 201 and the chip 202 adjacent to the substrate 201, and in contact with the first conductive portion 205 on the substrate 201 and the device layer 203 adjacent to the substrate 201 to electrically connect the substrate 201 and the chip 202; the second solder portion 209 may also be located between the substrate 201 and the chip 202 adjacent to the substrate 201, and in contact with the second conductive portion 206 on the substrate 201 and the device layer 203 adjacent to the substrate 201. The arrangement is such that the substrate 201 and the chip 202 are connected by the solder portion, and due to the arrangement of the thermal conduction portion 207, the heat generated by the thermal conduction portion 207 participates in the bonding process of the second solder portion 209 during the bonding process, so that the contact between the formed second solder portion 209 and the second conductive portion 206 is firmer, thereby improving the reliability of the stacked package structure 200.
The stacked package structure 200 provided by the embodiment of the present disclosure is provided with a first solder portion 208 and a second solder portion 209 between a substrate 201 and a chip 202, the chip 202 has a conductive through hole 204 penetrating the chip 202 therein, a device layer 203 is provided on a second surface 202b of the chip 202, and a first conductive portion 205, a second conductive portion 206 and a thermal conductive portion 207 are provided on the first surface 202a, wherein the first conductive portion 205 is connected to the first solder portion 208, the first solder portion 208 is connected to the conductive through hole 204 to electrically connect adjacent chips 202, and the second solder portion 209 is in contact with the thermal conductive portion 207, so that during a bonding process, the thermal conductive portion 207 generates heat and conducts the heat to the second conductive portion 206, and assists the second conductive portion 206 to be bonded to the second solder portion 209, thereby forming the second solder portion 209 and the second conductive portion 206 having better bonding stability, which is beneficial for improving reliability of the stacked package structure 200.
Accordingly, another embodiment of the present disclosure further provides a method for manufacturing a package on package structure, in which the package on package structure provided in the foregoing embodiment can be formed, and a semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the drawings. Fig. 8 and 9 are schematic cross-sectional views corresponding to steps of a method for manufacturing a package on package structure according to another embodiment of the disclosure.
Referring to fig. 8, a plurality of chips 202 are provided, wherein the substrate 201 is stacked on the substrate 201, wherein the chips 202 may have a first side 202a and a second side 202b opposite to each other, the second side 202b is formed with a device layer 203, and conductive vias 204 penetrating the chips 202 are formed in the chips 202.
A plurality of through holes may be formed in the substrate 201 and the chip 202, and the through holes may penetrate through the substrate 201, the chip 202, and the device layer 203 on the chip 202.
A first conductive portion 205 and a second conductive portion 206 may be formed on the first surface 202a, and the first conductive portion 205 is in contact with the conductive via 204; a thermal conductive portion 207 is formed, and the thermal conductive portion 207 is located on the first surface 202a and contacts the second conductive portion 206.
Specifically, the process of forming the thermal conductive portion 207 is the same as the process of forming the first conductive portion 205 and the second conductive portion 206, that is, the thermal conductive portion 207, the first conductive portion 205 and the second conductive portion 206 are formed in the same process, and the process of forming the first conductive portion 205 and the second conductive portion 206 may be a plasma sputtering process, an evaporation process or an electroplating process.
A first initial solder portion 301 and a second initial solder portion 302 may be formed between adjacent chips 202, the first initial solder portion 301 being in contact with the first conductive portion 205 and the device layer 203, and the second initial solder portion 302 being in contact with the second conductive portion 206 and the device layer 203.
Specifically, the first initial solder portion 301 may include a first initial solder 303 and a first conductive bump 211, the first initial solder 303 is formed between the first conductive portion 205 and the first conductive bump 211, the first conductive bump 211 is formed on the surface of the device layer 203 on the second side 202b, and the first conductive bump 211 is in contact with the conductive via 204, the second initial solder portion 302 may include a second initial solder 304 and a second conductive bump 213, the second initial solder 304 is formed between the second conductive portion 206 and the second initial conductive bump 213, and the second conductive bump 213 is formed on the surface of the device layer 203 on the second side 202 b.
In some embodiments, a first conductive portion 205 and a second conductive portion 206 are formed on the surface of the device layer 203 on the substrate 201; forming a thermal conduction portion 207 on a surface of the substrate 201 facing the chip 202, the thermal conduction portion 207 contacting the second conductive portion 206 on the substrate 201; a first initial solder part 301 and a second initial solder part 302 are formed between the substrate 201 and the chip 202 adjacent to the substrate 201, the first initial solder part 301 is in contact with the first conductive part 205 on the substrate 201 and the device layer 203 adjacent to the substrate 201, and the second initial solder part 302 is in contact with the second conductive part 206 on the substrate 201 and the device layer 203 adjacent to the substrate 201, so that after the subsequent bonding process, the substrate 201 and the chip 202 can be fixedly connected, and the reliability of the formed stacked package structure 200 is increased.
Referring to fig. 9, a bonding process 11 is performed to convert a first initial solder portion 301 into a first solder portion 208 secured to a first conductive portion 205 and a device layer 203, to convert a second initial solder portion 302 into a second solder portion 209 secured to a second conductive portion 206 and the device layer 203, and in the bonding process 11 step, a current is supplied to the heat conductive portion 207 to cause the heat conductive portion 207 to generate heat. In this way, the heat generated by the thermal conduction portion 207 assists the bonding of the second initial solder portion 302 with the second conductive portion 206 and the device layer 203, so as to improve the bonding success rate of the second initial solder portion 302, reduce the morphological difference between the formed second solder portion 209 and the first solder portion 208, and facilitate the improvement of the performance of the package on package structure.
A bond head 305 may be disposed above all the chips 202, and the bond head 305 is connected to the chips 202 through the first conductive portion 205 and the second conductive portion 206, so that in the step of the bonding process 11, heat generated by the bond head 305 is conducted from the chip 202 adjacent to the bond head 305 toward the substrate 201, and the heat is partially lost in the conducting process, so that the heat generated by the bond head 305 is gradually reduced from heat obtained by the chip 202 adjacent to the bond head 305 to the substrate 201 in the conducting process.
It can be understood that, since the first initial solder portion 301 is in contact with the conductive via 204, during the bonding process 11, the first initial solder portion 301 directly obtains the heat provided by the bond head 305 through the adjacent first conductive portion 205 and the adjacent conductive via 204, and the second initial solder portion 302 obtains the heat provided by the bond head 305 through the conduction of the adjacent chip 202, the adjacent device layer 203 and the adjacent second conductive portion 206, the thermal resistance of the heat transmission path of the first initial solder portion 301 is smaller than that of the heat transmission path of the second initial solder portion 302, so that the heat obtained by the first initial solder portion 301 is larger than that obtained by the second initial solder portion 302 in the heat provided by the bond head 305 in the same bonding time.
The thermal conductive portion 207 is disposed around an edge of the first surface 202a of the chip 202, and the thermal conductive portion 207 may include a first end 207a and a second end 207b at an end-to-end, and the first end 207a is adjacent to the second end 207b, and during the bonding process 11, an electric current source device (not shown) is provided to transmit electric current to the thermal conductive portion 207, wherein the electric current source device has a first type of probe (not shown) connected to an anode of the electric current source device and a second type of probe (not shown) connected to a cathode of the electric current source device, and the first end 207a and the second end 207b are respectively in contact with the first type of probe and the second type of probe, so that the thermal conductive portion 207 obtains electric current through the probes and generates resistive heat, and the resistive heat generated by the thermal conductive portion 207 is thermally conducted to the second initial solder portion 302 to reduce heat provided by the bonding head 305, and the heat obtained by the second initial solder portion 302 is smaller than the heat obtained by the first initial solder portion 301, thereby improving the reliability of the second initial solder portion 302 converted into the second solder portion 209, and improving the reliability of the stacked package structure and the yield.
In some embodiments, a first chip, a second chip, a third chip and a fourth chip may be sequentially stacked on the substrate 201, wherein in the step of bonding process 11, the heat conduction portion 207 on the first chip generates more heat than the heat conduction portion 207 on the second chip, and the heat conduction portion 207 on the second chip generates more heat than the heat conduction portion 207 on the third chip. With such an arrangement, the heat conduction portion 207 provides different heat according to different heat obtained by the solder portions of different layers, so that the second initial solder portion 302 with less heat provided by the bond head 305 obtains relatively more heat, and the second initial solder portion 302 with more heat provided by the bond head 305 obtains relatively less heat, which is not only beneficial to improving the bonding success rate of all the second initial solder connection portions 302, but also can ensure that all the formed solder portions have small form difference.
In the manufacturing method of the stacked package structure 200 provided by the embodiment of the present disclosure, the thermal conduction portion 207 is formed on the first surface 202a, and the thermal conduction portion 207 is in contact with the second conductive portion 206, so that in the step of performing the bonding process 11, the thermal conduction portion 207 generates heat and conducts the heat to the second conductive portion 206, and assists the second conductive portion 206 to be bonded with the second initial solder portion 302 and the device layer 203, so as to reduce a difference between the heat conducted to the second initial solder portion 302 and the heat of the first initial solder portion 301 in the heat provided by the bonding head 303 in the same bonding time, so as to improve a bonding success rate of the second initial solder portion 302, and reduce a morphological difference between the formed first solder portion 205 and the formed second solder portion 206, thereby being beneficial to improving reliability of the stacked package structure 200.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and the scope of the present disclosure should be defined only by the appended claims.

Claims (15)

1. A package on package structure, comprising:
the chip comprises a substrate and a plurality of chips which are stacked on the substrate, wherein the chips comprise a first surface and a second surface which are opposite, the second surface is provided with a device layer, and the chips are internally provided with conductive through holes which penetrate through the chips;
the first conductive part and the second conductive part are arranged on the first surface, and the first conductive part is in contact with the conductive through hole;
a heat conduction portion disposed on the first surface and contacting the second conductive portion;
a first solder part located between the adjacent chips, and contacting the first conductive part to electrically connect the adjacent chips;
a second solder part located between the adjacent chips, and the second solder part is in contact with the second conductive part; wherein the first solder part and the second solder part are positioned on the surface of the device layer of the second surface.
2. The package on package structure of claim 1, wherein the thermal conduction portion is disposed around an edge of the first side, the thermal conduction portion includes a first end and a second end at a front end and a rear end, and the first end is adjacent to the second end.
3. The package on package structure of claim 1, wherein the thermal conductor comprises: a plurality of linear parts arranged at intervals; each bent part is connected between the adjacent linear parts and bent towards the edge direction close to the first surface.
4. The stacked package structure of claim 3, wherein the bending shape of the bending portion comprises a fold line shape or an arc shape.
5. The package on package structure of claim 1, wherein the first side of the same chip has a plurality of the second conductive portions, and the same thermal conductive portion is in contact with the plurality of second conductive portions.
6. The package on package structure of claim 1, wherein the material of the thermal conductor comprises a metal material providing resistive heat.
7. The package on package structure of claim 1, wherein a material of the first conductive portion is the same as a material of the second conductive portion.
8. The package on package structure of claim 1, wherein the first conductive portion and the second conductive portion are further located on a surface of the substrate facing the chip; the heat conducting part is also positioned on the surface of the substrate facing the chip and is in contact with the second conducting part on the substrate; the first solder portion is also located between the substrate and the chip adjacent to the substrate and in contact with the first conductive portion on the substrate and the device layer adjacent to the substrate to electrically connect the substrate and the chip; the second solder portion is also located between the substrate and the chip adjacent to the substrate and in contact with the second conductive portion on the substrate and the device layer adjacent to the substrate.
9. The package on package structure of claim 1, wherein a material of the first solder portion is the same as a material of the second solder portion.
10. The package on package structure of claim 1, wherein a plurality of vias are disposed within the substrate and the chip, the vias extending through the substrate, the chip, and the device layer.
11. The package on package structure of claim 1, wherein the second side of each of the chips is provided with a plurality of the device layers, wherein the plurality of device layers, the first solder portion, and the second solder portion on the same chip are located on a surface of the device layer farthest from the second side.
12. A method for manufacturing a package on package structure includes:
providing a substrate and a plurality of chips stacked on the substrate, wherein the chips are provided with a first surface and a second surface which are opposite, a device layer is formed on the second surface, and a conductive through hole penetrating through the chips is formed in each chip;
forming a first conductive part and a second conductive part on the first surface, wherein the first conductive part is in contact with the conductive through hole;
forming a heat conduction portion which is located on the first surface and contacts the second conductive portion;
forming a first initial solder portion and a second initial solder portion between adjacent ones of the chips, the first initial solder portion being in contact with the first conductive portion and the device layer, the second initial solder portion being in contact with the second conductive portion and the device layer;
performing a bonding process to convert the first initial solder portion into a first solder portion secured to the first conductive portion and the device layer and to convert the second initial solder portion into a second solder portion secured to the second conductive portion and the device layer, and in the bonding process step, supplying an electric current to the heat conductive portion to cause the heat conductive portion to generate heat.
13. The method of manufacturing a package on package structure of claim 12, wherein a process of forming the thermal conduction portion is the same as a process of forming the first conductive portion and the second conductive portion.
14. The method of manufacturing a package on package structure of claim 12, further comprising: forming the first conductive part and the second conductive part on the surface of the substrate facing the chip; forming the thermal conduction portion on a surface of the substrate facing the chip, the thermal conduction portion being in contact with the second conductive portion on the substrate; forming the first initial solder portion and a second initial solder portion between the substrate and the chip adjacent to the substrate, the first initial solder portion being in contact with the first conductive portion on the substrate and the device layer adjacent to the substrate, the second initial solder portion being in contact with the second conductive portion on the substrate and the device layer adjacent to the substrate.
15. The method of manufacturing a package on package structure according to claim 12, wherein a first chip, a second chip, a third chip, and a fourth chip are stacked on the substrate in this order, and wherein in the bonding process step, the heat conduction portion on the first chip generates more heat than the heat conduction portion on the second chip, and the heat conduction portion on the second chip generates more heat than the heat conduction portion on the third chip.
CN202211159597.5A 2022-09-22 2022-09-22 Stack package structure and manufacturing method thereof Pending CN115425015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211159597.5A CN115425015A (en) 2022-09-22 2022-09-22 Stack package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211159597.5A CN115425015A (en) 2022-09-22 2022-09-22 Stack package structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115425015A true CN115425015A (en) 2022-12-02

Family

ID=84203765

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211159597.5A Pending CN115425015A (en) 2022-09-22 2022-09-22 Stack package structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN115425015A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116313946A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Temperature adjusting system and adjusting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116313946A (en) * 2023-05-24 2023-06-23 长鑫存储技术有限公司 Temperature adjusting system and adjusting method
CN116313946B (en) * 2023-05-24 2023-10-17 长鑫存储技术有限公司 Temperature adjusting system and adjusting method

Similar Documents

Publication Publication Date Title
US7652362B2 (en) Semiconductor package stack with through-via connection
US5804872A (en) Film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof
KR102065008B1 (en) Stack type semiconductor package
US7706148B2 (en) Stack structure of circuit boards embedded with semiconductor chips
CN102456677A (en) Packaging structure for ball grid array and manufacturing method for same
CN111739885B (en) Electromagnetic shielding structure, electromagnetic shielding structure manufacturing method and electronic product
US11721679B2 (en) Semiconductor package and method of fabricating the same
JPH09129817A (en) Semiconductor device
CN211150513U (en) Package body
JP2005011837A (en) Semiconductor device, substrate therefor, and its manufacturing method
US20020189853A1 (en) BGA substrate with direct heat dissipating structure
CN115425015A (en) Stack package structure and manufacturing method thereof
JPS6352432A (en) Semiconductor device
CN111524868A (en) Combined structure of lead frame and metal clamping piece and riveting and chip mounting process
JP2023514986A (en) Package substrate and package structure
CN113707621B (en) Semiconductor packaging structure and preparation method thereof
CN115346946A (en) Stack package structure and manufacturing method thereof
CN114334857A (en) Chip packaging structure and method
CN211351246U (en) Laser unit and laser module
CN217507308U (en) Semiconductor packaging device
JP2722451B2 (en) Semiconductor device
CN216902931U (en) Anti-deformation core plate
US9018759B2 (en) Semiconductor package substrate and semiconductor package including the same
JPH02134859A (en) Multi-chip semiconductor device and manufacture
US20240030171A1 (en) Semiconductor package with hybrid wire bond and bump bond connections

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination