CN115333556B - High-speed receiving and transmitting system based on MIPI protocol - Google Patents
High-speed receiving and transmitting system based on MIPI protocol Download PDFInfo
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- CN115333556B CN115333556B CN202210955914.8A CN202210955914A CN115333556B CN 115333556 B CN115333556 B CN 115333556B CN 202210955914 A CN202210955914 A CN 202210955914A CN 115333556 B CN115333556 B CN 115333556B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
The application provides a high-speed receiving module and a vehicle-mounted video transmission chip based on MIPI protocol, wherein the high-speed receiving module comprises: a second set of amplifiers consisting of a first amplifier and a second amplifier; a signal from a first output of the first stage amplifier is input from a positive input of the first amplifier and from a negative input of a second amplifier; a signal from the second output end of the first stage amplifier is input from the negative input end of the first amplifier and from the positive input end of the second amplifier; outputting a first signal from the first amplifier and a second signal from the second amplifier; and the first signal input from the first input end of the inverting structure and the second signal input from the second input end of the inverting structure are subjected to inverter cross processing to obtain a differential signal, and one path of forward signal or reverse signal is output from the output end OUT. The application obviously optimizes the clock jitter value and improves the product yield.
Description
Technical Field
The embodiment of the application relates to the technical field of vehicle-mounted video transmission chips, in particular to a high-speed receiving module based on MIPI (Mobile industry processor interface) protocol and a vehicle-mounted video transmission chip.
Background
In the high-speed transmission process of vehicle-mounted video data, along with the continuous improvement of video data precision, continuous increase of pixel quantity and continuous improvement of video transmission rate, higher requirements are also put forward on the performance of a receiving module, according to technical indexes defined by MIPI protocol, the range of a common mode voltage VCM of a high-speed serial signal input signal received by the receiving module is 70 mV-330 mV, the range of an amplitude VID is 140 mV-260 mV, and the receiving module needs to convert the input signal into output signals with high and low levels of 1.1V and 0V respectively under the condition of 2.5Gbps of the input signal, and the output signals are converted into 8 paths of parallel signals through serial conversion and are output to a digital module for processing.
The existing high-speed receiving module discovers that the jitter value is too large through process angle and Monte Carlo verification, and influences the product yield.
Disclosure of Invention
In order to solve the technical problems, the application provides a high-speed receiving and transmitting system based on an MIPI protocol, which obviously optimizes the jitter value of a high-speed receiving module by adopting a differential design, so that the jitter value of Monte Carlo verification is smaller than 0.1UI (one UI represents one bit width) under the worst condition, and the product yield is obviously improved.
In a first aspect of the present application, there is provided a high-speed receiving module based on MIPI protocol, comprising:
the first-stage amplifier is used for performing small gain amplification on input signals input from the positive input end INP and the negative input end INN and converting the common mode voltage of the input signals from low voltage to high voltage; wherein the input signal is from a high-speed transmission module;
a second stage amplifier including a first amplifier sec_amp1 and a second amplifier sec_amp2; a signal from a first output of the first stage amplifier is input from a positive input of the first amplifier sec_amp1 and from a negative input of the second amplifier sec_amp2; a signal from the second output of the first stage amplifier is input from the negative input of the first amplifier sec_amp1 and from the positive input of the second amplifier sec_amp2; the first and second amplifiers sec_amp1 and sec_amp2 amplify the input signal with higher gain, and output a first signal from the first amplifier sec_amp1 and a second signal from the second amplifier sec_amp2;
an inverting structure comprising a first input and a second input; and the first signal input from the first input end and the second signal input from the second input end are subjected to inverter cross processing to obtain a differential signal, and one path of forward signal or reverse signal of the differential signal is output from the output end OUT.
Optionally, the inverting structure includes a cross inverter and a multiplexer MUX;
the cross inverter performs inverter cross processing on the input first signal and the second signal, and inputs two paths of differential signals obtained by processing into the multiplexer MUX;
the multiplexer MUX selects one path of forward signal or reverse signal according to preset parameters and outputs the signal from the output end OUT.
Optionally, the cross inverter includes:
the input end of the first inverter is a first input end of an inverting structure INV and is connected with the output end of the first amplifier SEC_AMP 1;
the input end of the second inverter is a second input end of the inverting structure INV and is connected with the output end of the second amplifier SEC_AMP 1;
the cross-coupled inverter consists of a third inverter and a fourth inverter; the input end of the third inverter is connected with the output end of the fourth inverter to serve as a first end of the cross-coupled inverter; the output end of the third inverter is connected with the input end of the fourth inverter to serve as a second end of the cross-coupled inverter; the first end of the cross-coupled inverter is connected with the output end of the second inverter, and the second section is connected with the output end of the second first inverter;
the input end of the fifth inverter is connected with the second end of the cross-coupled inverter, and the output end of the fifth inverter is connected with one input end of the multiplexer MUX;
and the input end of the sixth inverter is connected with the first end of the cross-coupling inverter, and the output end of the sixth inverter is connected with one input end of the multiplexer MUX.
Optionally, the high-speed sending module comprises a triggering unit, a main path unit and a weighted path unit;
the input end of the main channel unit and the input end of the emphasis channel unit are connected with the output end of the trigger unit, so as to respectively receive high-speed data signals DIN through the trigger unit and respectively optimize the high-speed data signals DIN;
the output end of the main path unit is connected with the output end of the emphasis path unit so as to carry out superposition compensation on the optimized high-speed data signal DIN.
Optionally, the trigger unit includes a first trigger DFF1; the D pin of the first trigger DFF1 is used as an input end of a trigger unit and is used for receiving the high-speed data signal DIN; the CK pin of the first trigger DFF1 is used for receiving a clock signal HS_CLK; the RB pin of the first trigger DFF1 is connected with a first power supply VDD to provide power support for the first trigger DFF1 through the first power supply VDD; and the Q pin of the first trigger DFF1 is used as the output end of the trigger unit to be connected with the input ends of the main channel unit and the emphasis channel unit.
Optionally, the main path unit includes a first signal conversion subunit s_to_d1, a first signal optimization subunit d_buf1, a main signal logic conversion subunit reg_buf, a high-speed output driving subunit hs_driver, AND a first logic AND gate AND1;
the input end of the first signal conversion sub-unit S_TO_D1 is connected with the output end of the trigger unit, and is used for receiving a single-ended signal DIN_IN output by the trigger unit and converting the single-ended signal DIN_IN into a main differential signal for output;
the input end of the first signal optimizing subunit D_BUF1 is connected with the output end of the first signal converting subunit S_TO_D1, and is used for receiving the main differential signal, optimizing the main differential signal TO form a main optimizing signal and then outputting the main optimizing signal;
the input end of the main signal logic conversion subunit REG_BUFis connected with the output end of the first signal optimization subunit D_BUF1 and is used for receiving the main optimization signal; the enabling end of the main signal logic conversion subunit reg_buf is connected with the output end of the first logic AND gate AND1, so that the main signal logic conversion subunit reg_buf carries out logic conversion on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output driving subunit HS_DRIVER is connected with the output end of the main signal logic conversion subunit REG_BUF, AND is used for receiving the main optimized signal after logic conversion output by the main signal logic conversion subunit REG_BUF AND changing the equivalent impedance output by the transmitting module under the control action of the first logic AND gate AND1; and the output end of the high-speed output driving subunit HS_DRIVER is connected with the output end of the emphasis path unit.
Optionally, the emphasis path unit includes a second flip-flop DFF2, a second signal conversion subunit s_to_d2, a second signal optimization subunit d_buf2, an emphasis signal logic conversion subunit reg_e_buf, a high-speed output emphasis subunit hs_emp, AND a second logic AND gate AND2;
the input end of the second trigger DFF2 is connected with the output end of the trigger unit and is used for receiving a single-ended signal DIN_IN output by the trigger unit and converting the single-ended signal DIN_IN into an emphasis signal DIN_EMP to be output;
the input end of the second signal conversion subunit s_to_d2 is connected with the output end of the second trigger DFF2, and is used for receiving the emphasis signal din_emp and converting the emphasis signal din_emp into an emphasis differential signal output;
the input end of the second signal optimizing subunit D_BUF2 is connected with the output end of the second signal converting subunit S_TO_D2, and is used for receiving the aggravated differential signal, optimizing the aggravated differential signal TO form an aggravated optimizing signal and then outputting the aggravated optimizing signal;
the input end of the emphasis signal logic conversion subunit REG_E_BUF is connected with the output end of the second signal optimization subunit D_BUF2 and is used for receiving the emphasis optimization signal; the enabling end of the emphasis signal logic conversion subunit reg_e_buf is connected with the output end of the second logic AND gate AND2, so that the emphasis signal logic conversion subunit reg_e_buf performs logic conversion on the emphasis optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the transmitting module;
the input end of the high-speed output emphasis dividing unit HS_EMP is connected with the output end of the emphasis signal logic conversion dividing unit REG_E_BUF, AND is used for receiving the emphasis optimizing signal after logic conversion output by the emphasis signal logic conversion dividing unit REG_E_BUF AND changing the equivalent impedance output by the transmitting module under the control action of the second logic AND gate AND2; and the output end of the high-speed output emphasis unit HS_EMP is connected with the output end of the main channel unit.
In a second aspect of the present application, there is provided a vehicle-mounted video transmission chip comprising the high-speed receiving module as described in the first aspect.
According to the embodiment of the application, the first signal and the second signal with reverse relation are obtained through differential design in the second-stage amplifier, so that when the signal input into the second-stage amplifier has certain deviation, the first signal output by the first amplifier has forward deviation jitter, and the second signal output by the second amplifier has reverse deviation jitter, after the reverse-phase structure of the inverter is subjected to cross processing, complementary offset of jitter errors between the first signal and the second signal is achieved, a differential signal with smaller jitter is obtained, and the jitter value of the high-speed receiving module is effectively optimized, so that the product yield is improved.
It should be understood that the description in this summary is not intended to limit the critical or essential features of the embodiments of the application, nor is it intended to limit the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
The above and other features, advantages and aspects of embodiments of the present application will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:
fig. 1 is a circuit configuration diagram of a conventional high-speed receiving module;
fig. 2 is a circuit configuration diagram of a high-speed receiving module according to an embodiment of the present application;
FIG. 3 is a circuit diagram of a cross inverter according to an embodiment of the present application;
FIG. 4 is an eye diagram waveform of a first signal output by a first amplifier according to an embodiment of the present application;
FIG. 5 is an eye diagram waveform of a second signal output by a second amplifier according to an embodiment of the present application;
FIG. 6 is an eye diagram waveform of an output signal of a cross inverter according to an embodiment of the present application;
FIG. 7 is an eye diagram of a conventional high-speed receiving module verifying three different temperature outputs of-40 deg.C, 45 deg.C, 130 deg.C at all process angles TT, FF, SS, respectively;
fig. 8 is an eye diagram of three different temperature outputs of-40 ℃, 45 ℃ and 130 ℃ respectively verified by the high-speed receiving module provided by the embodiment of the application under all process angles TT, FF and SS;
FIG. 9 is a diagram showing the result of Monte Carlo verification in a conventional high-speed receiver module;
fig. 10 is a monte carlo verification result of the high-speed receiving module according to the embodiment of the present application;
FIG. 11 is a schematic circuit diagram of a high-speed transmission module according to an embodiment of the present application;
fig. 12 is a diagram showing an equivalent circuit of a resistor network formed by the high-speed output driving subunit hs_driver, the high-speed output weighting subunit hs_emp and the resistor-external R2 according to an embodiment of the present application (din_in=1, din_emp=0);
fig. 13 is a diagram showing an equivalent circuit of a resistor network formed by the high-speed output driving subunit hs_driver, the high-speed output weighting subunit hs_emp and the off-chip resistor R2 according to an embodiment of the present application (din_in=1, din_emp=1);
FIG. 14 is a diagram showing DIN_IN, DIN_EMP, and VOD timing relationships according to an embodiment of the application;
FIG. 15 is a waveform and eye diagram of the corresponding output signal when the input signal DIN is a PRBS9 signal of 4.5Gbps without turning on the emphasis path unit according to the embodiment of the application;
fig. 16 shows waveforms and eye diagrams of corresponding output signals when the input signal DIN is a PRBS9 signal of 4.5Gbps after turning on the emphasis path unit according to the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments in this disclosure without inventive faculty, are intended to be within the scope of this disclosure.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
As shown in fig. 1, the circuit structure of the conventional high-speed receiving module adopts two-stage amplification, the first-stage amplifier pre_amp provides small gain amplification, and converts the input common-mode voltage from low voltage to high voltage, so as to ensure that the second-stage amplifier sec_amp inputs NMOS to the pair of transistors to work normally; the second stage amplifier sec_amp provides a higher gain and outputs to and from an inverter. The clock jitter of the final output is relatively large due to non-ideal factors such as device mismatch, process errors and the like.
The application provides a high-speed receiving module based on MIPI protocol, as shown in figure 2, comprising:
the first-stage amplifier PRE_AMP is a PRE-amplifier, and the positive input end and the negative input end of the first-stage amplifier PRE_AMP are respectively a positive input end INP of the high-speed receiving module and a negative input end INN of the high-speed receiving module; the device is used for carrying out small gain amplification on input signals input from a positive input end INP and a negative input end INN, the gain range is generally 8 dB-10 dB, and the common mode voltage of the input signals is converted from low voltage to high voltage; wherein the input signal is from a high-speed transmission module; signals with the amplitude of plus or minus 70mV to plus or minus 130mV according to the MIPI protocol index common mode voltage of 70mV to 330 mV; the common-mode voltage high voltage is a signal output by the first-stage amplifier, and the common-mode voltage is converted into a signal with about 0.9V and an amplitude of about 200 mV.
The second stage amplifier sec_amp includes a first amplifier sec_amp1 and a second amplifier sec_amp2; the signal from the first output terminal of the first stage amplifier pre_amp is input to the first amplifier sec_amp1 from the positive input terminal of the first amplifier sec_amp1 and the second amplifier sec_amp2 from the negative input terminal of the second amplifier sec_amp2; the signal from the second output terminal of the first stage amplifier pre_amp is input to the first amplifier sec_amp1 from the negative input terminal of the first amplifier sec_amp1, and the signal from the positive input terminal of the second amplifier sec_amp2 is input to the second amplifier sec_amp2; the first amplifier sec_amp1 and the second amplifier sec_amp2 amplify the input signal with higher gain (the gain of the second stage amplifier is more than 20dB, so that the signal with smaller input amplitude can be directly converted into a digital signal with 0 to vdd), and the first signal is output from the first amplifier sec_amp1 and the second signal is output from the second amplifier sec_amp2, and the first signal and the second signal are in inverse relation.
The inverting structure INV comprises a first input end and a second input end, and the output end is an output end OUT of the high-speed receiving module; and the first signal input from the first input end and the second signal input from the second input end are subjected to the cross processing of an inverter, so that the complementary offset of the jitter errors of the first signal and the second signal is realized, a differential signal with smaller jitter is obtained, and one path of forward signal or reverse signal is output from the output end OUT.
According to the embodiment of the application, the first signal and the second signal with reverse relation are obtained by adopting differential design in the second-stage amplifier SEC_AMP, so that when the signal input into the second-stage amplifier has certain deviation, the first signal output by the first amplifier has forward deviation jitter, and the second signal output by the second amplifier has reverse deviation jitter, thus after the cross processing of the inverter of the inversion structure INV, the complementary offset of jitter error between the first signal and the second signal is realized, the differential signal with smaller jitter is obtained, and the jitter value of the high-speed receiving module is effectively optimized, thereby improving the product yield.
In this embodiment, the inverting structure INV includes a cross inverter INV-C and a multiplexer MUX, and two input ends of the cross inverter INV-C are used as input ends of the inverting structure INV, and an output end of the multiplexer MUX is used as an output end of the inverting structure INV; the cross inverter INV-C performs inverter cross processing on the input first signal and second signal, and inputs the two differential signals obtained by processing into a multiplexer MUX, and the multiplexer MUX selects one path of forward signal or reverse signal to be output from an output end OUT according to preset parameters (namely through digital control); the forward signal is in phase with the input signal and the reverse signal is in phase with the input signal.
As shown in fig. 3, in some embodiments, the cross inverter INV-C includes six inverters, and the specific structure is as follows:
the input end of the first inverter INV1 is a first input end IP1 of the inverting structure INV and is connected with the output end of the first amplifier sec_amp 1;
the input end of the second inverter INV2 is a second input end IN1 of the inverting structure INV and is connected with the output end of the second amplifier sec_amp 1;
a cross-coupled inverter composed of a third inverter INV3 and a fourth inverter INV 4; the input end of the third inverter INV3 is connected with the output end of the fourth inverter INV4 to serve as a first end of the cross-coupled inverter; the output end of the third inverter INV3 is connected with the input end of the fourth inverter INV4 to serve as a second end of the cross-coupled inverter; the first end of the cross-coupled inverter is connected with the output end of the second inverter INV2, and the second end of the cross-coupled inverter is connected with the output end of the first inverter INV 1;
a fifth inverter INV5, the input end of which is connected with the second end of the cross-coupled inverter, and the output end of which is connected with one input end of the multiplexer MUX;
and the input end of the sixth inverter INV6 is connected with the first end of the cross-coupled inverter, and the output end of the sixth inverter INV is connected with one input end of the multiplexer MUX.
In this embodiment, after the first signal and the second signal input from the cross inverter are respectively inverted through the first inverter and the second inverter, the rising and falling time of the input differential signal is optimized through the cross-coupled inverter, and then the output is respectively shaped through the fifth inverter and the sixth inverter, so that the jitter error between the input first signal and the input second signal is complementary and counteracted, and the purpose of optimizing the waveform eye jitter value of the input signal is achieved. Fig. 4 shows an eye waveform of a first signal output from a first amplifier, fig. 5 shows an eye waveform of a second signal output from a second amplifier, and fig. 6 shows an eye waveform of a cross inverter output signal; the clock jitter values at VDD/2, with fig. 4 eye cross point biased downward and fig. 5 eye cross point biased upward, are 15.22pS and 14.17pS, respectively, for the eye at VDD/2; while FIG. 6 is an eye diagram waveform after cross-inverter cancellation, the clock jitter value at VDD/2 is only 1pS, and the optimization is very obvious.
Taking the input signal rate of 2.5Gbps and the input amplitude of plus or minus 50mV as an example, under the condition of low power supply voltage (vdd=0.99V), the circuit structure of the traditional high-speed receiving module and the high-speed receiving module provided by the application are respectively subjected to process corner and Monte Carlo verification.
And (3) verifying the process angle:
FIG. 7 shows the eye diagrams of the conventional high-speed receiving module respectively verifying three different temperature outputs of-40 ℃, 45 ℃ and 130 ℃ under all process angles TT, FF and SS, wherein the jitter value reaches 22.4pS at maximum;
FIG. 8 shows the eye diagrams of the high-speed receiving module provided by the application, which respectively verify the output at the temperature of-40 ℃, 45 ℃ and 130 ℃ under all process angles TT, FF and SS, wherein the jitter value is 3.9pS at maximum;
therefore, the eye diagram obtained by the process corner verification shows that compared with the circuit structure of the traditional high-speed receiving module, the jitter performance of the high-speed receiving module provided by the application is obviously optimized.
Monte Carlo validation:
FIG. 9 shows the Monte Carlo verification result of a conventional high-speed receiving module, wherein the jitter value of 3sigma is 60.3pS;
FIG. 10 shows the Monte Carlo verification result of the high-speed receiving module provided by the application, wherein the jitter value of 3sigma is 39.8pS, which is smaller than 0.1UI;
therefore, the Monte Carlo verification result shows that compared with the circuit structure of the traditional high-speed receiving module, the jitter performance of the high-speed receiving module provided by the application is obviously optimized.
In summary, under the verification of the process angle and Monte Carlo, the jitter value of the high-speed receiving module provided by the application is obviously optimized, and the performance of the high-speed receiving module is greatly improved, so that the yield of products is effectively improved.
In this embodiment, in order to better ensure the performance of the high-speed receiving module, as shown in fig. 11, the high-speed transmitting module includes a trigger unit 10, a main path unit 20, and a weighted path unit 30; the main path unit 20 and the emphasis path unit 30 are connected in parallel; the input ends of the main path unit 20 and the emphasis path unit 30 are simultaneously connected with the output end of the trigger unit 10 to respectively receive the high-speed data signal DIN through the trigger unit 10 and respectively optimize the high-speed data signal DIN; the output end of the main path unit 20 is connected with the output end of the emphasis path unit 30 to perform superposition compensation on the optimized high-speed data signal DIN; the two connection nodes between the output of the main path unit 20 and the output of the emphasis path unit 30 are connected by an off-chip resistor R2.
In the present application, the input ends of the main path unit 20 and the emphasis path unit 30 are simultaneously connected with the output end of the trigger unit 10, so as to ensure that the high-speed data signals DIN obtained by the input ends of the main path unit 20 and the emphasis path unit 30 are the same; the main path unit 20 and the emphasis path unit 30 respectively perform optimization processing on the obtained high-speed data signal DIN, and then superimpose the optimized high-speed data signal DIN so as to compensate attenuation of the high-speed data signal DIN in a transmission process, thereby being beneficial to optimizing eye pattern quality of the damaged signal. By adopting the high-speed transmitting module with pre-emphasis in the technical scheme, the adjustable emphasis path unit 30 is added, so that the required emphasis amplitude can be adjusted according to actual conditions during use, the attenuation of the high-frequency signal in the transmission process of the high-speed data signal DIN is effectively compensated, and the receiving terminal can obtain a better signal waveform.
In some embodiments of the present application, the trigger unit 10 includes a first trigger DFF1, where the first trigger DFF1 is a class D trigger triggered by a clock rising edge; the D pin of the first flip-flop DFF1 is used as an input terminal of the trigger unit 10 for receiving the high-speed data signal DIN; the CK pin of the first trigger DFF1 is used for receiving a clock signal HS_CLK; the RB pin of the first trigger DFF1 is connected with a first power supply VDD to provide power support for the normal operation of the first trigger DFF1 through the first power supply VDD; the Q pin of the first flip-flop DFF1 serves as an output terminal of the trigger unit 10 and is connected to input terminals of the main path unit 20 and the emphasis path unit 30 at the same time. In the present application, when the rising edge of the clock signal received at the CK pin of the first flip-flop DFF1 comes, the D pin receives the high-speed data signal DIN to be transferred to the Q pin and output via the Q pin.
In some embodiments of the present application, the main path unit 20 includes a first signal conversion subunit s_to_d1, a first signal optimization subunit d_buf1, a main signal logic conversion subunit reg_buf, a high-speed output driving subunit hs_driver, AND a first logic AND gate AND1.
Wherein, the liquid crystal display device comprises a liquid crystal display device,
the input end of the first signal conversion subunit S_TO_D1 is connected with the Q pin of the first trigger DFF1, and is used for receiving a single-ended signal DIN_IN output by the Q pin of the first trigger DFF1 and converting the single-ended signal DIN_IN into a main differential signal output;
the input end of the first signal optimizing sub-unit D_BUF1 is connected with the output end of the first signal converting sub-unit S_TO_D1, and is used for receiving a main differential signal output by the output end of the first signal converting sub-unit S_TO_D1, optimizing the main differential signal TO form a main optimizing signal and then outputting the main optimizing signal;
the input end of the main signal logic conversion subunit REG_BUF1 is connected with the output end of the first signal optimization subunit D_BUF1 and is used for receiving a main optimization signal output by the output end of the first signal optimization subunit D_BUF1; the enabling end (i.e. the driving enabling signal pin en) of the main signal logic conversion subunit reg_buf is connected with the output end of the first logic AND gate AND1, so that the main signal logic conversion subunit reg_buf performs logic conversion on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module (i.e. the equivalent resistance output by the main channel unit 20); the input end of the first logic AND gate AND1 is respectively connected with a driving enable signal en_driver AND a driving register signal reg_driver;
the input end of the high-speed output driving sub-unit HS_DRIVER is connected with the output end of the main signal logic conversion sub-unit REG_BUF, and is used for receiving the logic converted main optimization signal output by the output end of the main signal logic conversion sub-unit REG_BUF and changing the equivalent impedance output by the transmitting module (namely the equivalent impedance output by the main channel unit 20) under the control of the driving register signal reg_driver; the output end of the high-speed output driving subunit hs_driver is connected to the output end of the emphasis path unit 30.
In some embodiments of the present application, the emphasis path unit 30 includes a second flip-flop DFF2, a second signal conversion subunit s_to_d2, a second signal optimization subunit d_buf2, an emphasis signal logic conversion subunit reg_e_buf, a high-speed output emphasis subunit hs_emp, AND a second logic AND gate AND2.
Wherein, the liquid crystal display device comprises a liquid crystal display device,
the input end of the second trigger DFF2 is connected with the output end of the trigger unit 10, and is used for receiving the single-ended signal din_in output by the trigger unit 10 and converting the single-ended signal din_in into an emphasis signal din_emp to be output;
the input end of the second signal conversion subunit S_TO_D2 is connected with the output end of the second trigger DFF2 and is used for receiving the emphasis signal DIN_EMP and converting the emphasis signal DIN_EMP into an emphasis differential signal output;
the input end of the second signal optimizing subunit D_BUF2 is connected with the output end of the second signal converting subunit S_TO_D2, and is used for receiving the aggravated differential signal, optimizing the aggravated differential signal TO form an aggravated optimized signal and then outputting the aggravated optimized signal;
the input end of the emphasis signal logic conversion subunit REG_E_BUF is connected with the output end of the second signal optimization subunit D_BUF2 and is used for receiving the emphasis optimization signal; the enabling end of the emphasis signal logic conversion subunit reg_e_buf is connected with the output end of the second logic AND gate AND2, so that the emphasis signal logic conversion subunit reg_e_buf carries out logic conversion on the emphasis optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output emphasis dividing unit HS_EMP is connected with the output end of the emphasis signal logic conversion dividing unit REG_E_BUF, AND is used for receiving the emphasis optimizing signal after logic conversion output by the emphasis signal logic conversion dividing unit REG_E_BUF AND changing the equivalent impedance output by the transmitting module under the control of the second logic AND gate AND2; the output terminal of the high-speed output emphasis unit hs_emp is connected to the output terminal of the main path unit 20.
Specifically, the D pin of the second flip-flop DFF2 is connected to the Q pin of the first flip-flop DFF1 as an input end of the emphasis path unit 30 to receive the single-ended signal din_in output from the Q pin of the first flip-flop DFF1; the CK pin of the second trigger DFF2 is used for receiving a clock signal HS_CLK; the Q pin of the second trigger DFF2 is connected with the input end of the second signal conversion subunit S_TO_D2 TO convert the single-ended signal DIN_IN into an emphasis signal DIN_EMP and then transmit the emphasis signal DIN_EMP TO the second signal conversion subunit S_TO_D2; the OP pin of the output end of the second signal conversion subunit S_TO_D2 is connected with the IP pin of the input end of the second signal optimization subunit D_BUF2; the ON pin of the output end of the second signal conversion subunit S_TO_D2 is connected with the IN pin of the input end of the second signal optimization subunit D_BUF2; the OP pin of the output end of the second signal optimization subunit D_BUF2 is connected with the IP pin of the input end of the emphasis signal logic conversion subunit REG_E_BUF; the ON pin of the output end of the second signal optimizing subunit d_buf2 is connected with the IN pin of the input end of the emphasis signal logic conversion subunit reg_e_buf; the enabling end (namely an emphasis enabling signal pin en) of the emphasis signal logic conversion subunit reg_e_buf is connected with the output end of the second logic AND gate AND2; the input end of the second logic AND gate AND2 is respectively connected with an emphasis enable signal en_emp AND an emphasis register signal reg_emp; the IP pin of the input end of the high-speed output emphasis unit HS_EMP is connected with the OP pin of the output end of the emphasis signal logic conversion subunit REG_E_BUF, and the IN pin of the input end of the high-speed output emphasis unit HS_EMP is connected with the ON pin of the output end of the emphasis signal logic conversion subunit REG_E_BUF; the OP pin of the output end of the high-speed output emphasis unit HS_EMP is connected with the ON pin of the output end of the high-speed output driving subunit HS_DRIVER; node ON_PAD is formed between the OP pin of the output end of the high-speed output emphasis unit HS_EMP and the ON pin of the output end of the high-speed output driving unit HS_DRIVER, the ON pin of the output end of the high-speed output emphasis unit HS_EMP is connected with the OP pin of the output end of the high-speed output driving unit HS_DRIVER to form node OP_PAD, and the node ON_PAD and the node OP_PAD are connected through an off-chip resistor R2.
In the present application, the internal circuit structure of the emphasis signal logic conversion subunit reg_e_buf is the same as that of the main signal logic conversion subunit reg_buf, and the internal circuit structure of the high-speed output emphasis subunit hs_emp is the same as that of the high-speed output driving subunit hs_driver, which is not described herein again. The multiple groups of trimming subunits UNIT in the high-speed output emphasis UNIT HS-EMP are respectively controlled to work and turn off by the emphasis register signal reg-EMP, so that the effect of controlling the emphasis amplitude is realized. Specifically, the emphasis register signal reg_emp controls the sub-unit of the high-speed output emphasis sub-unit HS_EMP through the OP0/1/2/3 pin of the output end of the emphasis signal logic conversion sub-unit REG_E_BUF and the ON0/1/2/3 pin of the output end; if the enable terminal en0=0 of the emphasis signal logic conversion subunit reg_e_buf, the output terminal op0=0 and on0=0, the corresponding trimming subunit UNIT is controlled to be turned off; if the enable terminal en0=1 of the emphasis signal logic conversion subunit reg_e_buf, the output terminal op0=1, on0=0 or op0=0, on0=1, the corresponding trimming subunit UNIT is controlled to be turned on. It should be noted that, when the enable terminal en0=1 of the emphasis signal logic conversion subunit reg_e_buf, the corresponding trimming subunit UNIT is controlled to be turned ON, the output terminal OP0 is in phase with the delayed input signal, and the ON0 is opposite to the delayed input signal.
In the present application, after the emphasis path unit 30 is turned on, it is assumed that the equivalent resistance output by the main path unit 20 is Rd, and the equivalent resistance output by the emphasis path unit 30 is Re; when the single-ended signal din_in is pulled from low to high, the input IP of the main path unit 20 (i.e., the IP pin of the first signal optimizing subunit d_buf1) is at high level, the input IN (i.e., the IN pin of the first signal optimizing subunit d_buf1) is at low level, and since the first flip-flop DFF1 remains IN the state before din_in before the rising edge of hs_clk, the ip_emp of the emphasis path unit 30 (i.e., the IP pin of the second signal optimizing subunit d_buf2) is at low level, and the in_emp (i.e., the IN pin of the second signal optimizing subunit d_buf2) is at high level; at this time, as shown in fig. 12, the equivalent circuit of the resistor network composed of the high-speed output driving subunit hs_driver, the high-speed output weighting subunit hs_emp and the off-chip resistor R2, the current flows from VLDO through the parallel branch composed of Rd and Re, then flows through the off-chip resistor R2 through the parallel branch composed of Rd and Re, and then is grounded (VSS); the voltage drop across the off-chip resistor R2 is Vh1 = R2 VLDO (1 + rd/Re)/[ 2rd + R2 (1 + rd/Re) ]. When the main path unit 20 is opened, the resistance from the output node P terminal to 0.4VLDO is Rd; when the emphasis path unit 30 is turned on, the resistance of the output node P to 0.4VLDO is Re, so that the equivalent resistance of the node P to 0.4VLDO is Rd in parallel with Re; similarly, the resistances of the output nodes N to VSS are Rd and Re in parallel.
After a high-speed clock period, the rising edge of hs_clk, the output of the first flip-flop DFF1 follows the din_in signal, the ip_emp of the emphasis path UNIT 30 is pulled down, the in_emp is pulled up, the first transistor MN1 and the fourth transistor MN4 of the corresponding trimming subunit UNIT IN the high-speed output emphasis subunit hs_emp are turned off, and the second transistor MN2 and the third transistor MN3 are turned on; at this time, as shown in fig. 13, the equivalent circuit of the resistor network consisting of the high-speed output driving subunit hs_driver, the high-speed output weighting subunit hs_emp and the off-chip resistor R2 has a voltage drop of vh2=r2×vldo (1-Rd/Re)/[ 2rd+r2×1+rd/Re ]. Output |VOD| is reduced by R2.times.VLDO.times.2 Rd/Re/[ 2Rd+R2.times.1+Rd/Re ].
Similarly, when the single-ended signal DIN_IN is pulled from high to low, the voltage drops across the off-chip resistor R2 are-Vh 1 and-Vh 2, respectively, and the timing diagrams of the single-ended signal DIN_IN, the emphasis signal DIN_EMP and the signal VOD are shown IN FIG. 14. By adding the emphasis function, the high-frequency part of the signal is emphasized, and the low-frequency signal is attenuated; by adjusting different emphasis amplitudes, the attenuation of the off-chip signal transmission line to the high-frequency part of the signal can be effectively compensated, and the signal output eye diagram is optimized.
When the high-speed data signal DIN is a PRBS9 signal of 4.5Gbps, the waveform of the output signal and the eye diagram are as shown in fig. 15 without turning on the emphasis path unit 30, and the high-frequency part of the waveform of the output signal is severely attenuated due to the loss on the output signal line, and the eye diagram jitter value is 52pS. After the emphasis path unit 30 is turned on, the waveform of the output signal and the eye diagram are as shown in fig. 16, and it can be seen that the waveform of the output signal is significantly optimized, the eye diagram quality is also improved, and the eye diagram jitter value is 3pS.
The embodiment of the application also provides a vehicle-mounted video transmission chip, which comprises the high-speed receiving module provided by the embodiment of the application.
The vehicle-mounted video transmission chip provided by the embodiment of the application can obviously optimize the clock jitter value through the high-speed receiving module in the embodiment, and effectively improve the product yield.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application is not limited to the specific combinations of the features described above, but also covers other embodiments which may be formed by any combination of the features described above or their equivalents without departing from the spirit of the application. Such as the above-mentioned features and the technical features having similar functions (but not limited to) applied for in the present application are replaced with each other.
Claims (5)
1. A high-speed receiving and transmitting system based on MIPI protocol comprises a high-speed receiving module and a high-speed transmitting module, which is characterized in that the high-speed receiving module comprises a first-stage amplifier, a second-stage amplifier and an inverting structure,
the first-stage amplifier is used for performing small gain amplification on input signals input from the positive input end INP and the negative input end INN and converting the common mode voltage of the input signals from low voltage to high voltage; wherein the input signal is from a high-speed transmission module;
a second stage amplifier including a first amplifier sec_amp1 and a second amplifier sec_amp2; a signal from a first output of the first stage amplifier is input from a positive input of the first amplifier sec_amp1 and from a negative input of the second amplifier sec_amp2; a signal from the second output of the first stage amplifier is input from the negative input of the first amplifier sec_amp1 and from the positive input of the second amplifier sec_amp2; the first and second amplifiers sec_amp1 and sec_amp2 amplify the input signal with higher gain, and output a first signal from the first amplifier sec_amp1 and a second signal from the second amplifier sec_amp2;
an inverting structure comprising a first input and a second input; the first signal input from the first input end and the second signal input from the second input end are subjected to phase inverter cross processing to obtain a differential signal, and one path of forward signal or reverse signal of the differential signal is output from an output end OUT;
the high-speed transmitting module comprises a triggering unit, a main path unit and a weighting path unit;
the input end of the main channel unit and the input end of the emphasis channel unit are connected with the output end of the trigger unit, so as to respectively receive high-speed data signals DIN through the trigger unit and respectively optimize the high-speed data signals DIN;
the output end of the main channel unit is connected with the output end of the emphasis channel unit so as to carry out superposition compensation on the optimized high-speed data signal DIN;
the main path unit comprises a first signal conversion subunit S_TO_D1, a first signal optimization subunit D_BUF1, a main signal logic conversion subunit REG_BUF, a high-speed output driving subunit HS_DRIVER AND a first logic AND gate AND1;
the input end of the first signal conversion sub-unit S_TO_D1 is connected with the output end of the trigger unit, and is used for receiving a single-ended signal DIN_IN output by the trigger unit and converting the single-ended signal DIN_IN into a main differential signal for output;
the input end of the first signal optimizing subunit D_BUF1 is connected with the output end of the first signal converting subunit S_TO_D1, and is used for receiving the main differential signal, optimizing the main differential signal TO form a main optimizing signal and then outputting the main optimizing signal;
the input end of the main signal logic conversion subunit REG_BUFis connected with the output end of the first signal optimization subunit D_BUF1 and is used for receiving the main optimization signal; the enabling end of the main signal logic conversion subunit reg_buf is connected with the output end of the first logic AND gate AND1, so that the main signal logic conversion subunit reg_buf carries out logic conversion on the main optimization signal under the control action of the first logic AND gate AND1 to adjust the equivalent resistance output by the sending module;
the input end of the high-speed output driving subunit HS_DRIVER is connected with the output end of the main signal logic conversion subunit REG_BUF, AND is used for receiving the main optimized signal after logic conversion output by the main signal logic conversion subunit REG_BUF AND changing the equivalent impedance output by the transmitting module under the control action of the first logic AND gate AND1; and the output end of the high-speed output driving subunit HS_DRIVER is connected with the output end of the emphasis path unit.
2. The high-speed transceiver system of claim 1, wherein the inverting structure comprises a cross inverter and a multiplexer MUX;
the cross inverter performs inverter cross processing on the input first signal and the second signal, and inputs two paths of differential signals obtained by processing into the multiplexer MUX;
the multiplexer MUX selects one path of forward signal or reverse signal according to preset parameters and outputs the signal from the output end OUT.
3. The high-speed transceiver system of claim 2, wherein the cross-over inverter comprises:
the input end of the first inverter is a first input end of an inverting structure and is connected with the output end of the first amplifier SEC_AMP 1;
the input end of the second inverter is a second input end of the inverting structure and is connected with the output end of the second amplifier SEC_AMP 1;
the cross-coupled inverter consists of a third inverter and a fourth inverter; the input end of the third inverter is connected with the output end of the fourth inverter to serve as a first end of the cross-coupled inverter; the output end of the third inverter is connected with the input end of the fourth inverter to serve as a second end of the cross-coupled inverter; the first end of the cross-coupled inverter is connected with the output end of the second inverter, and the second end of the cross-coupled inverter is connected with the output end of the first inverter;
the input end of the fifth inverter is connected with the second end of the cross-coupled inverter, and the output end of the fifth inverter is connected with one input end of the multiplexer MUX;
and the input end of the sixth inverter is connected with the first end of the cross-coupling inverter, and the output end of the sixth inverter is connected with one input end of the multiplexer MUX.
4. The high-speed transceiving system according to claim 1, wherein said trigger unit comprises a first trigger DFF1; the D pin of the first trigger DFF1 is used as an input end of a trigger unit and is used for receiving the high-speed data signal DIN; the CK pin of the first trigger DFF1 is used for receiving a clock signal HS_CLK; the RB pin of the first trigger DFF1 is connected with a first power supply VDD to provide power support for the first trigger DFF1 through the first power supply VDD; and the Q pin of the first trigger DFF1 is used as the output end of the trigger unit to be connected with the input ends of the main channel unit and the emphasis channel unit.
5. The high-speed transceiving system according TO claim 1, wherein said emphasis path unit comprises a second flip-flop DFF2, a second signal conversion subunit s_to_d2, a second signal optimization subunit d_buf2, an emphasis signal logic conversion subunit reg_e_buf, a high-speed output emphasis subunit hs_emp, AND a second logic AND gate AND2;
the input end of the second trigger DFF2 is connected with the output end of the trigger unit and is used for receiving a single-ended signal DIN_IN output by the trigger unit and converting the single-ended signal DIN_IN into an emphasis signal DIN_EMP to be output;
the input end of the second signal conversion subunit s_to_d2 is connected with the output end of the second trigger DFF2, and is used for receiving the emphasis signal din_emp and converting the emphasis signal din_emp into an emphasis differential signal output;
the input end of the second signal optimizing subunit D_BUF2 is connected with the output end of the second signal converting subunit S_TO_D2, and is used for receiving the aggravated differential signal, optimizing the aggravated differential signal TO form an aggravated optimizing signal and then outputting the aggravated optimizing signal;
the input end of the emphasis signal logic conversion subunit REG_E_BUF is connected with the output end of the second signal optimization subunit D_BUF2 and is used for receiving the emphasis optimization signal; the enabling end of the emphasis signal logic conversion subunit reg_e_buf is connected with the output end of the second logic AND gate AND2, so that the emphasis signal logic conversion subunit reg_e_buf performs logic conversion on the emphasis optimization signal under the control action of the second logic AND gate AND2 to adjust the equivalent resistance output by the transmitting module;
the input end of the high-speed output emphasis dividing unit HS_EMP is connected with the output end of the emphasis signal logic conversion dividing unit REG_E_BUF, AND is used for receiving the emphasis optimizing signal after logic conversion output by the emphasis signal logic conversion dividing unit REG_E_BUF AND changing the equivalent impedance output by the transmitting module under the control action of the second logic AND gate AND2; and the output end of the high-speed output emphasis unit HS_EMP is connected with the output end of the main channel unit.
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