CN203872144U - Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system - Google Patents
Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system Download PDFInfo
- Publication number
- CN203872144U CN203872144U CN201420261507.8U CN201420261507U CN203872144U CN 203872144 U CN203872144 U CN 203872144U CN 201420261507 U CN201420261507 U CN 201420261507U CN 203872144 U CN203872144 U CN 203872144U
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- inverter
- ended
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 claims description 36
- 230000001934 delay Effects 0.000 abstract description 3
- 230000008054 signal transmission Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000000739 chaotic effect Effects 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model provides a circuit of converting a single-ended signal to a differential signal and a high-speed integrated circuit transmission system. The circuit includes a first signal circuit, a second signal circuit and a delay adjusting circuit, the first signal circuit includes n inverters connected in series, an input end of the first signal circuit receives a single-ended signal, and outputs a first signal after passing through the n inverters connected in series, wherein n is an integer larger than or equal to 1; the second signal circuit includes m inverters connected in series, an input end of the second signal circuit receives a single-ended signal, and outputs an intermediate signal after passing through the m inverters connected in series, the m is an integer larger than or equal to 0, m is smaller than n, and a difference value of n and m is an odd number; and the delay adjusting circuit includes inverters of a difference value number which are connected in series, and the delay adjusting circuit receives the first signal, combines the first signal with the intermediate signal after the first signal passes through the inverters of the difference value number and outputs a second signal. The circuit of converting the single-ended signal to the differential signal provided by the utility model can eliminate difference between output end delays of two signals in the differential signals.
Description
Technical field
The utility model relates to circuit engineering, relates in particular to a kind of circuit and high speed integrated circuit transmission system of single-ended signal slip sub-signal.
Background technology
Single-ended signal is to transmit the signal of telecommunication by a wire, and the voltage of single-ended signal with respect to ground and definite, is easily subject to the interference of power supply ground noise.And differential signal is to carry out transmission of signal by two wires, the voltage of differential signal is two voltage differences between wire, in the time that there is power supply ground interference signal in the external world, voltage on two wires is interfered effect of signals respectively and changes, but the voltage difference on two wires can be offset variable quantity separately, the impact of interference-free signal.
High speed integrated circuit transmission system is a kind of for realizing the circuit structure of high speed transmission data, wherein there is the high-speed bus of a large amount of parallel transmissions, conventionally adopt multiple drive power circuit to guarantee speed and the quality of signal transmission, caused a large amount of current drains, cause power supply ground noise.In view of differential signal has stronger antijamming capability, differential signal is more suitable in being applied in high speed integrated circuit transmission system than single-ended signal, therefore, needs a kind of circuit that single-ended signal is converted to differential signal.
The circuit structure of existing a kind of single-ended signal slip sub-signal can be with reference to Fig. 1, and Fig. 1 is the electrical block diagram of existing a kind of single-ended signal slip sub-signal.This circuit comprises the individual inverter of 2n-1 (n >=1), single-ended signal is divided into the first output signal and the second output signal, wherein, the first output signal is exported as the first differential signal after n inverter, the second output signal as the second differential signal output, has realized single-ended signal has been converted to differential signal after n-1 inverter.But because the internal circuit configuration of inverter has certain time-lag action to signal transmission, between the time delay of the first differential signal of exporting after n inverter and the time delay of the second differential signal of exporting after n-1 inverter, there are differences.For high speed integrated circuit transmission system, in differential signal, the difference of two signal output part time delays there will be the error rate to improve, and even causes the serious problems such as signal transmission is chaotic.
Utility model content
The utility model provides a kind of circuit and high speed integrated circuit transmission system of single-ended signal slip sub-signal, to eliminate the difference between two signal output part time delays in differential signal.
The utility model embodiment provides a kind of circuit of single-ended signal slip sub-signal, comprising: circuit is adjusted in first signal circuit, secondary signal circuit and time delay;
Described first signal circuit comprises the inverter of n series connection; The input of described first signal circuit receives single-ended signal, and described single-ended signal is after the inverter of described n series connection, and as the first signal output in differential signal, described n is more than or equal to 1 integer;
Described secondary signal circuit comprises the inverter of m series connection; The input of described secondary signal circuit receives described single-ended signal, described single-ended signal after the inverter of described m series connection, output M signal, described m is more than or equal to 0 integer, m is less than n, and difference between n and m is odd number;
The inverter that circuit comprises the series connection of described difference is adjusted in described time delay; Described time delay is adjusted circuit and is connected with described secondary signal circuit with described first signal circuit respectively, be used for receiving described first signal, and described first signal is merged to the secondary signal output in differential signal with described M signal after the inverter of a described difference series connection.
The circuit of single-ended signal slip sub-signal as above, the difference between described n and m is 1.
The circuit of single-ended signal slip sub-signal as above, described n is more than or equal to 2 even number.
The circuit of single-ended signal slip sub-signal as above, described inverter comprises the first field effect transistor and the second field effect transistor, and described the first field effect transistor is p channel field-effect pipe, and described the second field effect transistor is n channel field-effect pipe;
The source electrode of described the first field effect transistor connects high level, and drain electrode is connected with the drain electrode of described the second field effect transistor, the source ground of described the second field effect transistor;
The grid of described the first field effect transistor is connected with the grid of described the second field effect transistor, and as the input of described inverter; The drain electrode of described the first field effect transistor is also as the output of described inverter.
Another embodiment of the utility model provides a kind of high speed integrated circuit transmission system, comprises the circuit of single-ended signal slip sub-signal as above.
The technical scheme that the present embodiment provides arranges time delay by employing and adjusts the output of connection at first signal circuit and secondary signal circuit, adjust circuit through time delay again with the first signal that single-ended signal is obtained after first signal circuit and carry out time delay, and merge with the M signal that single-ended signal obtains after secondary signal circuit, obtain secondary signal, dwindle the gap between secondary signal and first signal time delay, wherein, the quantity of the inverter that secondary signal circuit comprises is less than first signal circuit, the quantity that the inverter that comprises of circuit is adjusted in time delay equals the quantity of inverter that first signal circuit comprises and the difference of the quantity of the inverter that secondary signal circuit comprises.Technique scheme can be dwindled the gap between secondary signal and first signal time delay, foregoing circuit is applied to high speed integrated circuit transmission system, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause signal error redirect so that signal to transmit chaotic phenomenon, reduce the error rate, improved the accuracy rate of signal transmission.
Brief description of the drawings
Fig. 1 is the electrical block diagram of existing a kind of single-ended signal slip sub-signal;
The electrical block diagram of the single-ended signal slip sub-signal that Fig. 2 provides for the utility model embodiment mono-;
The electrical block diagram of the single-ended signal slip sub-signal that Fig. 3 provides for the utility model embodiment bis-;
Fig. 4 is the oscillogram that in Fig. 3, the secondary signal in line output signal, M signal and differential signal is adjusted in time delay;
Another electrical block diagram of the single-ended signal slip sub-signal that Fig. 5 provides for the utility model embodiment bis-;
The part signal oscillogram of the circuit of the single-ended signal slip sub-signal that Fig. 6 provides for the utility model embodiment bis-;
The structural representation of inverter in the circuit of the single-ended signal slip sub-signal that Fig. 7 provides for the utility model embodiment tri-.
Embodiment
Embodiment mono-
The electrical block diagram of the single-ended signal slip sub-signal that Fig. 2 provides for the utility model embodiment mono-.In view of the discrepant problem of time delay between the differential signal of the circuit output of existing single-ended signal slip sub-signal, the present embodiment has proposed a kind of circuit of new single-ended signal slip sub-signal, as shown in Figure 2, this circuit can comprise: circuit 3 is adjusted in first signal circuit 1, secondary signal circuit 2 and time delay.
Wherein, first signal circuit 1 comprises the inverter of n series connection, and the input of first signal circuit 1 receives single-ended signal, and this single-ended signal is after the inverter of n series connection, and as the first signal output in differential signal, n is more than or equal to 1 integer.
Secondary signal circuit 2 comprises the inverter of m series connection, and the input of secondary signal circuit 2 receives above-mentioned single-ended signal, then after the inverter of m series connection, exports M signal.M is more than or equal to 0 integer, and m is less than n, and the difference of n and m is odd number.
The inverter that circuit 3 comprises the series connection of above-mentioned difference is adjusted in time delay, also: time delay is adjusted circuit 3 and comprised at least one inverter, and the quantity of inverter equates with above-mentioned difference (n-m).Time delay is adjusted circuit 3 and is connected with first signal circuit 1 and secondary signal circuit 2 respectively, for receiving first signal, and this first signal is merged with M signal after a difference inverter, as the secondary signal output of differential signal.
Technique scheme arranges time delay by employing and adjusts the output of connection at first signal circuit and secondary signal circuit, adjust circuit through time delay again with the first signal that single-ended signal is obtained after first signal circuit and carry out time delay, and merge with the M signal that single-ended signal obtains after secondary signal circuit, obtain secondary signal, wherein, the quantity m of the inverter that secondary signal circuit comprises is less than the quantity n of the inverter that first signal circuit comprises, and the difference between n and m is odd number, the quantity that the inverter that comprises of circuit is adjusted in time delay equals the quantity n of inverter that first signal circuit comprises and the difference of the quantity m of the inverter that secondary signal circuit comprises.Technique scheme can be dwindled the gap between secondary signal and first signal time delay, foregoing circuit is applied to high speed integrated circuit transmission system, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause signal error redirect so that signal to transmit chaotic phenomenon, reduce the error rate, improved the accuracy rate of signal transmission.
In order to meet the various needs of differential signal, the difference of the inverter comprising between two signal lines in foregoing circuit can have situation not of the same race, the present embodiment is only elaborated taking difference as the technical scheme that 1 situation provides embodiment, and the Technical Design that those skilled in the art can provide according to the present embodiment is realized other implementation.
Above-mentioned first signal circuit 1 comprises the inverter of n series connection, and secondary signal circuit 2 comprises the inverter of m series connection, and the difference of n and m is 1, that is: time delay adjustment circuit 3 comprises an inverter.Wherein, n is more than or equal to 2 positive integer.
The input of first signal circuit 1 receives single-ended signal IN, this single-ended signal IN is after the inverter of n (n is more than or equal to 2 positive integer) series connection, export (in the time that n is even number as the first signal INP in differential signal, this first signal is INP, identical with single-ended signal phase place; In the time that n is odd number, this first signal is INN, and with single-ended signal single spin-echo, the present embodiment take first signal as example as INP).The input of secondary signal circuit 2 receives the single-ended signal IN identical with first signal circuit 1, and this single-ended signal IN, after the inverter of the individual series connection of m (m=n-1), exports M signal A0.The input that circuit 3 is adjusted in time delay receives the first signal INP that first signal circuit 1 is exported, the M signal A0 merging that this first signal INP exports with secondary signal circuit 2 after an inverter is exported (in the time that n is even number as the secondary signal INN in differential signal, this secondary signal is INN, with single-ended signal single spin-echo; In the time that n is odd number, this secondary signal is INP, identical with single-ended signal phase place, and the present embodiment take secondary signal as example as INN) so that first signal INP and secondary signal INN form differential signal.
Single-ended signal IN is every through an inverter, and its signal inversion saltus step once.On first signal circuit 1, be provided with the inverter of n series connection, and on secondary signal circuit 2, be provided with n-1 series connection inverter, single-ended signal IN on first signal circuit 1 and secondary signal circuit 2 respectively through separately series connection inverter after, the signal obtaining is anti-phase each other, and the first signal INP in above-mentioned differential signal and M signal A0 are anti-phase each other.
The input that circuit 3 is adjusted in time delay is connected with the output of last inverter in first signal circuit 1, receives the first signal INP that first signal circuit 1 is exported.The output that circuit 3 is adjusted in time delay is connected with the output of last inverter in secondary signal circuit 2, receives the M signal A0 that secondary signal circuit 2 is exported.After the inverter arranging on circuit 3 is adjusted in time delay, there is anti-phase redirect in first signal INP, obtains signal A1, and the saltus step rule of signal A1 and M signal A0 is identical, but signal A1 lags behind the delay time of two inverters of M signal A0.Signal A1 and M signal A0 merge the secondary signal INN that forms differential signal.
From sequential, in the time that saltus step occurs M signal A0, also there is saltus step in secondary signal INN thereupon, but owing to also not arriving in the identical hopping edge of signal A1, the trend that secondary signal INN changes is identical with M signal A0, but pace of change is slower.In the time arriving in the identical hopping edge of signal A1, drive secondary signal INN to change fast, to complete the moment of saltus step be between M signal A0 and signal A1 to secondary signal INN, realize the signal that secondary signal circuit 2 is exported and carried out time delay, shortened the gap between the 1 output signal time delay of first signal circuit.
The output of connection at first signal circuit and secondary signal circuit adjusted in the time delay that the technical scheme that the present embodiment provides is provided with an inverter by employing, with by single-ended signal after the inverter of n series connection the first signal that obtains again through the time delay of an inverter, and merge with the M signal that single-ended signal obtains after the individual inverter of m (m=n-1), obtain secondary signal, dwindle the gap between secondary signal and first signal time delay, foregoing circuit is applied to high speed integrated circuit transmission system, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause signal error redirect so that signal to transmit chaotic phenomenon, reduce the error rate, improve the accuracy rate of signal transmission.
Embodiment bis-
The electrical block diagram of the single-ended signal slip sub-signal that Fig. 3 provides for the utility model embodiment bis-.On the basis of above-described embodiment, the present embodiment provides the implementation of the circuit of another kind of single-ended signal slip sub-signal, in above-mentioned first signal circuit 1, the quantity n of inverter is set to be more than or equal to 2 even number, also be that n can be 2, or n can be the even numbers such as 4,6,8, in secondary signal circuit 2, the quantity m (m=n-1) of inverter must be odd number, can be 1, can be maybe the odd numbers such as 3,5,7.
As shown in Figure 3, in first signal circuit 1, be provided with the inverter of the individual series connection of 2x (x is positive integer, 2x=n), in secondary signal circuit 2, be provided with the inverter of (2x-1) individual series connection.The first signal INP that single-ended signal IN exports after the inverter of 2x series connection in first signal circuit 1, the M signal A0 that single-ended signal IN exports after the inverter of 2x-1 series connection in secondary signal circuit 2.The result of setting is like this, and first signal INP is identical with the saltus step trend of single-ended signal IN, and M signal A0 is contrary with the saltus step trend of single-ended signal IN.
The input that circuit 3 is adjusted in time delay receives the first signal INP that first signal circuit 1 is exported, the M signal A0 that this first signal INP exports with secondary signal circuit 2 after an inverter merges as the secondary signal INN output in differential signal, so that first signal INP and secondary signal INN form differential signal.
The input that circuit 3 is adjusted in time delay is connected with the output of last inverter in first signal circuit 1, receives the first signal INP that first signal circuit 1 is exported.The output that circuit 3 is adjusted in time delay is connected with the output of last inverter in secondary signal circuit 2, receives the M signal A0 that secondary signal circuit 2 is exported.After the inverter arranging on circuit 3 is adjusted in time delay, there is anti-phase redirect in first signal INP, obtains signal A1, and the saltus step rule of signal A1 and M signal A0 is identical, but signal A1 lags behind the delay time of two inverters of M signal A0.Signal A1 and M signal A0 merge the secondary signal INN that forms differential signal.
Fig. 4 is the oscillogram that in Fig. 3, the secondary signal in line output signal, M signal and differential signal is adjusted in time delay, represent the variation tendency of signal, and in the practical work process of circuit, signal should be curve in Fig. 4 with straightway.As shown in Figure 4:
In low level, skip in the process of high level, in the time that the rising edge moment of M signal A0 arrives, secondary signal INN is upwards saltus step thereupon, but because the rising edge of signal A1 does not also arrive, the speed that secondary signal INN changes is slower, and the absolute value that is equivalent to slope is less.In the time that the rising edge of signal A1 arrives, drive secondary signal INN to change fast, the absolute value of slope increases, to complete the moment of rising saltus step be between M signal A0 and signal A1 to secondary signal INN, realize the signal that secondary signal circuit 2 is exported and carried out time delay, shortened the gap between the 1 output signal time delay of first signal circuit.
Under high level, skip in low level process, in the time that the trailing edge of M signal A0 arrives, secondary signal INN is saltus step downwards thereupon, but because the trailing edge of signal A1 does not also arrive, the speed that secondary signal INN changes is slower, and the absolute value that is equivalent to slope is less.In the time that the trailing edge of signal A1 arrives, drive secondary signal INN to change fast, the absolute value of slope increases, to complete the moment of decline saltus step be between M signal A0 and signal A1 to secondary signal INN, realize the signal that secondary signal circuit 2 is exported and carried out time delay, shortened the gap between the 1 output signal time delay of first signal circuit.
Those skilled in the art can set according to technique scheme the quantity of inverter, the simplest a kind of mode for arranging two inverters in first signal circuit 1, an inverter is set in secondary signal circuit 2, the circuit forming can be with reference to Fig. 5, another electrical block diagram of the single-ended signal slip sub-signal that Fig. 5 provides for the utility model embodiment bis-.
The part signal oscillogram of the circuit of the single-ended signal slip sub-signal that Fig. 6 provides for the utility model embodiment bis-, the rough schematic view that Fig. 6 is signal waveform, only for the relation between the jumping moment of outstanding each signal.As shown in Figure 6, in the circuit that technique scheme provides, the sequential relationship of each signal saltus step is:
In the starting stage, single-ended signal IN is low level, and first signal INP is also low level, and M signal A0, signal A1 and secondary signal INN are high level.
Arrive when the rising edge moment of single-ended signal IN, after the delay time of an inverter of time delay, M signal A0 is low level by high level saltus step.After the delay time of two inverters of time delay, first signal INP is high level by low transition.After the delay time of three inverters of time delay, signal A1 by high level saltus step to low level.Under the mutual restraining function of M signal A0 and signal A1, the jumping moment of secondary signal INN occurs between M signal A0 and signal A1, is similar to and takes place at the same instant saltus step with first signal INP.
Therefore, the output of connection at first signal circuit and secondary signal circuit adjusted in the time delay that the technical scheme that the present embodiment provides is provided with an inverter by employing, with by single-ended signal after the inverter of even number n series connection the first signal that obtains again through the time delay of an inverter, and merge with the M signal that single-ended signal obtains after n-1 inverter, obtain secondary signal, dwindle the gap between secondary signal and first signal time delay, foregoing circuit is applied to high speed integrated circuit transmission system, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause signal error redirect so that signal to transmit chaotic phenomenon, reduce the error rate, improve the accuracy rate of signal transmission.
Embodiment tri-
The structural representation of inverter in the circuit of the single-ended signal slip sub-signal that Fig. 7 provides for the utility model embodiment tri-.On the basis of the various embodiments described above, the inverter arranging in each circuit can adopt inverter structure common in prior art to realize, or the circuit structure that also can design other form by those skilled in the art is realized the effect of signal inversion redirect.The present embodiment provides a kind of attainable mode:
As shown in Figure 7, inverter can comprise the first field effect transistor P1 and the second field effect transistor N1, and the first field effect transistor P1 is p channel field-effect pipe, and the second field effect transistor N1 is n channel field-effect pipe.Wherein, the source electrode of the first field effect transistor P1 connects high level, and drain electrode is connected with the drain electrode of the second field effect transistor N1, the source ground of the second field effect transistor N1.The grid of the first field effect transistor P1 is connected with the grid of the second field effect transistor N1, and as the input of inverter.The drain electrode of the first field effect transistor P1 is also as the output of inverter.
On the basis of above-described embodiment, the output of connection at first signal circuit and secondary signal circuit adjusted in the time delay that the technical scheme that the present embodiment provides is provided with an inverter by employing, with by single-ended signal after the inverter of n series connection the first signal that obtains again through the time delay of an inverter, and merge with the M signal that single-ended signal obtains after the individual inverter of m (m=n-1), obtain secondary signal, dwindle the gap between secondary signal and first signal time delay, foregoing circuit is applied to high speed integrated circuit transmission system, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause the phenomenon of signal error redirect, reduce the error rate, improve the accuracy rate of signal transmission.
The present embodiment also provides a kind of high speed integrated circuit transmission system, comprises the circuit of the single-ended signal slip sub-signal that above-mentioned any embodiment provides.By this circuit application in the transmission system at integrated circuit, for high-speed transfer signal, can avoid because the delay inequality distance of the first signal in differential signal and secondary signal is too large, and cause signal error redirect so that signal to transmit chaotic phenomenon, reduce the error rate, improved the accuracy rate of signal transmission.
Finally it should be noted that: above each embodiment, only in order to the technical solution of the utility model to be described, is not intended to limit; Although the utility model is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the scope of the each embodiment technical scheme of the utility model.
Claims (5)
1. a circuit for single-ended signal slip sub-signal, is characterized in that, comprising: circuit is adjusted in first signal circuit, secondary signal circuit and time delay;
Described first signal circuit comprises the inverter of n series connection; The input of described first signal circuit receives single-ended signal, and described single-ended signal is after the inverter of described n series connection, and as the first signal output in differential signal, described n is more than or equal to 1 integer;
Described secondary signal circuit comprises the inverter of m series connection; The input of described secondary signal circuit receives described single-ended signal, described single-ended signal after the inverter of described m series connection, output M signal, described m is more than or equal to 0 integer, m is less than n, and difference between n and m is odd number;
The inverter that circuit comprises the series connection of described difference is adjusted in described time delay; Described time delay is adjusted circuit and is connected with described secondary signal circuit with described first signal circuit respectively, be used for receiving described first signal, and described first signal is merged to the secondary signal output in differential signal with described M signal after the inverter of a described difference series connection.
2. the circuit of single-ended signal slip sub-signal according to claim 1, is characterized in that, the difference between described n and m is 1.
3. the circuit of single-ended signal slip sub-signal according to claim 2, is characterized in that, described n is more than or equal to 2 even number.
4. according to the circuit of the single-ended signal slip sub-signal described in claim 1-3 any one, it is characterized in that, described inverter comprises the first field effect transistor and the second field effect transistor, and described the first field effect transistor is p channel field-effect pipe, and described the second field effect transistor is n channel field-effect pipe;
The source electrode of described the first field effect transistor connects high level, and drain electrode is connected with the drain electrode of described the second field effect transistor, the source ground of described the second field effect transistor;
The grid of described the first field effect transistor is connected with the grid of described the second field effect transistor, and as the input of described inverter; The drain electrode of described the first field effect transistor is also as the output of described inverter.
5. a high speed integrated circuit transmission system, is characterized in that, comprises the circuit of the single-ended signal slip sub-signal as described in claim 1-4 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420261507.8U CN203872144U (en) | 2014-05-21 | 2014-05-21 | Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420261507.8U CN203872144U (en) | 2014-05-21 | 2014-05-21 | Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203872144U true CN203872144U (en) | 2014-10-08 |
Family
ID=51653063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420261507.8U Expired - Lifetime CN203872144U (en) | 2014-05-21 | 2014-05-21 | Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203872144U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115333556A (en) * | 2022-08-10 | 2022-11-11 | 慷智集成电路(上海)有限公司 | High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip |
-
2014
- 2014-05-21 CN CN201420261507.8U patent/CN203872144U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115333556A (en) * | 2022-08-10 | 2022-11-11 | 慷智集成电路(上海)有限公司 | High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip |
| CN115333556B (en) * | 2022-08-10 | 2023-10-03 | 慷智集成电路(上海)有限公司 | High-speed receiving and transmitting system based on MIPI protocol |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9054681B2 (en) | High speed duty cycle correction and double to single ended conversion circuit for PLL | |
| KR20200088650A (en) | Signal generation circuit synchronized with clock signal and semiconductor apparatus using the same | |
| US8674736B2 (en) | Clock synchronization circuit | |
| US9813188B2 (en) | Transmitting circuit, communication system, and communication method | |
| JP6361852B2 (en) | LVDS driver | |
| CN104335488A (en) | A differential clock signal generator | |
| CN106788353A (en) | A kind of skewed clock correcting method and circuit, terminal device | |
| US9001902B2 (en) | Transmission system | |
| CN103546151A (en) | High-speed DLL (Delay-locked loop) | |
| EP1063810A2 (en) | Clock signal control method and circuit and data transmitting apparatus employing the same | |
| CN102694538B (en) | Combined data level-shifter and de-skewer | |
| CN1881797B (en) | Synchronization circuits and methods | |
| CN203872144U (en) | Circuit of converting single-ended signal to differential signal and high-speed integrated circuit transmission system | |
| CN201869179U (en) | Multi-phase clock generating circuit with programmable dutyfactor | |
| CN109861690A (en) | Export feedback clock duty cycle adjustment device, method and system | |
| CN104143975A (en) | DLL delay link and method for reducing duty cycle distortion of DLL clock | |
| KR102624454B1 (en) | Data serializer circuit | |
| CN104102264A (en) | Continuous time pre-emphasis current module driver | |
| JP5522372B2 (en) | Receiver circuit | |
| CN110365327B (en) | Differential clock tree circuit | |
| CN106125822B (en) | A method of reducing skewed clock on long clock cabling | |
| CN203278775U (en) | Programmable non-overlapping clock generation circuit | |
| US10560292B1 (en) | Transmission apparatus and communication system | |
| US9088465B2 (en) | Receiver circuit | |
| US8130748B2 (en) | Transmitter circuit to compensate for influence of crosstalk noise in pre-emphasis scheme |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20141008 |