CN106125822B - A method of reducing skewed clock on long clock cabling - Google Patents
A method of reducing skewed clock on long clock cabling Download PDFInfo
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- CN106125822B CN106125822B CN201610459747.2A CN201610459747A CN106125822B CN 106125822 B CN106125822 B CN 106125822B CN 201610459747 A CN201610459747 A CN 201610459747A CN 106125822 B CN106125822 B CN 106125822B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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Abstract
The present invention relates to a kind of methods for reducing skewed clock on long clock cabling, this method is first increase by one and long clock cabling symmetrically consistent looped back clock cabling, then increase phase interpolation clock buffer at each clock output on long clock cabling and looped back clock cabling, the clock that generation phase is located at two-way clock phase middle position is exported, so that realize has approximately uniform clock phase at clock load.The present invention greatly reduces the skewed clock on long clock cabling using clock phase interpolation method, and static phase error is only decided by realize the mismatch in circuit between the process deviation and circuit of device parameters.
Description
Technical field
The invention belongs to technical field of integrated circuits, are a kind of sides for reducing skewed clock (Skew) on long clock cabling
Method, the larger situation of skewed clock on long clock cabling.
Background technique
With the continuous increase of footprint, the continuous enhancing of algorithm and function, chip operation clock frequency are realized
Continuous improvement, the requirement to the clock system in chip is also higher and higher, and the management of multi-clock zone, clock delay, clock are inclined
Tiltedly, clock jitter etc. will become the key factor for influencing chip design.The deflection (Skew) of clock is a weight of clock system
Index is wanted, ideally clock reaches at clock load at the same time.If skewed clock is larger, each logic will cause
The clock of Energy Resources Service has larger difference, causes difficulty to the satisfaction of the setup/hold timing requirements of sequence circuit, also can be into one
Walk the raising of influence system work clock.
The clock tree construction of clock system includes H tree (H-tree) type, fish-bone (spine) type etc., its main feature is that by clock
It is divided into many levels, the Skew of clock is reduced with the matching of clock track lengths.Sometimes, such as in fish bone well clock tree construction
In, very long specific to the cabling of the fish-bone of a certain layer, the clock of this layer of fish-bone cabling everywhere has biggish Skew, a kind of conventional
Processing method exactly matches the cabling difference of fish-bone everywhere in fish-bone with additional cabling everywhere.This is a kind of solution,
But when fish-bone cabling is very long, it may be desirable to which a large amount of matching clock cabling, the difficulty for causing Clock Tree to be routed are unfavorable for clock system
The comprehensive of system is realized.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the existing defects, provides a kind of reduce using clock phase interpolation and grows
The method of skewed clock on clock cabling greatly reduces the clock Skew on the long line of clock.
In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
A kind of method for reducing skewed clock on long clock cabling of the present invention, this method are first to increase by one to walk with long clock
Then the symmetrical consistent looped back clock cabling of line increases at each clock output on long clock cabling and looped back clock cabling
Phase interpolation clock buffer, the clock that generation phase is located at two-way clock phase middle position are exported, are existed to realize
There is approximately uniform clock phase at clock load.
Further, phase interpolation clock buffer is the clock buffer for realizing phase interpolation function, the phase interpolation
Clock buffer includes shaping clock buffer, slewrate adjustment circuit, phase interpolation circuit, differential comparator and difference-
Single ended buffer, shaping clock buffer are used to draw at each clock output on long clock cabling and looped back clock cabling
Two-pass DINSAR clock be shaped as rise/fall respectively along time and the consistent two-pass DINSAR clock signal of signal amplitude；
The slewrate that slewrate adjustment circuit is used to adjust two-pass DINSAR clock signal becomes smaller to meeting wanting for phase interpolation circuit
It asks；When the two-pass DINSAR clock signal generation phase that phase interpolation circuit is used to adjust slew rate is located at two-pass DINSAR
The differential clock signal in clock signal phase middle position；Differential comparator is for will revert to difference after differential clock signal shaping
Clock；Differential to single-ended buffer is used to differential clocks being converted to single channel clock signal, then send to clock load.
Beneficial effects of the present invention:
1, long clock cabling is carried out loopback by this method, and each clock on long clock cabling and looped back clock cabling is defeated
Source carries out phase-interpolation processing, generates phase and is located at the clock in two-way clock phase middle position, then each generation it is new when
Clock can keep approximately uniform phase, greatly reduce the clock Skew on long clock cabling；Its static phase error is (remaining
Skew deviation) only it is decided by realize the mismatch in circuit between the process deviation and circuit of device parameters.
2, this method is succinct, clear principle, convenient for realizing in fish bone well isochronon tree construction.
Detailed description of the invention
Fig. 1 is the way circuit functional block diagram for reducing the preferred implementation of skewed clock through the invention；
Fig. 2 is the functional block diagram of phase interpolation clock buffer of the invention；
Fig. 3 is the functional block diagram of phase interpolation circuit in Fig. 2；
Fig. 4 is the timing diagram of reduction skewed clock principle of the present invention by taking 120_0,121_0 and 120_N, 121_N as an example.
Specific embodiment
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present invention
The restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.
Fig. 1-4 is the specific implementation circuit block diagram that the present invention reduces skewed clock (Skew) by clock phase interpolation method.
Fig. 1 show the long linear system system 100 of a clock, wherein slow comprising differential clocks input source 101, the long line clock of difference
Rush the long line clock buffer 103 of device 102, loopback difference, differential clocks cabling 111, loopback differential clocks cabling 112, in phase
Interpolated clock buffer (CGBUF) 105 and clock load 106.101 input difference clock of differential clocks input source, it is long by difference
102 rear-guard of line clock buffer moves differential clocks cabling 111.In the long line of 111 end connection ring return difference of differential clocks cabling point
Clock buffer 103, drive ring return differential clocks cabling 112.On differential clocks cabling 111, loopback differential clocks cabling 112
Branch clock is drawn at 120_0,120_1,120_2 ... 120_N and 121_0,121_1,121_2 ... 121_N respectively via phase
Interpolation clock buffer 105 is sent to clock load 106.The long line 111 of above-mentioned differential clocks and the long line 112 of loopback differential clocks are symmetrical
Unanimously, for guarantee the correspondence clock waveform on difference (forward direction) clock cabling 111 and loopback difference (reversed) clock cabling 112 with
Consistent, the addition long line clock buffer of loopback difference identical with the long line clock buffer 102 of difference at loopback point of phase shift
103。
Fig. 2 show the functional block diagram of phase interpolation clock buffer (105 in Fig. 1), wherein including shaping clock buffer
Device 201, slew rate adjustment circuit 202, phase interpolation circuit (PI) 203, differential comparator 204 and differential to single-ended buffer
205.The two-pass DINSAR clock 141,142 and 143,144 drawn from 120_0,121_0 in Fig. 1 is slow by shaping clock respectively
It rushes device 201 and is shaped as rise/fall along time and the consistent two-pass DINSAR clock signal 211 of signal amplitude.Two-way after shaping
Differential clock signal 211 send respectively to slew rate adjustment circuit 202 adjust slew rate, make its slew rate become smaller to
Meet the requirement of phase interpolation circuit 203.The two-pass DINSAR clock signal 212 of slew rate was adjusted by phase interpolation electricity
The differential clock signal 213 that phase is located at 212 phase middle position of two-pass DINSAR clock signal is generated behind road 203.The difference of generation
Point clock signal 213 is by reverting to differential clocks 214 after 204 shaping of differential comparator, then passes through differential to single-ended buffer
205 are converted to single channel clock signal, i.e. clock signal 151 (151_0,151_1,151_2 ... of clock load 106 are given in Fig. 1
151_N)。
Fig. 3 show phase interpolation circuit (functional block diagram in PI, Fig. 2 203), wherein input signal VP1/N1, VP2/
N2 respectively corresponds the differential clock signal 212 in Fig. 2, differential clock signal 213 in output signal OUTP/N corresponding diagram 2.The phase
Position interpolating circuit 203 can realize that phase is located at the generation of the differential clock signal in two-pass DINSAR clock signal phase middle position.
Assuming that drawn on differential clocks cabling 111 in Fig. 1 branch clock it is each between delay be Δ t1, i.e. in Fig. 1
Delay between 120_0 and 120_1,120_1 and 120_2 etc. is all Δ t1, then the delay between 120_1 and 120_N is N*
Δt1.Also due to loopback differential clocks cabling 112 and differential clocks cabling 111 are symmetrical consistent, therefore loopback differential clocks are walked
Delay between extraction branch clock is each on line 112 is also Δ t1.Assume again that on differential clocks cabling 111 node 120_N and
Delay on loopback differential clocks cabling 112 between node 121_N is Δ t2, then the delay between 120_0 and 121_0 is
2N*Δt1+Δt2。
Fig. 4 show by taking 120_0,121_0 and 120_N, 121_N as an example introduce the present invention reduce clock skew principle when
Sequence figure.By after phase interpolation clock buffer 105 in Fig. 1 output 151_0 and 151_N timing distinguish it is as follows: 120_0 with
Delay between 151_0 be N* Δ t1+ Δ t2/2+tdly, tdly be phase interpolation clock buffer 105 unit inside prolong
Late；Delay between 120_N and 151_N is Δ t2/2+tdly.Unification is on the basis of 120_0, then 151_0 and 151_N are opposite
In the delay of 120_0 be all N* Δ t1+ Δ t2/2+tdly.Similarly it is found that 151_0,151_1,151_2 ... 151_N relative to
The delay of 120_0 is equal.
It can be seen that the present invention can be significantly reduced to the Skew of clock load, ideally can even accomplish
0Skew。
The invention proposes the methods for using clock phase interpolation to reduce clock Skew, increase by one first and walk with long clock
Symmetrical consistent looped back clock cabling (long clock cabling carries out loopback) of line, it is every on long clock cabling and looped back clock cabling
At a clock output, to the reversed clock of loopback exported on the positive clock and looped back clock cabling exported on long clock cabling into
Row phase-interpolation processing, i.e., addition phase interpolation clock buffer (CGBUF), then on long clock cabling output clock and
The output clock of same position carries out slew rate adjustment on looped back clock cabling, and a kind of phase interpolation circuit is recycled to generate
The clock that phase is located at two-way clock (positive clock and the reversed clock of loopback) phase middle position is exported, to realize every
The new clock of a generation has approximately uniform clock phase at clock load, greatly reduces clock Skew.
Claims (2)
1. a kind of method for reducing skewed clock on long clock cabling, it is characterised in that: the method is first to increase by one and length
The symmetrical consistent looped back clock cabling of clock cabling, then each clock output on long clock cabling and looped back clock cabling
Place increases phase interpolation clock buffer (105), and the clock that generation phase is located at two-way clock phase middle position is exported,
There is approximately uniform clock phase at clock load (106) to realize；Differential clocks input source input difference clock leads to
Long clock cabling is driven after crossing the long line clock buffer of difference, in the long line clock buffer of long clock cabling end connection ring return difference point
Device drives looped back clock cabling.
2. the method according to claim 1 for reducing skewed clock on long clock cabling, it is characterised in that: in the phase
Interpolated clock buffer (105) is the clock buffer for realizing phase interpolation function, which includes
Shaping clock buffer (201), slew rate adjustment circuit (202), phase interpolation circuit (203), differential comparator (204)
With differential to single-ended buffer (205), shaping clock buffer (201) is used for will be on long clock cabling and looped back clock cabling
The two-pass DINSAR clock (141,142 and 143,144) drawn at each clock output be shaped as respectively rise/fall along the time and
The consistent two-pass DINSAR clock signal (211) of signal amplitude；Slew rate adjustment circuit (202) is for when adjusting two-pass DINSAR
The slew rate of clock signal (211) becomes smaller to the requirement for meeting phase interpolation circuit (203)；Phase interpolation circuit (203) is used for
The two-pass DINSAR clock signal (212) for adjusting slew rate generation phase is located among two-pass DINSAR clock signal phase
The differential clock signal (213) of position；Differential comparator (204) is for will revert to difference after differential clock signal (213) shaping
Timesharing clock (214)；Differential to single-ended buffer (205) is used to be converted to differential clocks (214) single channel clock signal (151), then
It send at clock load (106).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610459747.2A CN106125822B (en) | 2016-06-23 | 2016-06-23 | A method of reducing skewed clock on long clock cabling |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610459747.2A CN106125822B (en) | 2016-06-23 | 2016-06-23 | A method of reducing skewed clock on long clock cabling |
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| Publication Number | Publication Date |
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| CN106125822A CN106125822A (en) | 2016-11-16 |
| CN106125822B true CN106125822B (en) | 2019-02-15 |
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| CN114528019A (en) * | 2020-11-23 | 2022-05-24 | 深圳比特微电子科技有限公司 | Multi-bit register, chip and computing device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773857A (en) * | 2004-11-12 | 2006-05-17 | 国际商业机器公司 | Method and apparatus for generating non-skewed complementary signals through interpolation |
| CN104184461A (en) * | 2014-08-20 | 2014-12-03 | 上海交通大学 | Fractional frequency divider |
| CN105553448A (en) * | 2014-10-27 | 2016-05-04 | 三星电子株式会社 | METHOD, SYSTEM AND DEVICE FOR ADJUSTING clock skew |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2532284A (en) * | 2014-11-17 | 2016-05-18 | Ibm | Method to reduce dynamic clock skew and/or slew in an electronic circuit |
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2016
- 2016-06-23 CN CN201610459747.2A patent/CN106125822B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773857A (en) * | 2004-11-12 | 2006-05-17 | 国际商业机器公司 | Method and apparatus for generating non-skewed complementary signals through interpolation |
| CN104184461A (en) * | 2014-08-20 | 2014-12-03 | 上海交通大学 | Fractional frequency divider |
| CN105553448A (en) * | 2014-10-27 | 2016-05-04 | 三星电子株式会社 | METHOD, SYSTEM AND DEVICE FOR ADJUSTING clock skew |
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Effective date of registration: 20201216 Address after: 2 / F, building B1, No. 777, Jianzhu West Road, Binhu District, Wuxi City, Jiangsu Province, 214000 Patentee after: WUXI ZHONGWEI YIXIN Co.,Ltd. Address before: Hui Road Binhu District 214035 Jiangsu city of Wuxi province No. 5 Patentee before: The 58th Research Institute of China Electronics Technology Group Corp. |
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