CN106125822A

CN106125822A - A kind of reduce the method for skewed clock on long clock cabling

Info

Publication number: CN106125822A
Application number: CN201610459747.2A
Authority: CN
Inventors: 谢长生; 于宗光; 单悦尔; 张艳飞
Original assignee: CETC 58 Research Institute
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2016-06-23
Filing date: 2016-06-23
Publication date: 2016-11-16
Anticipated expiration: 2036-06-23
Also published as: CN106125822B

Abstract

The present invention relates to a kind of reduce the method for skewed clock on long clock cabling, the method is first to increase a consistent looped back clock cabling symmetrical with long clock cabling, then phase interpolation clock buffer is increased at each clock output on long clock cabling and looped back clock cabling, generation phase place is positioned at the clock in two-way clock phase centre position and exports, thus realizes having approximately uniform clock phase at clock load.The present invention uses clock phase interpolation to greatly reduce the skewed clock on long clock cabling, and its static phase error is only decided by realize the mismatch between the process deviation of device parameters in circuit and circuit.

Description

A kind of reduce the method for skewed clock on long clock cabling

Technical field

The invention belongs to technical field of integrated circuits, be the side of skewed clock (Skew) on the long clock cabling of a kind of reduction Method, the situation that skewed clock is bigger on long clock cabling.

Background technology

Continuous increase along with footprint, it is achieved algorithm and the continuous enhancing of function, chip operation clock frequency Improve constantly, the requirement to the clock system in chip is more and more higher, and the management of multi-clock zone, clock delay, clock are inclined Tiltedly, clock jitter etc. will become the key factor affecting chip design.The deflection (Skew) of clock is a weight of clock system Wanting index, ideally clock arrived at clock load in the identical time.If skewed clock is relatively big, each logic can be caused The clock of Energy Resources Service has bigger difference, and the satisfied of setup/hold timing requirements of sequence circuit is caused difficulty, also can enter one Step affects the raising of system work clock.

The clock trees structure of clock system includes H tree (H-tree) type, fishbone (spine) type etc., is characterized in clock It is divided into many levels, reduces the Skew of clock by the coupling of clock track lengths.Sometimes, such as in fish bone well clock trees structure In, the cabling specific to the fishbone of a certain layer is the longest, and this layer of fishbone cabling clock everywhere has bigger Skew, a kind of routine Processing method, it is simply that mate fishbone cabling difference everywhere with extra cabling everywhere at fishbone.This is a kind of solution, But when fishbone cabling is the longest, it may be desirable to substantial amounts of coupling clock cabling, causes the difficulty that clock trees connects up, be unfavorable for clock system The comprehensive realization of system.

Summary of the invention

The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of employing clock phase interpolation reduces long The method of skewed clock on clock cabling, greatly reduces the clock Skew on the long line of clock.

In order to solve above-mentioned technical problem, the invention provides following technical scheme:

The present invention is a kind of reduces the method for skewed clock on long clock cabling, and the method is first to increase by one to walk with long clock The symmetrical consistent looped back clock cabling of line, then increases at each clock output on long clock cabling and looped back clock cabling Phase interpolation clock buffer, generation phase place is positioned at the clock in two-way clock phase centre position and exports, thus realizes existing There is at clock load approximately uniform clock phase.

Further, phase interpolation clock buffer is the clock buffer realizing phase interpolation function, this phase interpolation Clock buffer include shaping clock buffer, slewrate adjust circuit, phase interpolation circuit, differential comparator and difference- Single ended buffer, shaping clock buffer is for drawing at each clock output on long clock cabling and looped back clock cabling Two-pass DINSAR clock be shaped as rise/fall respectively along the time two-pass DINSAR clock signal consistent with signal amplitude； Slewrate adjusts circuit and diminishes to meeting wanting of phase interpolation circuit for the slewrate adjusting two-pass DINSAR clock signal Ask；When phase interpolation circuit is positioned at two-pass DINSAR for the two-pass DINSAR clock signal adjusting slew rate generates phase place The differential clock signal in clock signal phase centre position；Differential comparator is for reverting to difference after differential clock signal shaping Clock；Differential to single-ended buffer for being converted to single channel clock signal by differential clocks, then delivers at clock load.

Beneficial effects of the present invention:

1, long clock cabling is carried out loopback by the method, and each clock on long clock cabling and looped back clock cabling is defeated Source carries out phase-interpolation process, generates phase place and is positioned at the clock in two-way clock phase centre position, during the most each generation new Clock can keep approximately uniform phase place, greatly reduces the clock Skew on long clock cabling；Its static phase error (residue Skew deviation) only it is decided by realize the mismatch between the process deviation of device parameters in circuit and circuit.

2, the method is succinct, clear principle, it is simple to realize in fish bone well isochronon tree construction.

Accompanying drawing explanation

Fig. 1 is the way circuit theory diagram being preferable to carry out being reduced skewed clock by the present invention；

Fig. 2 is the theory diagram of the phase interpolation clock buffer of the present invention；

Fig. 3 is the theory diagram of phase interpolation circuit in Fig. 2；

Fig. 4 is the present invention sequential chart reducing skewed clock principle as a example by 120_0,121_0 and 120_N, 121_N.

Detailed description of the invention

Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the present invention is protected model The restriction enclosed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to right The present invention makes improvements and modifications, and these improve and modification also falls in the range of the claims in the present invention protection.

Fig. 1-4 for the present invention by clock phase interpolation reduce skewed clock (Skew) be embodied as circuit block diagram.

Fig. 1 show a long wire system of clock 100, wherein comprise differential clocks input source 101, difference long line clock delay Rush in device 102, loopback difference long line clock buffer 103, differential clocks cabling 111, loopback differential clocks cabling 112, phase place Interpolated clock buffer (CGBUF) 105 and clock load 106.Differential clocks input source 101 input difference clock, long by difference Line clock buffer 102 rear drive differential clocks cabling 111.When differential clocks cabling 111 end connects the long line of loopback difference Clock buffer 103, drives loopback differential clocks cabling 112.On differential clocks cabling 111, loopback differential clocks cabling 112 120_0,120_1,120_2 ... 120_N and 121_0,121_1,121_2 ... draw branch clock at 121_N respectively via phase place Interpolation clock buffer 105 delivers to clock load 106.The long line of above-mentioned differential clocks 111 and loopback differential clocks long line 112 are symmetrical Unanimously, for ensure corresponding clock waveform on difference (forward) clock cabling 111 and loopback difference (reversely) clock cabling 112 with Phase shift consistent, adds the loopback difference long line clock buffer that line clock buffer 102 long with difference is identical at loopback point 103。

Fig. 2 show the theory diagram of phase interpolation clock buffer (in Fig. 1 105), wherein comprises shaping clock buffer Device 201, slew rate adjust circuit 202, phase interpolation circuit (PI) 203, differential comparator 204 and differential to single-ended buffer 205.The two-pass DINSAR clock 141,142 and 143,144 drawn at 120_0,121_0 from Fig. 1 delays respectively through shaping clock Rush device 201 and be shaped as rise/fall along the time two-pass DINSAR clock signal 211 consistent with signal amplitude.Two-way after shaping Differential clock signal 211 deliver to respectively slew rate adjust circuit 202 adjust slew rate so that it is slew rate diminish to Meet the requirement of phase interpolation circuit 203.Adjusted the two-pass DINSAR clock signal 212 of slew rate through phase interpolation electricity Generate phase place behind road 203 and be positioned at the differential clock signal 213 in two-pass DINSAR clock signal 212 phase place centre position.The difference generated Point clock signal 213 is by reverting to differential clocks 214 after differential comparator 204 shaping, then by differential to single-ended buffer 205 clock signals 151 being converted to give in single channel clock signal, i.e. Fig. 1 clock load 106 (151_0,151_1,151_2 ... 151_N)。

Fig. 3 show the theory diagram of phase interpolation circuit (in PI, Fig. 2 203), wherein input signal VP1/N1, VP2/ Differential clock signal 212 in N2 corresponding diagram 2 respectively, differential clock signal 213 in output signal OUTP/N corresponding diagram 2.This phase Position interpolating circuit 203 can realize the generation that phase place is positioned at the differential clock signal in two-pass DINSAR clock signal phase centre position.

Assume in Fig. 1 to draw on differential clocks cabling 111 branch clock each between delay be Δ t₁, i.e. in Fig. 1 Delay between 120_0 and 120_1,120_1 and 120_2 etc. is all Δ t₁, then the delay between 120_1 and 120_N is N* Δt₁.Also due to loopback differential clocks cabling 112 is symmetrical with differential clocks cabling 111 consistent, therefore loopback differential clocks is walked Delay between extraction branch clock is each on line 112 is also Δ t.Assume again that on differential clocks cabling 111 node 120_N and On loopback differential clocks cabling 112, the delay between node 121_N is Δ t₂, then the delay between 120_0 and 121_0 is 2N*Δt₁+Δt₂。

Fig. 4 show as a example by 120_0,121_0 and 120_N, 121_N introduce the present invention reduce clock skew principle time Sequence figure.As follows by the sequential of output 151_0 and 151_N after phase interpolation clock buffer 105 in Fig. 1: 120_0 and Delay between 151_0 is N* Δ t₁+Δt₂/2+t_dly, t_dlyIt it is the unit internal latency of phase interpolation clock buffer 105； Delay between 120_N and 151_N is Δ t₂/2+t_dly.Unified on the basis of 120_0, then 151_0 and 151_N relative to The delay of 120_0 is N* Δ t₁+Δt₂/2+t_dly.In like manner understand, 151_0,151_1,151_2 ... 151_N is relative to 120_0 Delay equal.

As can be seen here, the present invention can be significantly reduced to the Skew of clock load, the most even can accomplish 0Skew。

The present invention proposes the method using clock phase interpolation to reduce clock Skew, first increases by one and walks with long clock The symmetrical consistent looped back clock cabling (long clock cabling carries out loopback) of line, every on long clock cabling and looped back clock cabling At individual clock output, the reverse clock of loopback of output on the forward clock that long clock cabling exports and looped back clock cabling is entered Line phase interpolation processing, i.e. adds phase interpolation clock buffer (CGBUF), then to the output clock on long clock cabling and On looped back clock cabling, the output clock of same position carries out slew rate adjustment, and a kind of phase interpolation circuit of recycling generates Phase place is positioned at the clock in two-way clock (forward clock and the reverse clock of loopback) phase place centre position and exports, thus realizes every The new clock of individual generation has approximately uniform clock phase at clock load, greatly reduces clock Skew.

Claims

1. one kind is reduced the method for skewed clock on long clock cabling, it is characterised in that: described method is first to increase by one with long The symmetrical consistent looped back clock cabling of clock cabling, the then output of each clock on long clock cabling and looped back clock cabling Place increases phase interpolation clock buffer (105), and generation phase place is positioned at the clock in two-way clock phase centre position and exports, Thus realize, at clock load (106) place, there is approximately uniform clock phase.

The method of skewed clock on reduction the most according to claim 1 long clock cabling, it is characterised in that: in described phase place Interpolated clock buffer (105) is the clock buffer realizing phase interpolation function, and this phase interpolation clock buffer (105) includes Shaping clock buffer (201), slew rate adjust circuit (202), phase interpolation circuit (203), differential comparator (204) With differential to single-ended buffer (205), shaping clock buffer (201) is for by long clock cabling and looped back clock cabling The two-pass DINSAR clock (141,142 and 143,144) drawn at each clock output be shaped as respectively rise/fall along the time and The two-pass DINSAR clock signal (211) that signal amplitude is consistent；When slew rate adjustment circuit (202) is used for adjusting two-pass DINSAR The slew rate of clock signal (211) diminishes to the requirement meeting phase interpolation circuit (203)；Phase interpolation circuit (203) is used for The two-pass DINSAR clock signal (212) adjusting slew rate is generated phase place be positioned in the middle of two-pass DINSAR clock signal phase The differential clock signal (213) of position；Differential comparator (204) is for poor by reverting to after differential clock signal (213) shaping Timesharing clock (214)；Differential to single-ended buffer (205) is used for differential clocks (214) is converted to single channel clock signal (151), then Deliver to clock load (106) place.