JP3805311B2 - Output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output circuit.
[0002]
[Prior art]
There is a semiconductor chip interface circuit in which a plurality of semiconductor chips are mounted on a printed circuit board and the like, and information transmission means between these chips uses, for example, serial bus wiring. Among them, there are semiconductor input / output circuits for handling minute amplitude signals and high frequency signals such as GTL (Gunning Transceiver Logic) bus specifications.
[0003]
In recent years, systems installed in household devices, communication devices, and industrial devices have been increasing in scale, such as information control processing circuits (microcontrollers, etc.) and general-purpose circuits (LCD drivers, I / O ports, In general, functional circuits such as RAM / ROM, etc. and dedicated circuits (digital tuner circuit, signal processing circuit, etc.) according to application are configured by mounting a plurality of semiconductor chips on one printed circuit board.
[0004]
Even today, when the scale of functional circuits that can be mounted on a single chip has increased dramatically due to the miniaturization technology of large-scale integrated circuits, for example, due to reasons such as the development period, development costs, or the use of technically common manufacturing processes, In the future, it is possible to use such a method for the time being. The plurality of functional circuits communicate information with each other by pattern wiring on the printed circuit board. Recently, however, the speed of these functional circuits and their peripheral devices is required due to an increase in the amount of information.
[0005]
For this reason, it is possible to increase the speed and efficiency of information transmission between functional circuits by compressing communication information by standardizing information formats, encoding information, etc., adding parallel transmission paths, and increasing the serial communication speed. Has been planned. For example, when the serial communication speed is increased, if the power supply noise generated by switching the output buffer when outputting data to the bus wiring is large, it may cause malfunction of the logic circuit and deterioration of the characteristics of the analog circuit. This effect becomes even more pronounced due to simultaneous switching by multiple output buffers.
[0006]
Therefore, conventionally I related to system configuration and information transfer format ² It is necessary to perform inter-chip communication according to bus specifications such as C (Inter Integrated Circuit) bus specifications and GTL bus specifications that prevent power supply noise by lowering the output signal voltage and reducing the Slew Rate.
[0007]
FIG. 13 is a schematic diagram of an example of GTL bus connection using general bidirectional serial bus wiring. The serial bus wiring 132 is a mutual bus wiring that mutually transmits information. Each functional circuit mounted on the semiconductor chip transmits information to the serial bus wiring 132 via an input / output circuit 131 configured by an input circuit and an output circuit. In this example, 8 bits of input / output circuits 131 mounted on each functional circuit are connected. The bus wiring 132 is connected to the termination voltage VTT having a lower potential than the positive power supply VDD supplied to the input / output circuit 131 via the termination resistors RT1 and RT2, and is connected to the ground via the load capacitors CT1 and CT2. Is done. When the bus wiring 132 is opened from the output buffer (output circuit), it becomes the VTT potential (logical logic high level (“H”)).
[0008]
The output buffer connected in parallel to the bus line 132 is an N-channel open drain (or NPN open collector) circuit, and the bus line 132 is connected to the ground GND through any of these output buffers. Voltage VOL (logic low level ("L")) potential. Therefore, the circuit configuration has an AND (logical product) function. The logic information transmitted on the bus wiring 132 is selectively taken into each functional circuit by the input circuit. In this example, the output circuit and the input circuit are described as one module. However, they may be individually mounted according to the application.
[0009]
FIG. 14 is a circuit diagram of the first prior art corresponding to the input / output circuit 131 shown in FIG. This circuit includes an output circuit OUT that outputs an output signal from the functional circuit to the serial bus wiring, and an input circuit IN that inputs an input signal from the serial bus wiring to the functional circuit. FIG. 15 shows operation waveforms of the circuit of FIG.
[0010]
When this circuit is connected to the serial bus wiring and the bus wiring is open from other output buffers, the potential of the internal output signal A changes from the ground side to the positive power supply side (logical value from "L" to "H" ) When changed (hereinafter referred to as rising or rising), the main output buffer N7 is turned off (hereinafter referred to as ON) from the conductive state (hereinafter referred to as ON), and the external input / output signal EB has a terminating resistance. Through the terminal voltage VTT. At this time, the absolute value | ΔV / Δt | (hereinafter referred to as Slew Rate) of the rate of voltage change with respect to the time of the signal EB is mainly determined by the termination resistors RT1 and RT2 and the load capacitors CT1 and CT2. For this reason, the delay time (hereinafter referred to as total output delay time Tdmax) required for transmitting logical information until the change of the internal output signal A is transmitted to the external output signal EB is also large.
[0011]
When the internal output signal A changes from the positive power supply side to the ground side (logic value changes from "H" to "L") (hereinafter referred to as falling or falling), the main output buffer N7 turns from OFF to ON. Thus, the external input / output signal EB is sharply lowered to the low voltage side output voltage VOL. At this time, since the output impedance of the main output buffer N7 is sufficiently small compared to the bias of the termination voltage VTT via the termination resistors RT1 and RT2, the influence of the signal EB on the Slew Rate is dominated by the resistor R1 and the capacitor C1 It becomes.
[0012]
Further, the capacitor C1 acts in a direction to correct for a steep voltage fluctuation due to an external factor of the bus wiring. For example, when the external input / output signal EB changes from the desired voltage to the positive power supply VDD side, the main bias signal CA is raised to the VDD side by the coupling operation of the capacitor C1, and the voltage between the gate and source of the main output buffer N7 Turns on when Vgs becomes large, and acts to make signal EB fall to the GND potential side. Conversely, when the signal EB changes to the GND side, the main output buffer N7 is turned off.
[0013]
The problem with this circuit is that the adjustment range of the Slew Rate is narrow because the adjustment of the Slew Rate when the external input / output signal EB falls is only the adjustment of the resistor R1 and the capacitance C1 with the CR time constant.
[0014]
When the Slew Rate is decreased, the total output delay time Tdmax is increased, and when the Slew Rate is increased, an overshoot occurs in the output waveform, which is a source of power supply noise.
[0015]
FIG. 16 is a circuit diagram of the second prior art corresponding to the output circuit OUT shown in FIG. This circuit includes two output buffers. If each is called a main output buffer and a sub-output buffer, the main output buffer N7 is a normal electric circuit similar to N7 in the first prior art (FIG. 14). This is an output buffer whose transistor size is determined by the low-voltage side output current IOL of the characteristic specification, and the sub output buffer N8 is connected in parallel for the purpose of further reducing the output impedance.
[0016]
To determine the transistor capacity of the output buffer of this circuit, first determine the transistor size of the main output buffer N7 based on the low voltage side output current IOL of the electrical characteristics specification, and then the falling of the external input / output signal EB In order to make it steep, the transistor capability when the output impedance is reduced is determined, and the transistor size of the slave output buffer N8 is determined so that both N7 and N8 have the capability.
[0017]
FIG. 17 shows operation waveforms of the circuit of FIG. In this circuit, the period during which the slave output buffer N8 is ON is a period in which the slave bias signal CB is higher than the threshold voltage (hereinafter referred to as VthN) of the N-channel MOS transistor N8, that is, the rising edge of the internal output signal A. This is only a momentary period from immediately after falling to after the delay time Td set by the delay circuit Delay has elapsed. Accordingly, only during this period when the internal output signal A falls, both the main output buffer N7 and the sub output buffer N8 are turned on, the output impedance is lowered, and the slew rate of the external input / output signal EB is increased. Thereafter, the normal output impedance is restored, and the Slew rate of the signal EB becomes normal.
[0018]
In this way, the Slew Rate is increased and sharply decreased just after the internal output signal A rises, and then the Slew Rate is decreased and slowed down so that the total output delay time Tdmax does not increase and the over (under) shoot occurs. Can be prevented. In this example, two output buffers are provided. However, if two or more output buffers connected in parallel are prepared, the output impedance can be controlled in more detail and the Slew Rate can be optimized. I can do it.
[0019]
FIG. 18 is a circuit diagram of an output circuit of the third prior art. The operation of this output circuit is almost the same as that of the second prior art (FIG. 16). The difference from the second prior art is that the signal for determining the timing to turn off the slave output buffer N8 is changed from the gate signal of the slave output buffer N8 to the drain signal, that is, the external input / output signal EB. Since the signal EB changes more slowly than the slave bias signal CB depending on the load capacity, the delay circuit is deleted, and the total output delay time Tdmax is adjusted by adjusting the circuit threshold voltage (hereinafter referred to as VthC) of the sense amplifier I7. To do.
[0020]
Further, by feeding back the external input / output signal EB to the sense amplifier I7, it becomes possible to correct the output impedance in accordance with voltage fluctuations caused by some external factor of the bus wiring. For example, when the potential of the signal EB fluctuates to the VDD potential side from the circuit threshold value VthC of the sense amplifier I7 for some reason, the slave output buffer N8 is turned ON / OFF at substantially the same timing as the main output buffer N7. Conversely, when it changes to the GND potential side, the slave output buffer N8 is always OFF.
[0021]
The first problem in the second and third prior art circuits is that a plurality of large buffers are prepared so as to satisfy the low voltage side output current IOL of the electrical characteristics specification while considering the desired change in output impedance. It is a point that must be done. For example, in order to halve the output impedance based on the output current IOL, an area about twice as large as the transistor size is required. For this reason, an increase in layout area is inevitable.
[0022]
In addition, in order to reduce the Slew Rate, even if a higher output impedance is desired, it cannot be set higher than the output impedance based on the output current IOL.
[0023]
The second problem in these circuits is that the margin of the transistor threshold voltage Vth (hereinafter referred to as Vth margin) becomes narrow due to variations in the manufacturing process of the delay circuit Delay and the sense amplifier I7. The timing to turn off the slave output buffer N8 needs to be set sufficiently before the external input / output signal EB reaches the ground GND. However, in the case of the second prior art, for example, the threshold voltage Vth is low. When the potential is varied, the total output delay time Tdmax is reduced, the timing for turning off the slave output buffer N8 is advanced, and the transistor capacity of the output buffer is increased more than necessary, thereby increasing the undershoot. Conversely, when the threshold voltage Vth varies to the high potential side, the delay time Tdmax increases, the timing for turning off the slave output buffer N8 is delayed, and the undershoot increases. Further, in the case of the third prior art, the delay time Tdmax becomes small when VthP is low N and high (the threshold voltage VthP of the P-channel MOS transistor is low and the threshold voltage VthN of the N-channel MOS transistor is high). Also, the delay time Tdmax becomes large when VthP is high N and low (VthP is high and VthN is low), and the same tendency as in the second prior art occurs.
[0024]
Moreover, the following patent documents 1 to 4 are disclosed.
[0025]
[Patent Document 1]
Japanese Patent Laid-Open No. 9-200033
[Patent Document 2]
JP-A-8-274616
[Patent Document 3]
US Pat. No. 6,242,942
[Patent Document 4]
US Pat. No. 6,184,730
[0026]
[Problems to be solved by the invention]
Therefore, since the output impedance of the output buffer cannot be controlled with a wide Vth margin without increasing the layout area, optimal Slew Rate control cannot be performed, resulting in an increase in signal delay time or an over (under) output waveform. A shoot occurred and became a source of power supply noise. Therefore, it is difficult to increase the circuit operation speed.
[0027]
An object of the present invention is to provide an output circuit that reduces noise and operates at high speed.
[0028]
[Means for Solving the Problems]
According to one aspect of the present invention, after an internal signal is input and the rising edge of the internal signal is changed, The current path of the bias signal line to the Bias signal line after falling change of Current path Conduct A bias control unit for supplying a bias signal, a holder unit for holding the bias signal of the bias signal line with the bias signal supplied by the bias control unit as an input, and biasing the output line with the bias signal of the bias signal line as an input. An output circuit having an output section is provided. After change of internal signal of bias control unit Continuity A field effect transistor having a gate and a drain connected to each other or a bipolar transistor having a base and a collector connected to each other are connected to the current path.
[0029]
Not only when the internal signal rises but also when it falls Bias signal line Current path Conduct Therefore, it is possible to optimize the output impedance of the output unit and perform optimum Slew Rate control. Thus, overshoot and undershoot of the output waveform can be prevented without increasing the signal delay time, and noise of the power supply can be prevented. In addition, the output signal can be reduced in voltage and the circuit operation speed can be increased.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
First, the principle of the first embodiment of the present invention will be described with reference to FIGS. FIG. 13 shows a schematic diagram of an example of GTL bus connection using general bidirectional serial bus wiring. The detailed description of FIG. 13 is the same as described above. FIG. 2 is a circuit diagram of the semiconductor input / output circuit. In the figure, IN is an input circuit, and OUT is an output circuit. 2 corresponds to the input / output circuit 131 shown in FIG. 13, and FIG. 1 shows the circuit configuration of the output circuit OUT shown in FIG.
[0031]
FIG. 1 is a schematic diagram illustrating a configuration example of an output circuit of a semiconductor input / output circuit. The delay unit DLY outputs a delay signal AD obtained by adding a delay time to the internal output signal A. The bias controller BCNT inputs the internal output signal A and the delay signal AD, and outputs a bias signal CA on the bias signal line. The holder unit HOLD holds the bias signal CA of the bias signal line with the bias signal CA supplied by the bias control unit BCNT as an input. The output unit OT receives the bias signal CA of the bias signal line and outputs an external output signal EB to the output line. The output line of the output unit OT is connected to the serial bus wiring 132 in FIG.
[0032]
Next, a description will be given with reference to FIG. The input circuit IN has an operational amplifier AMP1. The operational amplifier AMP1 inputs the external input / output signal EB to the negative input terminal, inputs the reference voltage Vref to the positive input terminal, and outputs the internal input signal X.
[0033]
Next, the configuration of the output circuit OUT will be described. Inverters I1 and I2 are delay units DLY, circuit BCNT is a bias control unit, circuit HOLD is a holder unit, circuit N7 is an output unit, signal A is an internal output signal, signals AD and ADN are delay signals, signal CA is a main bias signal, The signal EB corresponds to an external input / output signal. The delay unit DLY is a delay circuit that delays the input signal by the delay time Td due to the gate delay of the CMOS transistor, the bias control unit BCNT is a combinational circuit that biases the main bias signal CA, and the holder unit HOLD is a sense amplifier ( Inverter) A circuit for re-biasing the main bias signal by the circuit threshold value VthC of I4 and I5, and the output unit OT is an N-channel open drain output buffer by gate control of the main bias signal CA.
[0034]
The delay unit DLY is a series connection of inverters I1 and I2, and is configured by an even number of inverters. The delay unit DLY outputs a delay signal AD obtained by adding a delay time to the internal output signal A. The output unit OT includes an N-channel MOS field effect transistor (MOSFET) N7. Hereinafter, unless otherwise specified, a transistor refers to a MOSFET.
[0035]
Next, the configuration of the bias control unit BCNT will be described. P-channel MOS transistor P1 has a gate connected to internal output signal A and a source connected to positive power supply potential VDD. The P-channel MOS transistor P2 has a gate connected to the delay signal AD, a source connected to the drain of the transistor P1, and a drain connected to the bias signal CA line. The N-channel MOS transistor N1 has a gate and a drain connected to the bias signal CA line. The N-channel MOS transistor N2 has a gate connected to the internal output signal A, a source connected to the ground GND, and a drain connected to the source of the transistor N1.
[0036]
The inverter I3 outputs a signal ADN obtained by logically inverting the delay signal AD. P-channel MOS transistor P3 has a gate connected to internal output signal A and a source connected to positive power supply potential VDD. In the P-channel MOS transistor P4, the gate is connected to the signal ADN, the source is connected to the drain of the transistor P3, and the drain is connected to the line of the bias signal CA. N-channel MOS transistor N3 has a gate connected to signal ADN and a drain connected to the line of bias signal CA. The N-channel MOS transistor N4 has a gate connected to the internal output signal A, a source connected to the ground GND, and a drain connected to the source of the transistor N3.
[0037]
Next, the structure of the holder part HOLD is demonstrated. The sense amplifiers (inverters) I4 and I5 output a logical inversion signal of the bias signal CA. P-channel MOS transistor P5 has a gate connected to the output of inverter I4 and a source connected to positive power supply potential VDD. The P-channel MOS transistor P6 has a gate connected to the internal output signal A, a source connected to the drain of the transistor P5, and a drain connected to the bias signal CA line. N-channel MOS transistor N5 has a gate connected to internal output signal A and a drain connected to a line of bias signal CA. N-channel MOS transistor N6 has a gate connected to the output of inverter I5, a source connected to ground GND, and a drain connected to the source of transistor N5.
[0038]
The transistor N7 has a gate connected to the bias signal CA line, a source connected to the ground GND, and a drain connected to the external input signal EB line.
[0039]
3 shows operation waveforms of the output circuit OUT of FIG. 2, and FIG. 4 shows the states of the functional circuits. Hereinafter, the circuit operation will be described with reference to FIGS. 2, 3, and 4.
[0040]
First, during the period I in FIG. 3, when the internal output signal A rises, the transistors P2, P5, N2, N3, N4, and N5 are turned on and the other transistors are turned off. However, since the gate and the drain of the transistor N1 are connected to each other, on / off switching does not occur. The current paths of the transistors N3 and N4 are conducted with respect to the line of the bias signal CA. The main bias signal CA sharply falls to the GND side. Then, the main output buffer N7 starts to turn off (OFF) with a short delay time, and the external input / output signal EB starts to rise to the positive power supply VTT side via the termination resistors RT1 and RT2. Here, before the bias signal CA reaches GND (low level) (preferably, before reaching the threshold voltage VthN of the transistor N1), the period II is switched.
[0041]
Next, in period II, when the rising change of the signal A is transmitted to the delay signals AD and ADN via the delay circuits I1 and I2, the transistor N3 is turned off, and the main bias signal CA is applied to the N-channel MOS transistor N2 and the gate and drain. It is biased only by the current path of the N-channel MOS transistor N1 connected between them and operated in the saturation region. Since the gate and drain of the transistor N1 are connected to each other, the main bias signal CA is once stabilized at a potential near the threshold voltage VthN of the transistor N1. Then, the output impedance of the main output buffer N7 becomes high. As a result, the Slew rate of the signal EB is reduced, and overshoot can be prevented.
[0042]
Next, in period III, when the potential of the main bias signal CA falls below the circuit threshold value VthC of the sense amplifier I5, the transistor N6 is turned on, and the current paths of the transistors N5 and N6 are conducted to the bias signal CA line. To do. Then, the main bias signal CA is finally held at the GND potential. Therefore, the main output buffer N7 is completely turned off, and the signal EB becomes the VTT potential (high level).
[0043]
Next, when the signal A falls in the period IV, the transistors P3 and P4 are turned on and the transistors N2 and N5 are turned off. Since the current paths of the transistors P3 and P4 are conducted with respect to the bias signal CA line, the main bias signal CA is raised to the VDD side. The main output buffer N7 starts to turn on with a short delay time, and the signal EB starts to fall to the GND side.
[0044]
Next, in the period V, when the falling change of the signal A is transmitted to the delay signals AD and ADN via the delay circuits I1 and I2, the transistor P4 is turned off and the transistor P2 is turned on. Since the current paths of the transistors P1 and P2 are conducted with respect to the line of the bias signal CA, the main bias signal CA is slowly raised to the VDD side via the transistor P2 and the transistor P1 having a small transistor capability. The main output buffer N7 begins to turn on gradually, and the signal EB further approaches the GND potential. As a result, the Slew rate of the signal EB becomes small and undershoot can be prevented.
[0045]
Next, in the period VI, when the potential of the main bias signal CA exceeds the circuit threshold value VthC of the sense amplifier I4, the transistor P5 is turned on. In addition to the current paths of the transistors P1 and P2, the current paths of the transistors P5 and P6 are conducted to the bias signal CA line, so that the main bias signal CA finally becomes the positive power supply potential VDD. Therefore, the main output buffer N7 is completely turned on, and the signal EB becomes the low voltage side output voltage VOL, that is, the drain-source voltage Vds (low level) of the main output buffer N7.
[0046]
The first feature of this circuit system is that the output impedance of the main output buffer N7 for biasing the external input / output signal EB is adjusted by the gate bias. For this reason, it is not necessary to prepare a plurality of large buffers, and only an output buffer necessary for satisfying the low voltage side output current IOL may be prepared, and the layout area can be reduced. The circuit configuration of the bias control unit and the holder unit is somewhat complicated, but this is not a problem because the layout area is sufficiently small compared to the output buffer. For example, when a large number of input / output circuits must be connected in parallel to the bus wiring, such as a functional circuit such as a data input / output port, this reduction in layout area is a particularly significant advantage.
[0047]
The second feature of this circuit system is that the final gate potential of the main output buffer is determined by the holder unit. To prevent overshoot, the time until the potential of the main bias signal CA, whose voltage change has slowed down by the bias controller, reaches the circuit threshold value VthC of the sense amplifier, is adjusted by adjusting the sense amplifier. It can be set sufficiently longer than the delay time set by a normal delay circuit, and the Slew Rate of the external input / output signal EB can be adjusted in a very wide range. The sense amplifier is an inverting circuit composed of a pair of P-channel and N-channel MOS transistors, and the circuit threshold VthC can be easily adjusted by the ratio of these transistor capabilities. For example, to shift the circuit threshold VthC to the positive power supply side, the capability of the P channel MOS transistor is increased, and to shift to the ground side, the capability of the N channel MOS transistor is increased. Therefore, it is easy to prevent overshoot according to conditions such as the termination power supply VTT, termination resistance, load capacitance, and transmission line parameters such as the characteristic impedance Z0 of the bus wiring.
[0048]
A third feature of this circuit system is that the Slew Rate at the time of rising and the rising of the external input / output signal EB can be optimized and designed separately. When the signal EB rises, the main output buffer N7 is turned off and the bus wiring potential is raised to the termination voltage VTT via the termination resistor, whereas when EB falls, the main output buffer N7 is turned off. This is an operation that turns ON and falls to the low voltage output voltage VOL by the low voltage output current IOL of the main output buffer N7. Also, since the positive power supply VDD is generally higher in potential than the termination voltage VTT, the potential difference from the positive power supply potential VDD to the vicinity of the threshold voltage VthN and the potential difference from the threshold voltage VthN to GND are greatly different. The shape of the operation waveform required for the main bias signal CA differs between when the signal EB rises and when it falls. The operation waveform required for the main bias signal CA is determined by the three timings of the internal output signal A, the delay signal of the internal output signal A, and the bias by the holder unit, and at the rising edge of the external input / output signal EB, This is achieved by optimizing the N-channel side of the holder HOLD and the bias controller BCNT and the P-channel side of the holder HOLD when the signal EB falls.
[0049]
In the above, a combination of input waveforms is considered so that a through current path does not occur as much as possible in the bias control unit and the holder unit. However, the through current is temporarily passed and the main bias signal CA is set to an arbitrary potential between VDD and GND. It is also possible to set to. Further, although two types of signals having different timings, that is, the signal A and the delay signals AD and ADN are used as the input of the bias control unit, more various controls can be performed by providing different timings. It is obvious that the present invention can be easily applied not only to an N-channel open drain output buffer but also to a push-pull type circuit using a CMOS or bipolar transistor. Furthermore, the present invention is not particularly limited to the bias to the pattern wiring on the printed circuit board, and can be applied to the wiring bias in the semiconductor chip, for example. Needless to say, the present invention is not limited to serial bus wiring and can also be applied to general signal wiring.
[0050]
As described above, the bias control by multiple timing signals generated by the delay circuit and further biasing by the gate signal potential optimize the output buffer gate signal and optimize the output buffer output impedance control. Good.
[0051]
By optimizing the output buffer gate signal by biasing it at multiple timings, the output impedance control of the output buffer is optimized, so that a wide threshold voltage Vth margin can be achieved without increasing the layout area of the output circuit. Thus, the optimum Slew Rate control of the serial bus signal transmitted by the pattern wiring on the printed circuit board becomes possible. Accordingly, it is possible to prevent an overshoot of the output waveform without increasing the total output delay time Tdmax of the signal and to speed up the circuit operation.
[0052]
Next, problems of the output circuit OUT in FIG. 2 will be described. In the output circuit OUT of FIG. 2, when the output voltage A rises, the gate voltage of the N-channel transistor N7 is once biased in the vicinity of the threshold voltage VthN, so that overshoot can be suppressed at the rise. Although it is possible, it is difficult to provide a period for biasing near the threshold voltage VthN because the gate bias of the P-channel transistor is controlled at the fall. For this reason, the output impedance of the transistor N7 cannot be optimized, resulting in a trade-off between undershoot suppression and delay time reduction, making circuit adjustment difficult.
[0053]
Next, the output circuit OUT according to the present embodiment will be described with reference to FIGS. FIG. 5 is a schematic diagram illustrating a configuration example of the output circuit of the semiconductor input / output circuit. FIG. 5 is the same as FIG. 1 except that a current path PTH is added to the bias controller BCNT of FIG. FIG. 6 is a circuit diagram of the semiconductor input / output circuit. FIG. 5 shows a circuit configuration of the output circuit OUT of FIG. The circuit of FIG. 6 is obtained by adding a current path PTH to FIG.
[0054]
The configuration of the current path PTH will be described with reference to FIG. The inverter I11 outputs a signal obtained by logically inverting the bias signal CA. The N-channel MOS transistor N11 has a gate and a drain connected to the bias signal CA line and applies a threshold voltage VthN to the bias signal CA line. N-channel MOS transistor N12 has a gate connected to the output of inverter I11, and a drain connected to the source of transistor N11. The N-channel MOS transistor N13 has a gate connected to the signal ADN, a drain connected to the source of the transistor N12, and a source connected to the ground GND.
[0055]
FIG. 7 shows an operation waveform of the output circuit OUT of FIG. 6, and FIG. 8 shows a state of each functional circuit. FIG. 8 is obtained by adding the states of the transistors N11, N12, and N13 to the state of FIG. For other transistors, FIGS. 4 and 8 are the same. Since the gate and the drain of the transistor N11 are connected to each other, on / off switching does not occur. The transistors N12 and N13 are turned on simultaneously in the period I and the period V. That is, the current path PTH of the transistors N11, N12, and N13 is conducted to the bias signal CA line in the periods I and V. In other periods, the operation of the circuit in FIG. 6 and the circuit in FIG. 2 are the same.
[0056]
In the period I, in addition to the current path PTH, the current paths of the transistors N3 and N4 are also conducted with respect to the line of the bias signal CA. Therefore, the operations of the circuit of FIG. 6 and the circuit of FIG. In the period I, the current path PTH is not necessarily conducted. Later, in the second embodiment, a circuit in which the current path PTH is not conducted in the period I will be described.
[0057]
In the period V, the current paths of the transistors P1 and P2 and the current paths of the transistors N11, N12, and N13 are conducted with respect to the line of the bias signal CA. As a result, the current 60 shown in FIG. 6 flows through the current path. However, since the gate and drain of the transistor N11 are connected to each other, the bias signal CA becomes the threshold voltage VthN of the transistor N11 as shown in the area 71 of FIG.
[0058]
If the output circuit is manufactured by the same semiconductor process, the threshold voltages VthN of the N-channel MOS transistors N1, N11, N7 are almost the same. Thereby, in the periods II and V, the signal EB has a reduced Slew Rate and can prevent overshoot.
[0059]
This will be described more specifically. In the period IV, the current paths of the transistors P3 and P4 are conducted with respect to the line of the bias signal CA, and the main bias signal CA is sharply raised to the VDD side. Then, the main output buffer N7 starts to turn on with a short delay time, and the external input / output signal EB starts to fall to the low voltage side output voltage VOL. Here, before the bias signal CA reaches VDD (high level) (preferably, before reaching the threshold voltage VthN of the transistor N11), the period V is switched.
[0060]
Next, in the period V, the current paths of the transistors P1 and P2 and the current paths of the transistors N11, N12, and N13 are conducted with respect to the line of the bias signal CA. Since the transistor N11 operates in a saturation region with the gate and drain connected, the main bias signal CA is stabilized at a potential in the vicinity of the threshold voltage VthN of the transistor N11 as shown in an area 71 of FIG. Then, the output impedance of the main output buffer N7 becomes high. As a result, as shown in the area 72 of FIG. 7, the Slew Rate of the signal EB is reduced, and undershoot can be prevented.
[0061]
Next, in the period VI, when the potential of the main bias signal CA exceeds the circuit threshold value VthC of the sense amplifier I4, the transistors P5 and P6 are turned on. In addition to the current paths of the transistors P1 and P2, the current paths of the transistors P5 and P6 are conducted to the bias signal CA line, so that the main bias signal CA finally becomes the positive power supply potential VDD. Therefore, the main output buffer N7 is completely turned on, and the signal EB becomes the low voltage side output voltage VOL, that is, the drain-source voltage Vds (low level) of N7.
[0062]
Here, the inverters I4 and I5 may be a single inverter. The one inverter outputs a logic inversion signal of the bias signal CA to the gates of the transistors P5 and N6. In this case, the circuit threshold value VthC for determining the start timing of the periods III and VI is the same. However, as shown in FIG. 6, by providing the two inverters I4 and I5, the signal levels of the hold start timings of the periods III and VI are separately set according to the circuit threshold value VthC of the inverters I4 and I5, respectively. There is an advantage that can be controlled.
[0063]
Note that when the current path PTH in FIG. 6 is turned on, current is consumed. However, since the transistors N11 to N13 constituting the current path PTH are smaller in size than the transistor N7, the current flowing through the current path PTH is small. Furthermore, the period during which the current path PTH is conductive is extremely short. Therefore, the current consumption of the current path PTH can be extremely small.
[0064]
9A to 9C show simulation voltage waveforms by SPICE (Simulation Program with Integrated Circuit Emphasis). The vertical axis represents voltage, and the horizontal axis represents time. FIG. 9A shows the voltage waveform of the internal output signal A. FIG.
[0065]
FIG. 9B shows a voltage waveform of the bias signal CA. A waveform 91 is the bias signal CA of the circuit of FIG. 6, and a waveform 92 is the bias signal CA of the circuit of FIG. Since the waveform 91 is once stabilized at the threshold voltage VthN at the time of falling of the internal output signal A and thereafter, the rising of the waveform 91 can be delayed as compared with the waveform 92.
[0066]
FIG. 9C shows the voltage waveform of the external input / output signal EB. A waveform 93 is the external input / output signal EB of the circuit of FIG. 6, and a waveform 94 is the external input / output signal EB of the circuit of FIG. At the time when the internal output signal A falls and thereafter, the waveform 93 can slow down the fall compared to the waveform 94 (by reducing the Slew Rate) to suppress undershoot.
[0067]
According to this embodiment, a plurality of N-channel open drain output buffers N7 that output signals to the bus wiring terminated and connected to the high potential VTT side are used. At that time, not only when the internal output voltage A rises but also when it falls, a period in which a current path is intentionally generated and the gate voltage of the N-channel buffer N7 is once biased near the threshold voltage VthN By providing II and V, the output impedance of the output buffer N7 can be optimized, and overshoot and undershoot can be suppressed without increasing the delay time. Accordingly, it is possible to reduce the voltage and speed of the bus signal without causing power supply noise at both the rising and falling edges of the output voltage EB.
[0068]
(Second Embodiment)
FIG. 10 is a circuit diagram of the output circuit OUT according to the second embodiment of the present invention. The output circuit of FIG. 10 is obtained by adding a circuit 100 to the output circuit OUT of FIG. The additional circuit 100 is an N-channel MOS transistor N14. The transistor N14 has a gate connected to the output of the inverter I1, a drain connected to the source of the transistor N13, and a source connected to the ground GND.
[0069]
FIG. 11 shows the state of each functional circuit of the output circuit of FIG. The state of FIG. 11 is obtained by adding the state of the transistor N14 to the state of FIG. The transistor N14 is turned on only during the periods IV, V, and VI. As a result, the current paths of the transistors N11, N12, N13, and N14 are conducted to the bias signal CA line only in the period V. In FIG. 8, the current path PTH is conducted in the periods I and V. However, as shown in FIG. 11, it is sufficient that the current path is conducted only in the period V.
[0070]
(Third embodiment)
FIG. 12 is a circuit diagram of the output circuit OUT according to the third embodiment of the present invention. The output circuit of FIG. 12 is obtained by adding a circuit 120 to the output circuit OUT of FIG. The configuration of the additional circuit 120 will be described. The delay inverter I2D outputs a signal ADD obtained by delaying and logically inverting the signal AD. A signal ADD is input to the gate of the transistor N13. P-channel MOS transistor P3D has a gate connected to internal output signal A and a source connected to positive power supply potential VDD. The P-channel MOS transistor P4D has a gate connected to the signal ADD, a source connected to the drain of the transistor P3D, and a drain connected to the line of the bias signal CA. N-channel MOS transistor N3D has a gate connected to signal ADD and a drain connected to the line of bias signal CA. N-channel MOS transistor N4D has a gate connected to internal output signal A, a source connected to ground GND, and a drain connected to the source of transistor N3D.
[0071]
In the circuit of FIG. 6, the bias control unit BCNT is controlled at two kinds of change timings of the internal output signal A and the signal AD obtained by delaying the internal output signal A by a predetermined time Tdx. On the other hand, in the circuit of FIG. 12, there are three types of change timing: an internal output signal A, a signal AD obtained by delaying the internal output signal A by a predetermined time Tdy, and a signal ADD obtained by delaying the signal AD by a predetermined time Tdz. The bias control unit BCNT is controlled by. This makes it possible to control the bias signal CA in the periods I and IV of FIG. 7 with more detailed timing and bias.
[0072]
In other words, the bias control unit BCNT generates a line of the bias signal CA during that time in addition to the current paths in the periods I and IV after the change of the internal output signal A and the current paths in the periods II and V after the delay time. Further, another current path can be provided to supply a bias signal.
[0073]
In the first to third embodiments, examples of two types and three types of timing are shown, but the timing can be further subdivided or adjusted according to the voltage and the delay time.
[0074]
In the first to third embodiments, the main output buffer N7 may be a P-channel MOS transistor. In that case, all the polarities of the transistors may be reversed.
[0075]
The transistor is not limited to a MOS field effect transistor, and may be a bipolar transistor. In that case, the N-channel and P-channel MOS field effect transistors may be replaced with NPN and PNP bipolar transistors, respectively. The transistors N1 and N11 whose gates and drains are interconnected may be bipolar transistors whose bases and collectors are interconnected.
[0076]
The gate of the transistor N7 receives a bias signal CA that is controlled by the transistors N1 and N11 to the threshold voltage VthN. Therefore, the transistors N1, N11, and N7 may be field effect transistors or bipolar transistors having the same polarity. An N-channel MOS field effect transistor is particularly preferable.
[0077]
The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
[0078]
The embodiment of the present invention can be applied in various ways as follows, for example.
[0079]
(Supplementary Note 1) A bias control unit that inputs an internal signal and supplies a bias signal by providing a current path in the bias signal line after the rising change and the falling change of the internal signal;
A holder unit for holding a bias signal of the bias signal line with a bias signal supplied by the bias control unit as an input;
An output unit that applies a bias signal of the bias signal line as an input and applies a bias to the output line;
An output circuit in which a field effect transistor in which a gate and a drain are connected to each other or a bipolar transistor in which a base and a collector are connected to each other are connected to a current path provided after a change in an internal signal of the bias control unit.
(Additional remark 2) Furthermore, it has a delay part which outputs a delay signal which gave delay time to the internal signal,
The bias control unit inputs the internal signal and the delay signal, and supplies a bias signal by providing another current path in the bias signal line after the change of the internal signal and before the delay time elapses. The output circuit described.
(Additional remark 3) The said output part is an output circuit of Additional remark 1 which gives a bias to the mutual bus wiring which mutually transmits information.
(Supplementary note 4) The output circuit according to Supplementary note 1, wherein a MOS field effect transistor having a gate and a drain connected to each other is connected to the current path.
(Supplementary note 5) The output circuit according to Supplementary note 4, wherein the MOS field effect transistor uses a bias signal of the bias signal line as a threshold voltage of the field effect transistor.
(Additional remark 6) The said output part is an output circuit of Additional remark 4 comprised by one MOS field effect transistor.
(Supplementary note 7) In addition to the current path after the change of the internal signal and the current path after the delay time, the bias control unit provides another current path in the bias signal line during the time to bias The output circuit according to appendix 2, which supplies a signal.
(Supplementary note 8) The output circuit according to supplementary note 1, wherein the holder unit includes an inverter that inputs the bias signal, and holds the bias signal in accordance with a circuit threshold value of the inverter.
(Supplementary Note 9) The holder unit has two inverters for inputting the bias signal, and holds signals at the rising edge and the falling edge of the bias signal according to the circuit thresholds of the two inverters, respectively. The output circuit according to appendix 1, wherein the level is determined.
(Additional remark 10) The said output part is an output circuit of Additional remark 1 comprised with a field effect transistor or a bipolar transistor.
(Additional remark 11) The said output part is an output circuit of Additional remark 1 comprised by one MOS field effect transistor.
(Supplementary Note 12) In the bias controller, the first current path provided in the bias signal line after the change of the internal signal connects the bias signal line to a low level or a high level, and the bias signal line after the delay time. The output circuit according to appendix 4, wherein the second current path provided in the circuit connects the bias signal line to a MOS field effect transistor having the gate and drain connected to each other.
(Supplementary Note 13) The bias control unit may apply the second signal to the bias signal line before the bias signal line reaches a low level or a high level after providing the first current path in the bias signal line. The output circuit according to appendix 12, wherein a current path is provided.
(Supplementary Note 14) The bias control unit may include the bias signal line before the bias signal line reaches the threshold voltage of the MOS field effect transistor after providing the first current path to the bias signal line. 13. The output circuit according to appendix 12, wherein the second current path is provided in the output circuit.
(Supplementary note 15) The output according to supplementary note 14, wherein the bias control unit sets the bias signal of the bias signal line to a threshold voltage of the field effect transistor by providing the second current path in the bias signal line. circuit.
(Supplementary note 16) The output circuit according to supplementary note 6, wherein the MOS field effect transistor in the current path of the bias control unit and the MOS field effect transistor in the output unit are field effect transistors having the same polarity.
(Supplementary note 17) The output circuit according to supplementary note 16, wherein the MOS field effect transistor in the current path of the bias control unit and the MOS field effect transistor in the output unit are N-channel MOS field effect transistors.
(Supplementary note 18) Supplementary note 1, wherein in the bias control unit, a current path provided in the bias signal line after the rising change of the internal signal is different from a current path provided in the bias signal line after the falling change of the internal signal. Output circuit.
(Supplementary note 19) The output circuit according to supplementary note 2, wherein the delay unit includes an even number of inverters.
(Supplementary note 20) The output circuit according to supplementary note 1, wherein the output unit applies a bias to a GTL (Gunning Transceiver Logic) bus wiring.
[0080]
【The invention's effect】
As explained above, not only when the internal signal rises but also when it falls Bias signal line Current path Conduct Therefore, it is possible to optimize the output impedance of the output unit and perform optimum Slew Rate control. Thus, overshoot and undershoot of the output waveform can be prevented without increasing the signal delay time, and noise of the power supply can be prevented. In addition, the output signal can be reduced in voltage and the circuit operation speed can be increased.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a configuration of an output circuit of a semiconductor input / output circuit.
FIG. 2 is a circuit diagram of a semiconductor input / output circuit.
FIG. 3 is a waveform diagram showing an operation of the output circuit of FIG. 2;
4 is a diagram illustrating a state of each functional circuit in FIG. 2;
FIG. 5 is a schematic diagram showing a configuration of an output circuit of a semiconductor input / output circuit.
FIG. 6 is a circuit diagram of a semiconductor input / output circuit.
7 is a waveform diagram showing an operation of the output circuit of FIG. 6. FIG.
8 is a diagram illustrating a state of each functional circuit in FIG. 6;
9A to 9C are diagrams showing simulation voltage waveforms by SPICE.
FIG. 10 is a circuit diagram of an output circuit.
11 is a diagram illustrating a state of each functional circuit of the output circuit of FIG. 10;
FIG. 12 is a circuit diagram of an output circuit.
FIG. 13 is a schematic diagram of a bus connection example.
FIG. 14 is a circuit diagram of a first prior art.
FIG. 15 is a diagram showing operation waveforms of the first prior art.
FIG. 16 is a circuit diagram of a second prior art.
FIG. 17 is a diagram showing operation waveforms of the second prior art.
FIG. 18 is a circuit diagram of a third prior art.
[Explanation of symbols]
AMP1 operational amplifier
BCNT bias controller
C1 capacity
CT1, CT2 load capacity
Delay Delay circuit
HOLD holder
I1, I2 delay circuit
I3, I6, I11 Inverter circuit
I4, I5, I7 sense amplifier
IN input circuit
N1-N6 N-channel MOS transistors
N7 main output buffer
N8 secondary output buffer
N11 to N13 N-channel MOS transistors
NR1-NR3 NOR circuit
OUT output circuit
P1-P6 P-channel MOS transistor
RT1, RT2 termination resistor
R1, R2 resistance
S1 Schmitt circuit
A, A1 to A8 Internal output signal
AD, AND delay signal
CA (Main) Bias signal
CB secondary bias signal
EB external input / output signal
GND Ground
Vref reference voltage
VDD Positive power supply (positive voltage)
VTT termination power supply (termination voltage)
VthN N-channel MOS transistor threshold voltage
VOL Low voltage output voltage
X, X1 to X8 Internal input signal

Claims (10)

Enter the internal signal, the following rising transition of the internal signal to conduct current path of the bias signal line, the after falling transition of the internal signal by conducting current path of the bias signal line bias control for supplying a bias signal And
A holder unit for holding a bias signal of the bias signal line with a bias signal supplied by the bias control unit as an input;
An output unit that applies a bias signal of the bias signal line as an input and applies a bias to the output line;
An output circuit in which a field effect transistor having a gate and a drain connected to each other or a bipolar transistor having a base and a collector connected to each other are connected to a current path conducted after a change of an internal signal of the bias control unit. Furthermore, it has a delay unit that outputs a delay signal obtained by adding a delay time to the internal signal,
The bias controller receives the internal signal and the delay signal, and conducts the first current path of the bias signal line after the change of the internal signal and before the delay time elapses, thereby changing the internal signal. 2. The output circuit according to claim 1, wherein the bias signal is supplied by conducting the second current path of the bias signal line later and after the delay time has elapsed .   2. The output circuit according to claim 1, wherein a MOS field effect transistor having a gate and a drain connected to each other is connected to the current path.   4. The output circuit according to claim 3, wherein the MOS field effect transistor uses a bias signal of the bias signal line as a threshold voltage of the field effect transistor.   The output circuit according to claim 3, wherein the output unit includes one MOS field effect transistor. In the bias control unit, before Symbol first current path connects said bias signal line to a low level or a high level, before Symbol second current path, said bias signal line to each other the gate and drain 3. The output circuit according to claim 2 , wherein the output circuit is connected to a connected MOS field effect transistor. The bias control unit, before said bias signal line after conducting the first current path of the bias signal line reaches a threshold voltage of said MOS field effect transistor, the first of said bias signal line the output circuit according to claim 6 wherein Ru is conducting second current path. The bias control unit, by Rukoto to conduct the second current path of the bias signal line, the output circuit according to claim 7 wherein the bias signal of the bias signal line to the threshold voltage of the field effect transistor .   6. The output circuit according to claim 5, wherein the MOS field effect transistor in the current path of the bias control unit and the MOS field effect transistor in the output unit are field effect transistors having the same polarity. In the bias control unit, according to claim 1 wherein after the rising transition of the internal signal in a current path that Ru is electrically connected to the bias signal line and the internal signal falling Ru is electrically connected to the bias signal line after the change current path is different current paths The output circuit described.

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