JP5082527B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  In USB (Universal Serial Bus) 2.0, HS (High Speed), FS (Full Speed), and LS (Low Speed) transfer modes are prepared. In these HS, FS, and LS modes, 480 Mbps and 12 Mbps, respectively. Data transfer is performed at 1.5 Mbps. In USB, as an electrical characteristic required for the transmission circuit for the LS mode, the rise time and fall time of the output signal are within the range of 75 to 300 ns with respect to the load capacitance in the wide range of 50 to 350 pf. Is stipulated. In this case, a USB device that supports only the HS and FS modes does not require such a transmission circuit for the LS mode. However, in a USB host or a USB device that supports the LS mode, it is necessary to provide a transmission circuit for the LS mode.

  As a conventional example for realizing such a transmission circuit for the LS mode, a first conventional example in which a capacitor for adjusting a slew rate is provided at an output node of the transmission circuit, or a gate control signal of a transistor constituting the transmission circuit is standardized. There is a second conventional example that is complicatedly controlled to satisfy.

However, in the first and second conventional examples, USB 2.0 HS mode data transfer is not considered. Further, when a large capacity for adjusting the slew rate is provided at the output node of the transmission circuit as in the first conventional example, there is a problem that the circuit becomes large and data transfer in the HS mode becomes difficult. In the second conventional example, since the control of the gate control signal is complicated, there is a problem that the circuit becomes complicated and large in scale.
JP 2000-49585 A JP 2001-196916 A

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an integrated circuit device capable of realizing data transmission in the first and second transfer modes with a small-sized circuit. And providing an electronic device including the same.

  The present invention is a circuit for transmitting data in a first transfer mode via first and second signal lines constituting a differential pair, and a first transmission driver for driving the first signal line And a first transmission circuit for a first transfer mode having a second transmission driver for driving the second signal line, and the first and second signal lines constituting a differential pair. A circuit that transmits data in a second transfer mode that is faster than the first transfer mode, the third transmission driver driving the first signal line, and the second signal line And a second transmission circuit for the second transfer mode having a fourth transmission driver, and a first P-type transistor constituting the first transmission driver for the first transfer mode; A third P-type transistor constituting the third transmission driver for two transfer modes is A first N-type transistor formed in the first P-type transistor region and constituting the first transmission driver for the first transfer mode, and the third transmission driver for the second transfer mode are constituted. A third N-type transistor that is formed in the first N-type transistor region and that constitutes the second transmission driver for the first transfer mode and a second transfer mode The fourth P-type transistor constituting the fourth transmission driver is formed in the second P-type transistor region, and the second N-type constituting the second transmission driver for the first transfer mode is formed. The transistor and the fourth N-type transistor constituting the fourth transmission driver for the second transfer mode are related to the integrated circuit device formed in the second N-type transistor region.

  According to the present invention, the P-type transistor constituting the transmission driver for the first transfer mode and the P-type transistor constituting the transmission driver for the second transfer mode are formed in the same transistor region. Further, the N-type transistor constituting the transmission driver for the first transfer mode and the N-type transistor constituting the transmission driver for the second transfer mode are formed in the same transistor region. Accordingly, both the first transfer mode transmission circuit and the second transfer mode transmission circuit can be realized with a small transistor area, and data transmission in the first and second transfer modes can be performed on a small scale. This can be realized by a circuit having a configuration.

  In the present invention, the first P-type transistor that constitutes the first transmission driver is provided between a first output node that is an output node of the first transmission driver and a first power supply. In addition, a first P-side transmission control signal is input to the gate, and the first N-type transistor constituting the first transmission driver is provided between the first output node and a second power supply. At the same time, a first N-side transmission control signal is input to the gate thereof, and the second P-type transistor constituting the second transmission driver is a second output that is an output node of the second transmission driver. The second N-type transistor that is provided between the node and the first power supply and receives a second P-side transmission control signal at its gate and constitutes the second transmission driver, Output node and second The second N-side transmission control signal is input to the gate of the third P-type transistor, and the third P-type transistor constituting the third transmission driver is connected to the output of the third transmission driver. The third N-type that is provided between the third output node, which is a node, and the first power supply, and a third P-side transmission control signal is input to the gate thereof and constitutes the third transmission driver The transistor is provided between the third output node and the second power source, and a third N-side transmission control signal is input to a gate thereof, and the fourth P constituting the fourth transmission driver. The type transistor is provided between a fourth output node, which is an output node of the fourth transmission driver, and a first power supply, and a fourth P-side transmission control signal is input to a gate thereof. Send driver The fourth N-type transistor to be formed may also be a fourth N-side transmission control signal is input to the gate along with provided between said fourth output node and the second power supply.

  In this way, a transmission circuit for the first transfer mode and a transmission circuit for the second transfer mode can be realized with a circuit having a simple configuration.

  In the present invention, the first transmission control circuit for the first transfer mode that generates and outputs the first P-side and N-side transmission control signals and the second P-side and N-side transmission control signals; A second transmission control circuit for a second transfer mode that generates and outputs the third P-side and N-side transmission control signals and the fourth P-side and N-side transmission control signals. .

  In this way, it is possible to adjust the rise time, fall time, etc. of the output signals of the first and second transmission circuits only by adjusting the rise time, fall time, etc. of the transmission control signal. .

  Further, in the present invention, the first transmission control circuit is based on the third P-side and N-side transmission control signals and the fourth P-side and N-side transmission control signals output from the second transmission control circuit. Alternatively, the first P-side and N-side transmission control signals and the second P-side and N-side transmission control signals having a long rise time or fall time may be generated and output.

  In this way, it becomes possible to lengthen the rise time and fall time of the transmission circuit for the first transfer mode with a simple circuit and control, and compliance with the standards and the like becomes easy.

  In the present invention, the first P-type transistor region and the first N-type transistor region are formed adjacent to each other, and the second P-type transistor region and the second N-type transistor region are adjacent to each other. It may be formed.

  In this way, the circuit area occupied by the transmission circuit for the first transfer mode and the transmission circuit for the second transfer mode can be further reduced.

  In the present invention, a first damping resistor provided between the first node to which the output nodes of the first and third transmission drivers are connected, and the first signal line, and the second, A second damping resistor provided between a second node to which an output node of a fourth transmission driver is connected and the second signal line, wherein the first damping resistor is the first damping resistor. It may be formed in a first resistance region adjacent to the N-type transistor region, and the second damping resistor may be formed in a second resistance region adjacent to the second N-type transistor region.

  In this way, the first and second damping resistors can be built in the integrated circuit device, and the increase in circuit scale due to the built-in first and second damping resistors can be minimized.

  In the present invention, the first and second damping resistors may be formed of an N-type diffusion layer.

  In this way, the increase in circuit scale can be further suppressed.

  In the present invention, the first termination resistor circuit provided between the first node to which the output nodes of the first and third transmission drivers are connected and the second power source, the second and second An N-type transistor comprising the second termination resistor circuit provided between the second node to which the output node of the four transmission drivers is connected and the second power supply, and constituting the first termination resistor circuit However, an N-type transistor that is formed in the first N-type transistor region and that constitutes the second termination resistor circuit may be formed in the second N-type transistor region.

  In this way, an increase in circuit scale due to the built-in first and second termination resistor circuits can be minimized.

  The present invention may also include a termination resistance control circuit that variably controls the termination resistance values of the first and second termination resistance circuits.

  This makes it possible to adjust the amplitude (output high level voltage) of the output signal by controlling the termination resistance value.

  In the present invention, the third transfer mode for transmitting data in the third transfer mode, which is faster than the second transfer mode, via the first and second signal lines constituting the differential pair. A third transmission circuit including a constant current circuit provided between a first power source and a given node; and between the node and the first signal line. A first switch element provided and a second switch element provided between the node and the second signal line may be included.

  In the present invention, the transmission circuit for the first transfer mode can be realized without substantially increasing the capacity added to the output node of the first transmission circuit. Accordingly, it is possible to effectively prevent adverse effects on the high-speed data transfer in the third transfer mode by the current-driven type third transmission circuit.

  In the present invention, the third transmission circuit includes a current control circuit that variably controls the value of the current flowing from the constant current circuit, and the current from the constant current circuit variably controlled by the current control circuit. Thus, the first or second signal line may be driven via the first or second switch element.

  According to the present invention, the value of the current flowing from the constant current circuit (constant current) does not become a fixed value, but is variably controlled by the current control circuit. For example, when the first setting is made by the current control circuit, the first or second signal line is driven (current driven) by the current having the first current value from the constant current circuit, and the second setting is made. Then, the first or second signal line is driven by the current of the second current value from the constant current circuit. In this way, the amplitude of the output signal (output high level voltage or the like) can be adjusted, and it becomes possible to maintain a good signal waveform and perform intelligent control that enables low power consumption.

  In the present invention, the first buffer circuit that outputs the first transmission control signal to the gate of the first transistor that constitutes the first switch element, and the second buffer that constitutes the second switch element. And a second buffer circuit for outputting a second transmission control signal to the gate of the transistor, and one of the first and second transmission control signals is set to be active. Sometimes, the other transmission control signal is set to inactive, and each of the first and second buffer circuits has a first inverter and an input node connected to an output node of the first inverter. 2 inverters and a capacitance adjusting circuit connected to the output node of the first inverter.

  This makes it possible to adjust the slew rate of the output signal.

  In the present invention, the differential signal transmitted through the first and second signal lines constituting the differential pair is a USB (Universal Serial Bus) standard signal, and the first, second, The third transfer modes may be a USB low speed mode, a full speed mode, and a high speed mode, respectively.

  The present invention also relates to an electronic apparatus including the integrated circuit device described above and a processing unit that controls the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. 1. Circuit Configuration of Integrated Circuit Device FIG. 1 shows a circuit configuration example of a data transfer control device realized by the integrated circuit device of this embodiment. Note that the device realized by the integrated circuit device of the present embodiment is not limited to the configuration shown in FIG. For example, a data transfer control device having a configuration different from that shown in FIG. 1 may be realized. Alternatively, an application layer device or a CPU (processor in a broad sense) may be added to the configuration shown in FIG.

  The data transfer control device of FIG. 1 includes a transceiver 200, a transfer controller 210, a buffer controller 220, a data buffer 230, and an interface circuit 240. Note that some of these circuit blocks may be omitted, the connection form between these circuit blocks may be changed, or circuit blocks different from these may be added. For example, the buffer controller 220, the data buffer 230, and the interface circuit 240 may be omitted.

  The transceiver 200 (physical layer circuit) is a circuit for transmitting and receiving data using DP and DM signal lines (first and second signal lines in a broad sense) constituting a differential pair (differential signal line). It is. The transceiver 200 includes a transmission circuit 50 for LS mode (first transfer mode in a broad sense) and a transmission circuit 52 for FS mode (second transfer mode in a broad sense). Further, a transmission circuit 54 for the HS mode (third transfer mode in a broad sense) can be included. The transceiver 200 includes a receiving circuit (differential receiver, single-ended receiver), a resistor circuit (pull-up resistor circuit, pull-down resistor circuit), a detection circuit (disconnection detection circuit, squelch circuit), a clock generation circuit (PLL), A sampling clock generation circuit (HSDLL), a reference voltage generation circuit, a parallel / serial conversion circuit, or a serial / parallel conversion circuit (elasticity buffer) can be included.

  The transfer controller 210 is a controller for controlling data transfer via the USB, and is for realizing a so-called SIE (Serial Interface Engine) function and the like. For example, the transfer controller 210 performs packet handle processing, suspend / resume control, or transaction management. The transfer controller 210 can include a link controller and a transaction controller (not shown).

  The buffer controller 220 secures a storage area (endpoint area, pipe area, etc.) in the data buffer 230 and controls access to the storage area of the data buffer 230. More specifically, the buffer controller 220 controls access from the application layer device side via the interface circuit 240, access from the CPU side via the interface circuit 240, and access from the USB (transfer controller 210) side. Access arbitration, access address generation and management.

  The data buffer 230 (packet buffer) is a buffer (FIFO) for temporarily storing (buffering) data (transmission data or reception data) transferred via the USB. The data buffer 230 can be constituted by a memory such as a RAM.

  The interface circuit 240 is a circuit for realizing an interface via a DMA (Direct Memory Access) bus to which an application layer device is connected and a CPU bus to which a CPU is connected. The interface circuit 240 can include a DMA handler circuit for DMA transfer.

2. Transmission Circuit FIG. 2 shows a configuration example of a transmission circuit and a transmission control circuit included in the integrated circuit device of this embodiment. In FIG. 2, a first transmission circuit 50 for LS mode (first transfer mode) includes DP and DM signal lines (first and second signals) constituting a differential pair (differential data signal line). This is a circuit for transmitting data in the LS (low speed) mode via a line. The transmission circuit 50 includes a first transmission driver 71 that drives (voltage drives) a DP signal line (first signal line), and a second transmission that drives a DM signal line (second signal line). A driver 72 is included.

  The second transmission circuit 52 for the FS mode (second transfer mode) is a circuit that transmits data in the FS (full speed) mode, which is faster than the LS mode, via the DP and DM signal lines. The transmission circuit 52 includes a third transmission driver 73 that drives the DP signal line and a fourth transmission driver 74 that drives the DM signal line.

  The third transmission circuit 54 for the HS mode (second transfer mode in a broad sense) is a circuit that transmits data in the HS (high speed) mode, which is faster than the FS mode, via the DP and DM signal lines. is there. The transmission circuit 54 includes a constant current circuit provided between a power supply AVDD (first power supply in a broad sense) and a given node, and a first current provided between the node and the DP signal line. And a second switch element provided between the node and the DM signal line.

  The first P-type transistor PT1 that constitutes the LS DP-side transmission driver 71 is provided between the first output node QN1 that is the output node of the transmission driver 71 and the power supply AVDD, and the gate has the first P-type transistor PT1. A P-side transmission control signal OP1 is input. The first N-type transistor NT1 constituting the transmission driver 71 is provided between the output node QN1 and the power source AVSS (second power source in a broad sense) and has a first N-side transmission control signal ON1 at its gate. Is entered.

  The second P-type transistor PT2 constituting the DM-side transmission driver 72 for LS is provided between the second output node QN2 that is the output node of the transmission driver 72 and the power supply AVDD, and the gate is connected to the second P-type transistor PT2. The P-side transmission control signal OP2 is input. The second N-type transistor NT2 constituting the transmission driver 72 is provided between the output node QN2 and the power source AVSS, and the second N-side transmission control signal ON2 is input to the gate thereof.

  The third P-type transistor PT3 constituting the DP-side transmission driver 73 for FS is provided between the third output node QN3, which is the output node of the transmission driver 73, and the power supply AVDD, and the gate thereof has a third P-type transistor PT3. A P-side transmission control signal OP3 is input. The third N-type transistor NT3 constituting the transmission driver 73 is provided between the output node QN3 and the power source AVSS, and the third N-side transmission control signal ON3 is input to the gate thereof.

  The fourth P-type transistor PT4 constituting the DM-side transmission driver 74 for FS is provided between the fourth output node QN4, which is the output node of the transmission driver 74, and the power supply AVDD, and the gate has the fourth P-type transistor PT4. A P-side transmission control signal OP4 is input. The fourth N-type transistor NT4 constituting the transmission driver 74 is provided between the output node QN4 and the power source AVSS, and the fourth N-side transmission control signal ON4 is input to the gate thereof.

  The transmission drivers 71, 72, 73, and 74 are not limited to the configuration shown in FIG. 2, and the connection relationship may be changed or another transistor may be added.

  The LS first transmission control circuit 60 receives the LS data signals LSDPOUT, LSDMOUT and the enable signal LSOUTENB, and receives the first P side, N side transmission control signals OP1, ON1 and the second P side, N side. Transmission control signals OP2 and ON2 are generated and output. The transmission control circuit 60 includes a first signal generation circuit 81 that generates signals OP1 and ON1, and a second signal generation circuit 82 that generates signals OP2 and ON2.

  The FS second transmission control circuit 62 receives the FS data signals FSDPOUT and FSDMOUT and the enable signal FSOUTENB, and receives the third P side, N side transmission control signals OP3 and ON3 and the fourth P side and N side. Transmission control signals OP4 and ON4 are generated and output. The transmission control circuit 62 includes a third signal generation circuit 83 that generates signals OP3 and ON3 and a fourth signal generation circuit 84 that generates signals OP4 and ON4.

  The HS transmission control circuit 64 receives the HS data signals HSDPUOT and HSDMOUT and the enable signal HSOUTENB, and generates and outputs first to third transmission control signals GC1, GC2, and GC3.

  The LS transmission control circuit 60 transmits the transmission control signals OP1, ON1, OP2, ON2 having a longer rise time or fall time than the transmission control signals OP3, ON3, OP4, ON4 output from the FS transmission control circuit 62. Is output. In other words, a transmission control signal with a low slew rate is output. Here, the rise time can be defined as the time from the time when the signal level becomes 10% of the wave height to the time when the signal level becomes 90% of the wave height. The fall time can be defined as the time from the time when the signal level becomes 90% of the wave height to the time when the signal level becomes 10% of the wave height.

  As shown in FIG. 2, the integrated circuit device according to the present embodiment includes a first node TN1 connected to the output nodes QN1 and QN3 of the transmission drivers 71 and 73, and a first signal line provided between the DP signal lines. The damping resistor RSP (fixed resistor) can be included. In addition, a second damping resistor RSM (fixed resistor) provided between the second node TN2 to which the output nodes QN2 and QN4 of the transmission drivers 72 and 74 are connected and the DM signal line can be included.

  Further, as shown in FIG. 3, the integrated circuit device of this embodiment includes a first termination resistor circuit 30 provided between the node TN1 and the power source AVSS, and a second terminal resistor provided between the node TN2 and the power source AVSS. A termination resistor circuit 32 may be included. These termination resistance circuits 30 and 32 are circuits for terminating the DP and DM signal lines during HS data transfer, and the termination resistance values are variably controlled, for example.

  As shown in FIG. 3, the integrated circuit device may include a termination resistance control circuit 40. The termination resistance control circuit 40 is a circuit for variably controlling (setting) the termination resistance values of the termination resistance circuits 30 and 32, and includes a termination resistance setting information register 42. Specifically, the termination resistance control circuit 40 outputs resistance control signals CP (CP1 to CP3) and CM (CM1 to CM3) to the termination resistance circuits 30 and 32. The voltage levels of the resistance control signals CP and CM are set based on setting information (setting value) in the termination resistance setting information register 42. The setting information can be written to the termination resistance setting information register 42 by, for example, firmware (processing unit, CPU).

  In FIG. 3, in the LS and FS modes, the resistors RSP and RSM are used as damping resistors for LS and FS, for example, by turning off the transistors constituting the resistors of the termination resistor circuits 30 and 32. On the other hand, in the HS mode, by setting the transmission circuits 50 and 52 for LS and FS to the disabled state, the resistance composed of the resistor RSP and the termination resistance circuit 30 and the resistance composed of the resistance RSM and the termination resistance circuit 32 are changed. , It can be used as a termination resistor for HS. Accordingly, the resistors RSP and RSM can be shared in the LS and FS modes and in the HS mode, so that the circuit can be reduced in size.

3. Layout of Integrated Circuit Device FIG. 4 shows a layout example of the integrated circuit device of this embodiment. This integrated circuit device includes a first macro cell MC1 and a second macro cell MC2. Note that these macrocells MC1 and MC2 (megacells and macroblocks) are units of a medium-scale or large-scale circuit having a logic function. Further, the integrated circuit device of this embodiment may include three or more macro cells.

  In FIG. 4, a macro cell MC1 is a macro cell including a physical layer circuit which is, for example, the transceiver 200 of FIG. The macro cell MC1 may include a circuit other than the physical layer circuit (such as a logic layer circuit).

  The macro cell MC1 is, for example, a hard macro whose wiring and circuit cell arrangement are fixed. More specifically, for example, wiring and circuit cell placement are performed by manual layout. A part of the wiring and arrangement may be automated.

  On the other hand, the macro cell MC2 is a macro cell including circuits in layers higher than the physical layer (logical layer, link layer, transaction layer, application layer, etc.). Taking USB as an example, the macro cell MC2 can include a logic layer circuit (another part of the logic layer circuit included in the MC1) such as an SIE (Serial Interface Engine) or a user logic (device-specific circuit). In FIG. 4, the pads (DP, DM, etc.) may be provided in the I / O area or outside the I / O area.

  The macro cell MC2 is, for example, a soft macro whose wiring and circuit cell arrangement are automatically arranged and wired. More specifically, for example, wiring between basic cells is automatically performed by a gate array automatic placement and routing tool. A part of the arrangement and wiring may be fixed.

  FIG. 5 shows a layout example of circuits such as the transmission circuits 50 and 52 shown in FIGS. 2 and 3 included in the macro cell MC1. In FIG. 5, a DP-side circuit is arranged in the first area AR1, and a DM-side circuit is arranged in the second area AR2. These regions AR1 and AR2 are, for example, line-symmetrically arranged with a line along the direction D2 in FIG. 5 (a direction from the outside to the inside of the integrated circuit device) as a symmetry axis.

  The DP-side region AR1 includes a first P-type transistor region ARP1 and a first N-type transistor region ARN1. Also, the first resistance region ARR1 is included. The regions ARP1 and ARN1 are formed adjacent to each other, and ARN1 and ARR1 are also formed adjacent to each other.

  On the other hand, the DM-side region AR2 includes a second P-type transistor region ARP2 and a second N-type transistor region ARN2. Also, the second resistance region ARR2 is included. The regions ARP2 and ARN2 are formed adjacent to each other, and ARN2 and ARR2 are also formed adjacent to each other.

  In this embodiment, as shown in FIG. 5, the P-type transistor PT1 constituting the LS DP-side transmission driver 71 and the P-type transistor PT3 constituting the FS DP-side transmission driver 73 shown in FIGS. , Formed in the P-type transistor region ARP1. An N-type transistor NT1 constituting the LS DP-side transmission driver 71 and an N-type transistor NT3 constituting the FS DP-side transmission driver 73 are formed in the N-type transistor region ARN1.

  On the other hand, a P-type transistor PT2 constituting the DM-side transmission driver 72 for LS and a P-type transistor PT4 constituting the DM-side transmission driver 74 for FS are formed in the P-type transistor region ARP2. An N-type transistor NT2 constituting the DM-side transmission driver 72 for LS and an N-type transistor NT4 constituting the DM-side transmission driver 74 for FS are formed in the N-type transistor region ARN2.

  As described above, in this embodiment, the P-type transistors constituting the LS transmission driver and the P-type transistors constituting the FS transmission driver are formed together in the same P-type transistor region. Further, the N-type transistor constituting the LS transmission driver and the N-type transistor constituting the FS transmission driver are formed together in the same N-type transistor region.

  In FIG. 5, the damping resistor RSP of FIGS. 2 and 3 is formed in the resistance region ARR1 adjacent to the N-type transistor region ARN1. A damping resistor RSM is formed in the resistance region ARR2 adjacent to the N-type transistor region ARN2. These damping resistors RSP and RSM can be formed by, for example, an N-type diffusion layer (N + diffusion layer, active region).

  In FIG. 5, the N-type transistor NTRTP constituting the DP-side termination resistor circuit 30 of FIG. 3 is formed in the DP-side N-type transistor region ARN1. An N-type transistor NTRTM constituting the DM-side termination resistor circuit 32 is formed in the DM-side N-type transistor region ARN2.

  FIG. 6 shows a detailed layout example of the area AR2. The layout of the area AR1 is the same as that in FIG. As shown in FIG. 6, in the P-type transistor region ARP2, the P-type transistor PT2 of the LS transmission driver 72 and the P-type transistor PT4 of the FS transmission driver 74 are arranged side by side in the D2 direction. In the N-type transistor area ARN2, the N-type transistor NT2 of the LS transmission driver 72 and the N-type transistor NT4 of the FS transmission driver 74 are arranged side by side in the D2 direction. Further, these N-type transistors NT2 and NT4 and the N-type transistor NTRTM constituting the termination resistor circuit 32 of FIG. 3 are arranged side by side in the D2 direction. In addition, a damping resistor RSM formed of an N-type diffusion region (N + diffusion region) is formed in the resistance region ARR2.

  The signal line 86 from the DM pad is connected to one end of the damping resistor RSM in the resistance region ARR2. The signal line 88 connected to the other end of the damping resistor RSM is connected to the drains of the transistors PT2, PT4, NT2, and NT4.

  As shown in FIGS. 2 and 3, in USB 2.0, a very high-speed HS transmission circuit 54 is provided, and this transmission circuit 54 current-drives the DP and DM signal lines. Therefore, when a circuit having a configuration in which a large capacity is added to the output node of the transmission circuit as in the above-described conventional example 1 as the transmission circuit for LS, charging / discharging of this large capacity is required in the HS mode. Therefore, it becomes difficult to realize high-speed data transfer of HS. Further, in the above-described conventional examples 1 and 2, problems such as an increase in the size of an LS transmission circuit and a complicated control are caused.

  In this regard, in the transmission circuit 50 for LS of the present embodiment shown in FIGS. 2 and 3, a very large capacity is not added to the nodes TN1 and TN2. Accordingly, it is possible to prevent the HS transfer by the HS transmission circuit 54 from being adversely affected. Further, since the LS transmission circuit 50 can be realized by the same configuration as the FS transmission circuit 52, the circuit scale can be significantly reduced as compared with the conventional examples 1 and 2. If the circuit scale is small as described above, the LS transmission circuit 50 can be arranged in a vacant space in the macro cell MC1, so that the layout area of the integrated circuit device can be reduced. In particular, in the present embodiment, as shown in FIG. 5, the transistors constituting the LS transmission circuit 50 and the transistors constituting the FS transmission circuit 52 are collectively formed in the regions AR <b> 1 and AR <b> 2. Therefore, an increase in circuit area due to the provision of the LS transmission circuit 50 can be minimized.

  For example, in a data transfer control device of a USB device that supports only HS and FS and does not support LS, the transmission circuit 50 for LS is not necessary. However, when the macro cell MC1 has a USB host function, an LS-compatible USB device such as a mouse may be connected to the DP and DM signal lines. Therefore, it is necessary to newly incorporate the LS transmission circuit 50 in the macro cell MC1 capable of realizing the USB host function.

  In this case, if a large capacity is added to the output node of the LS transmission circuit 50 newly built for realizing the USB host function, there arises a problem that HS data transfer cannot be realized. In this respect, in this embodiment, since such a large capacity is not added, the occurrence of the above problem can be prevented.

  Further, when the circuit scale of the newly built LS transmission circuit 50 is large, there is a problem that the integrated circuit device becomes large. In this respect, in this embodiment, as is apparent from FIGS. 5 and 6, it is possible to add a small transistor such as PT1 to the region ARP1, NT1 to the region ARN1, PT2 to the region ARP2, and NT2 to the region ARN2. The transmission circuit 50 can be realized. Therefore, the transmission circuit 50 for LS can be realized with almost no increase in the scale of the integrated circuit device, and the realization of the USB host function by the macro cell MC1 can be facilitated.

  5 and 6, the damping resistors RSP and RSM are built in the integrated circuit device. However, modifications may be made in a configuration in which the damping resistors RSP and RSM are not built. In this case, the damping resistors RSP and RSM may be realized with external parts.

  3, 5, and 6, the termination resistor circuits 30 and 32 and the termination resistor control circuit 40 are provided in the integrated circuit device. However, a configuration without the termination resistor circuits 30 and 32 may be employed. In this case, in the HS mode, the transmission circuit 52 for FS may drive the DP and DM signal lines with “0” and cause the damping resistors RSP and RSM to function as termination resistors.

  5 and 6, the P-type transistor region ARP1 and the N-type transistor region ARN1 are adjacent to each other, and the P-type transistor region ARP2 and the N-type transistor region ARN2 are adjacent to each other. is there. For example, a modification may be made in which the resistance region ARR1 is formed between the P-type transistor region ARP1 and the N-type transistor region ARN1, or the resistance region ARR2 is formed between the P-type transistor region ARP2 and the N-type transistor region ARN2.

4). Transmission Control Circuit FIG. 7A shows a detailed configuration example of the signal generation circuits 81, 82, 83, 84 included in the transmission control circuits 60, 62.

  Signals IN (LSDPOUT, LSDMOUT, FSDPOUT, FSDMOUT) are input to the gates of the transistors TA1 and TA2. The node N1 at the drain of the transistor TA1 is connected to the input of the inverter INV1 composed of the transistors TA3 and TA4, and the output node N3 of the INV1 is connected to the input of the inverter INV2 composed of the transistors TA5 and TA6. The node N2 at the drain of the transistor TA2 is connected to the input of the inverter INV3 composed of the transistors TA7 and TA8, and the output node N4 of the INV3 is connected to the input of the inverter INV4 composed of the transistors TA9 and TA10.

  The enable signals OUTENB (LSOUTENB and FSOUTENB) are input to the gates of the transistors TA11 and TA12, and the node N1 is connected to the drains. Further, the inverted signal XOUTENB of OUTENB is input to the gates of the transistors TA13 and TA14, and the node N2 is connected to the drain. Note that the transistor TA15 functions as a pull-down resistor, and the transistors TA16, TA17, and TA18 function as pull-up resistors.

  FIG. 7B shows a truth table of the signal generation circuit in FIG. When the signal OUTENB is at the H (High) level, the transistors TA12 and TA13 are turned on, and the nodes N1 and N2 are connected through the transistors TA12 and TA13. In this state, when the signal IN is at the L (Low) level, the transistor TA1 is turned on, and the nodes N1 and N2 are both at the H level. Therefore, the transmission control signals OP and ON, which are the outputs of the inverters INV2 and INV4, are both H level. When the signals OP and ON become H level, as is apparent from FIG. 2, the output of the transmission driver to which the signals OP and ON are inputted becomes L level.

  On the other hand, when the signal IN is at the H level, the transistor TA2 is turned on, and the nodes N1 and N2 are both at the L level. Accordingly, the signals OP and ON are both at the L level. When the signals OP and ON become L level, as is apparent from FIG. 2, the output of the transmission driver to which the signals OP and ON are input becomes H level.

  When the signal OUTENB is at L level, the transistors TA11 and TA14 are turned on, the node N1 becomes H level, and the node N2 becomes L level. Therefore, the signal OP becomes H level and the signal ON becomes L level. Then, as is apparent from FIG. 2, the output of the transmission driver to which the signals OP and ON are input is in a high impedance state.

  8A and 8B show examples of waveforms of the transmission control signals OP1, ON1, OP2, and ON2 input to the LS transmission drivers 71 and 72, and FIG. 8C shows an LS transmission driver. An example of waveforms of output signals DP and DM of 71 and 72 is shown.

  As shown in FIGS. 8A and 8B, the signals OP1 and OP2 have waveforms having a long fall time and a short rise time. This is realized by reducing the transistor size (W / L, current supply capability) of the N-type transistor TA6 in FIG. 7A and increasing the transistor size of the P-type transistor TA5. On the other hand, the signals ON1 and ON2 have waveforms having a long rise time and a short fall time. This is achieved by reducing the transistor size of the P-type transistor TA9 in FIG. 7A and increasing the transistor size of the N-type transistor TA10.

  If the fall time of the signal OP1 is lengthened as indicated by D1 in FIG. 8A, the rise time of the signal DP can be lengthened as indicated by E1 in FIG. 8C. Further, if the rise time of the signal ON1 is lengthened as D2 in FIG. 8A, the fall time of the signal DP can be lengthened as E2 in FIG. Therefore, both the rise time and fall time of the signal DP can be lengthened.

  If the rise time of the signal ON2 is lengthened as indicated by D3 in FIG. 8B, the fall time of the signal DM can be lengthened as indicated by E3 in FIG. Further, if the falling time of the signal OP2 is lengthened as indicated by D4 in FIG. 8B, the rising time of the signal DM can be lengthened as indicated by E4 in FIG. 8C. Therefore, both the rise time and fall time of the signal DM can be lengthened.

  As described above, in this embodiment, the rise time and fall time of the signals DP and DM can be controlled and lengthened only by changing the transistor size of the transistors TA5, TA6, TA9, TA10, etc. in FIG. It becomes possible. Therefore, it becomes possible to easily keep the rise time and fall time of DP and DM in the range of 75 to 300 ns with respect to the load capacity in the range of 50 to 350 pf, and the USB standard in the LS mode can be observed. Further, even if the transistor sizes of the transistors TA5, TA6, TA9, and TA10 are changed, the load capacity of the output nodes QN1 and QN2 of the transmission drivers 71 and 72 does not change, which adversely affects HS mode data transfer by the transmission circuit 54. Can be prevented.

  In this embodiment, as shown in FIGS. 8A and 8B, the transmission control circuit 60 for LS has a rise time or rise time higher than the signals OP3, ON3, OP4, and ON4 output from the transmission control circuit 62 for FS. Signals OP1, ON1, OP2, and ON2 having a long fall time are output. This can be realized by reducing the transistor sizes of the transistors TA6, TA9, etc. in FIG. 7A in the LS transmission control circuit 60 as compared with the FS transmission control circuit 62.

5. HS Transmission Circuit FIG. 9 shows a configuration example of the HS transmission circuit 54 (current driver) of FIG. The transmission circuit includes a constant current circuit 10 and first to third switch elements SW1, SW2, and SW3.

  The constant current circuit 10 (current source, current circuit) is provided between the power supply AVDD and the node ND. The switch element SW1 is provided between the node ND and the plus side signal line DP constituting the differential signal line. The switch element SW2 is provided between the node ND and the minus side signal line DM constituting the differential signal line. The switch element SW3 is provided between the node ND and the power supply AVSS. These switch elements SW1, SW2, SW3 can be constituted by transistors (CMOS transistors, N-type transistors), and on / off control is performed by transmission control signals GC1, GC2, GC3.

  9 drives (current drive) a DP or DM signal line (first or second signal line in a broad sense) via the switch element SW1 or SW2 by the current from the constant current circuit 10. . Specifically, the switch elements SW1, SW2, and SW3 are turned on / off based on the transmission control signals GC1, GC2, and GC3 from the transmission control circuit 64 of FIG. 2, and the DP and DM signal lines are driven. .

  FIG. 10A shows signal waveform examples of the transmission control signals GC1, GC2, and GC3. The signals GC1 and GC2 are non-overlapping signals in which one of them is active (for example, high level) and the other is inactive (for example, low level). The signal GC3 is a signal that becomes inactive during the transmission period and becomes active during a period other than the transmission period.

  When the signal GC1 becomes active, the switch element SW1 is turned on, and a current (constant current) from the constant current circuit 10 flows to the signal line DP side through SW1. On the other hand, when the signal GC2 becomes active, the switch element SW2 is turned on, and the current from the constant current circuit 10 flows to the signal line DM via SW2. Here, termination resistors are connected to the signal lines DP and DM. Accordingly, when the signal GC1 is activated and the signal GC2 is deactivated, a J state is generated in which the DP voltage is 400 mV and the DM voltage is 0V. When the signal GC1 is deactivated and the signal GC2 is activated, a K state is generated in which the DP voltage is 0V and the DM voltage is 400 mV. Thus, by controlling the signals GC1 and GC2 to change the USB bus state to the J state or the K state, data transfer (packet transfer) via the USB becomes possible.

  Further, as shown in FIG. 10A, in a period other than the transmission (HS transmission) period, the signal GC3 becomes active, so that the current from the constant current circuit 10 flows to the power supply AVSS side via the switch element SW3. . That is, the current from the constant current circuit 10 is discarded. As described above, even during a period other than the transmission period, the potential of the node ND can be stabilized by continuously flowing the current from the constant current circuit 10 to the AVSS (GND) side via the SW3. Then, immediately after the start of transmission, a stable current from the constant current circuit 10 can be passed through the signal lines DP and DM via the switch elements SW1 and SW2, and the response of the transmission circuit can be improved.

  The current value IHS flowing from the constant current circuit 10 is as large as Ihs = 17.78 mA. Therefore, even in a period other than the transmission period, if the current from the constant current circuit 10 flows into the AVSS side, the power consumption of the transmission circuit increases.

  In this regard, in FIG. 10B, the enable signal (the current source is set to the enable state) of the constant current circuit 10 at the timing indicated by C2 before the transmission start timing indicated by C1 when the packet is transmitted on the USB. Signal) is active. In other words, the enable signal is activated at the timing (C2) before the transmission waiting period TS before the packet transmission start timing (C1). This makes it possible to perform proper packet transmission using the current of the constant current circuit 10 during the packet transmission period, and to prevent a situation where a wasteful current flows into the AVSS during a period other than the transmission period. Thereby, it is possible to save power in the data transfer control device and the electronic device. In addition, by setting the length of the transmission standby period TS to a length sufficient for stabilizing the current of the constant current circuit 10 and stabilizing the potential of the node ND (for example, 100 ns or more), the transmission standby period TS is fixed immediately at the start of transmission. A stable current from the current circuit 10 can be supplied to DP and DM via SW1 and SW2, and the high response performance of the transmission circuit can be maintained.

  In this case, it is desirable that the transaction layer (transaction controller) controls (generates and outputs) the enable signal of the constant current circuit 10. For example, as a comparative example, a method in which the enable signal is controlled by a circuit in a packet layer (or a layer below it) such as a packet generation circuit can be considered. However, the packet layer circuit is completely unaware of the transactions that are taking place on the bus. Therefore, the method of this comparative example cannot realize intelligent control such as changing the signal change timing of the enable signal according to the type of transaction being executed.

  On the other hand, if the transaction layer circuit (transaction controller) that recognizes the transaction (transaction phase switching timing) controls the enable signal, control according to the transaction being performed on the bus becomes possible. Intelligent control such as changing the signal change timing of the enable signal according to the type of transaction being executed can be realized. Specifically, when the transaction type is an IN transaction, the enable signal can be controlled to be active at a timing between the IN token packet reception completion timing and the data packet transmission start timing. Further, when the transaction type is an OUT transaction, it is possible to control to activate the enable signal at a timing between the reception completion timing of the data packet and the transmission start timing of the handshake packet.

6). Control of Constant Current Value FIG. 11 shows a first modification of the HS transmission circuit of FIG. In FIG. 11, a current control circuit 20 is provided in addition to the configuration of FIG. The current control circuit 20 is a circuit for variably controlling (setting) the value of the current flowing from the constant current circuit 10 (current flowing between AVDD and ND), and includes a current setting information register 22. Specifically, the current control circuit 20 outputs current control signals IC <b> 1 to ICJ to the constant current circuit 10. The voltage levels of the current control signals IC1 to ICJ are set based on setting information (setting values) in the current setting information register 22. The setting information is written into the current setting information register 22 by, for example, firmware (processing unit, CPU). A constant current having a current value corresponding to the voltage levels of the current control signals IC1 to ICJ flows from the constant current circuit 10 to the node ND. For example, when the voltage levels of the current control signals IC1 to ICJ are the first setting, a constant current of the first current value flows, and when the voltage level of the current control signals IC1 to ICJ is the second setting, the constant current of the second current value is Flow: When the setting is the Kth, a constant current of the Kth current value flows.

  In USB, the output high level voltage VHSOH is standardized. Specifically, the minimum value (vmin) of VHSOH is 360 mV, and the maximum value (vmax) is 440 mV. In USB 2.0, the termination resistance value rterm is also standardized. Specifically, the minimum value (rtl, rrl) of rterm is 40.5Ω, and the maximum value (rth, rrh) is 49.5Ω.

  For example, FIG. 12 shows an example of a USB eye pattern (differential signal characteristic). The band-like areas indicated by A1 and A2 in FIG. 12 and the hexagonal area indicated by A3 are prohibited areas defined by USB, and a transmission circuit and a transmission path are provided so that DP and DM signal waveforms do not enter the prohibited areas. Need to design. As is apparent from FIG. 12, when the voltage level of the DP and DM signal lines becomes higher than 440 mV or lower than 360 mV, the DP and DM signal waveforms enter the prohibited areas A1 and A2, and the USB standard cannot be satisfied. .

  In the conventional USB (USB 2.0) transmission circuit, the value of the current flowing from the constant current circuit is a fixed value and has not been variably controlled. That is, the constant current circuit supplies a current having a fixed value of ihs = 17.78 mA, assuming that the terminating resistance values on the transmission side and the reception side are 45Ω. In this way, as shown at A4 in FIG. 12, the voltage levels of DP and DM become 400 mV, and the signal waveforms of DP and DM do not enter the prohibited areas of A1, A2, and A3.

  However, the distance from the IC terminal of the data transfer control device having the transmission circuit to the USB receptacle of the circuit board may be long. In this case, even if VHSOH = 400 mV at the IC terminal, VHSOH at the receptacle terminal. = 400 mV may not be obtained. In addition, necessary and sufficient signal amplitude may not be obtained due to fluctuations in device characteristics or waveform deterioration (waveform attenuation) on the transmission path. Furthermore, when the data transfer control device on the reception side does not comply with the USB standard, there is a possibility that the data transfer may not be performed normally even if the signal waveform (VHSOH) on the transmission side complies with the USB standard. is there.

  Therefore, in FIG. 11, the current value Ihs of the current IHS flowing from the constant current circuit 10 can be set variably. That is, the current value ihs is set to various values based on the current control signals IC1 to ICJ from the current control circuit 20. For example, it is assumed that the termination resistance values on the transmission side and the reception side are both 45Ω. At this time, if the value of current flowing from the constant current circuit 10 is set to ihs = 16 mA, VHSOH = vmin = 360 mV, and if ihs = 19.56 mA, VHSOH = vmax = 440 mV.

  For example, when the distance from the IC terminal of the data transfer control device to the USB receptacle on the circuit board is long and the signal amplitude is greatly attenuated, it is desirable to increase the output high level voltage VHSOH. Therefore, in this case, the value ihs of the current flowing from the constant current circuit 10 is increased. By doing so, the DP and DM signal waveforms are as shown by A5 in FIG. 12, and even if the signal amplitude is attenuated, the VHSOH at the position of the USB receptacle terminal can be set to about 400 mV. Even when the data transfer control device on the receiving side does not comply with the USB standard and the prohibited area A3 in FIG. 12 is larger than the standard, data transfer without error can be realized.

  Further, for example, when the distance between the transmission side and the reception side is short like a USB memory, it is considered that the attenuation of the signal amplitude during transmission is small. Therefore, in this case, the power consumption is prioritized and the value ihs of the current flowing from the constant current circuit 10 is reduced. In this way, the DP and DM signal waveforms are as shown by A6 in FIG. 12, and VHSOH is smaller than 400 mV. However, when the USB transmission path is short like a USB memory, even if VHSOH is smaller than 400 mV, there is almost no possibility that the DP and DM signal waveforms will enter the prohibited area of A3 on the receiving side. If the current value ihs is reduced, the current consumption of the transmission circuit can be reduced, and power saving of the data transfer control device including the transmission circuit and the electronic device including the data transfer control device can be achieved.

  As described above, in FIG. 11, a constant current circuit that is normally designed to flow a fixed value current can flow a variable value current. For example, as a comparative example of making the output high level voltage VHSOH variable, a method of variably controlling only the value of the termination resistor connected to DP and DM is conceivable.

  However, according to this method, when the termination resistance value on the transmission side is changed, impedance matching with the termination resistance value on the reception side cannot be obtained, and the transmission waveform may be deteriorated.

  In this regard, in FIG. 11, since the current value of the constant current circuit 10 is variably controlled, it is not necessary to change the termination resistance value. Therefore, impedance matching with the receiving side can be easily performed, and a good transmission waveform can be maintained. In FIG. 11, the end user can adjust the current value ihs of the constant current circuit 10 by firmware or the like. Therefore, for example, when the transmission path is short, it is possible to perform intelligent control such as reducing the current value ihs and setting to the low power consumption mode, thereby realizing a transmission circuit that is not conventionally available.

  Note that the minimum value of the output high level voltage of the transmission circuit for HS is vmin (= 360 mV), the maximum value of the output high level voltage of the transmission circuit is vmax (= 440 mV), and the termination resistance value on the transmission side is rt. Assume that the terminating resistance value on the receiving side is rr and the value of the current flowing from the constant current circuit 10 is ihs. In this case, the range of current flowing from the constant current circuit 10 is, for example, a range satisfying {(rt + rr) / (rt × rr)} × vmin ≦ ihs ≦ {(rt + rr) / (rt × rr)} × vmax. Can be set.

  In this way, the minimum value of the current value ihs is ihsmin = {(rt + rr) / (rt × rr)} × vmin, and the maximum value is ihsmax = {(rt + rr) / (rt × rr)} × vmax. . Therefore, the output high level voltage when a current of ihs = ihsmin flows becomes VSVOH = vmin = 360 mV, and the output high level voltage when a current of ihs = ihsmax flows becomes VSVOH = vmax = 440 mV. Therefore, the current value ihs from the constant current circuit 10 can be variably controlled while complying with the USB standard. Further, it is assumed that the minimum value of the terminating resistance on the receiving side is rrl (= 40.5Ω) and the maximum value is rrh (49.5Ω). In this case, the range of the current flowing from the constant current circuit 10 is set to a range satisfying {(rt + rrl) / (rt × rrl)} × vmin ≦ ihs ≦ {(rt + rrh) / (rt × rrh)} × vmax. May be.

7). Variable Control of Termination Resistance Value FIG. 13 shows a configuration example of the termination resistance circuit 30 of FIG. The termination resistor circuits 32 and 34 have the same configuration as that shown in FIG.

  Termination resistor circuit 30 includes resistor circuits 36, 37 and 38. Each of these resistance circuits 36, 37, and 38 is composed of a plurality of transistors. Specifically, as shown in FIGS. 14A, 14B, and 14C, each of the resistance circuits 36, 37, and 38 includes, for example, five, twelve, and three N-type transistors connected in parallel. The These N-type transistors are transistors NTRTP and NTRTM formed in the N-type transistor regions ARN1 and ARN2 in FIGS. The node TN1 is connected to the drain of these N-type transistors, and the power source AVSS is connected to the source. Resistance control signals CP1, CP2, and CP3 from the termination resistance control circuit 40 are input to the gates of the N-type transistors constituting the resistance circuits 36, 37, and 38, respectively. When the resistance control signals CP1, CP2, and CP3 are activated, the N-type transistors that constitute the resistance circuits 36, 37, and 38 are turned on, and the on-resistance value is the resistance value (termination of the resistance circuits 36, 37, and 38). Resistance value).

  For example, when the resistance control signals CP1 to CP3 are all active, all of the 20 (= 5 + 12 + 3) transistors connected in parallel constituting the resistance circuits 36, 37, and 38 are turned on, and these transistors are turned on. The parallel resistance value formed by the resistance value is, for example, 2.4Ω. Since the RSP has a fixed resistance value rsp = 39Ω, the termination resistance value is 41.4Ω.

  Further, when the resistance control signals CP1 and CP3 are active and CP2 is inactive, eight (= 5 + 3) transistors connected in parallel constituting the resistance circuits 36 and 38 are turned on. The parallel resistance value formed by the on-resistance value of the transistor is, for example, 6.0Ω. Therefore, the termination resistance value is 39 + 6.0 = 45Ω.

  Further, when the resistance control signal CP1 is active and CP2 and CP3 are inactive, the five transistors connected in parallel constituting the resistance circuit 36 are turned on, and the on resistance values of these transistors are The formed parallel resistance value is, for example, 9.6Ω. Therefore, the termination resistance value is 39 + 9.6 = 48.6Ω.

  As described above, in FIGS. 3 and 13, the termination resistance values of DP and DM can be variably controlled. As a result, the output high level voltage can be adjusted as indicated by A4, A5, and A6 in FIG. Also, when impedance matching with the terminating resistance value on the receiving side is not taken, impedance matching can be achieved by changing the terminating resistance value on the transmitting side.

8). Capacity Adjustment Circuit FIG. 15 shows a second modification of the HS transmission circuit of FIG. In FIG. 15, buffer circuits 510-1, 510-2, and 510-3 are further provided. In FIG. 15, the switch elements SW1, SW2, and SW3 of FIG. 9 are constituted by transistors TE1, TE2, and TE3.

  The buffer circuits 510-1, 510-2, and 510-3 receive the transmission control signals GC1, GC2, and GC3 and output the transmission control signals GC1 ', GC2', and GC3 'to the gates of the transistors TE1, TE2, and TE3. The transmission control signals GC1 and GC2 are non-overlapping signals that become inactive when one of them is active.

  Buffer circuits 510-1, 510-2, and 510-3 include capacitance adjustment circuits 520-1, 520-2, and 520-3, respectively. If the capacitance is adjusted by providing such capacitance adjustment circuits 520-1, 520-2, and 520-3, the output waveform of the HS transmission circuit can be adjusted to an arbitrary waveform. That is, the eye pattern can be adjusted by adjusting the slew rate of the transmission circuit. For example, the rising slew rate of the DP and DM signals can be adjusted as indicated by A7 in FIG. 12, and the falling slew rate of the DP and DM signals can be adjusted as indicated by A8. . As a result, an optimum slew rate (potential gradient) according to the transmission path and the substrate can be selected. Therefore, accurate data transfer using differential signals can be realized even when the data transfer control device (electronic device) on the other side connected via USB is not strictly compliant with the USB standard.

  FIG. 16 shows a configuration example of the buffer circuit 510 (510-1, 510-2, 510-3) and the capacity adjustment circuit 520 (520-1, 520-2, 520-3). Buffer circuit 510 includes a first inverter 512 and a second inverter 514 whose input node is connected to the output node of inverter 512. A capacity adjustment circuit 520 is connected to the output node of the inverter 512.

  The capacitance adjustment circuit 520 includes transistors TE4, TE5, and TE6 (at least one capacitance adjustment switch element in a broad sense) that are on / off controlled by capacitance adjustment signals SS1, SS2, and SS3, and capacitance elements C1, C2, and C3 ( In a broad sense, it includes at least one capacitor element). One ends of the capacitive elements C1, C2, and C3 are connected to the other ends (sources) of the transistors TE4, TE5, and TE6 (capacitance adjustment switch elements), and the other ends of the C1, C2, and C3 are connected to AVSS (second power source). ).

  By setting the levels of the capacitance adjustment signals SS1, SS2, and SS3 to various values, the wiring capacitance of the output node of the inverter 512 (input node of the inverter 514) can be adjusted to an arbitrary value. Thereby, the slew rate of the output of the HS transmission circuit can be arbitrarily adjusted. As the capacitive elements C1, C2, and C3, a gate capacitance of a MOS transistor may be used, or a capacitance formed between the first and second polysilicon wirings may be used.

  According to the second modification of FIG. 15, not only the output high level voltage VHSOH but also the slew rate can be adjusted. Therefore, the DP and DM signal waveforms can be set to various waveforms according to the transmission path, and compliance with the USB standard relating to the eye pattern as shown in FIG. 12 can be facilitated.

9. Electronic Device FIG. 17 shows a configuration example of the electronic device of this embodiment. The electronic apparatus 300 includes a data transfer control device 310 that is an integrated circuit device described in the present embodiment, an application layer device 320 including an ASIC, a CPU 330, a ROM 340, a RAM 350, a display unit 360, An operation unit 370 is included. A part of these functional blocks may be omitted.

  Here, the application layer device 320 is, for example, a device that realizes an application engine of a mobile phone, a device that controls a drive of an information storage medium (hard disk, optical disk), a device that controls a printer, an MPEG encoder, an MPEG decoder, or the like Including the device. The processing unit 330 (CPU) controls the data transfer control device 310 and the entire electronic device. The ROM 340 stores control programs and various data. The RAM 350 functions as a work area and a data storage area for the processing unit 330 and the data transfer control device 310. The display unit 360 displays various information to the user. The operation unit 370 is for the user to operate the electronic device.

  In FIG. 17, the DMA bus and the CPU bus are separated, but they may be shared. Further, a processing unit that controls the data transfer control device 310 and a processing unit that controls the electronic apparatus may be provided separately.

  The electronic device 300 of the present embodiment includes a mobile phone, a portable music player, a portable video player, a video camera, a digital camera, an optical disk drive device, a hard disk drive device, an audio device, a portable game machine, an electronic notebook, an electronic notebook Various things such as a dictionary or a portable information terminal can be considered.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, at least once, terms (AVDD,) described together with different terms having a broader meaning or the same meaning (first power supply, second power supply, first signal line, second signal line, etc.) (AVSS, DP, DM, etc.) can be replaced by the different terms anywhere in the specification or drawings. In addition, the configurations and operations of the integrated circuit device, the data transfer control device, the transmission circuit, and the electronic device are not limited to those described in this embodiment, and various modifications can be made. In this embodiment, the application example of the present invention to USB 2.0 has been described. However, the present invention is also applied to a standard based on the same idea as USB 2.0, a standard developed from USB 2.0, and the like. it can.

2 is a configuration example of a data transfer control device realized by the integrated circuit device of the present embodiment. 2 is a configuration example of a transmission circuit and a transmission control circuit. 6 shows another configuration example of a transmission circuit and a transmission control circuit. 6 is a layout example of an integrated circuit device. A layout example of a transmission circuit for LS and FS. A detailed layout example of a transmission circuit for LS and FS. 7A and 7B are a configuration example and a truth table of the signal generation circuit of the transmission control circuit. 8A, 8B, and 8C show examples of signal waveforms such as transmission control signals. 2 is a configuration example of an HS transmission circuit. 10A and 10B are signal waveform examples of the transmission control signal for HS. The 1st modification of the transmission circuit for HS. Explanatory drawing of an eye pattern. The example of a structure of a termination resistance circuit. 14A, 14B, and 14C are examples of N-type transistors that form a resistance circuit. The 2nd modification of the transmission circuit for HS. 2 is a configuration example of a buffer circuit. Configuration example of an electronic device.

Explanation of symbols

PT1, PT2, PT3, PT4 P-type transistor,
NT1, NT2, NT3, NT4 N-type transistor,
QN1, QN2, QN3, QN4 output nodes,
OP1, ON1, OP2, ON2, OP3, ON3, OP4, ON4 transmission control signal,
GC1, GC2, GC3 transmission control signal,
10 constant current circuit, 20 current control circuit, 22 current setting information register,
30, 32, 34 termination resistance circuit, 40 termination resistance control circuit,
42 terminal resistance setting information register, 50 LS transmission circuit, 52 FS transmission circuit,
54 HS transmission circuit, 60 LS transmission control circuit, 62 FS transmission control circuit,
64 HS transmission control circuit, 71, 72, 73, 74 transmission driver,
81, 82, 83, 84 signal generation circuit,
520-1, 520-2, 520-3 capacity adjustment circuit,
510-1, 510-2, 510-3 Buffer circuit

Claims (10)

A circuit for transmitting data in a first transfer mode via first and second signal lines constituting a differential pair, wherein the first transmission driver drives the first signal line; A first transmission circuit for a first transfer mode having a second transmission driver for driving two signal lines;
A circuit for transmitting data in a second transfer mode, in which data transfer is faster than the first transfer mode, via the first and second signal lines constituting a differential pair, A second transmission circuit for a second transfer mode having a third transmission driver for driving a signal line and a fourth transmission driver for driving the second signal line;
The first constituting a differential pair, via a second signal line, first for the third transfer mode of the even data transfer from the second transfer mode for transmitting data at a high-speed third transfer mode 3 transmission circuits ;
A first transmission control circuit for a first transfer mode that generates and outputs a first P-side, N-side transmission control signal and a second P-side, N-side transmission control signal;
A second transmission control circuit for a second transfer mode that generates and outputs a third P-side, N-side transmission control signal and a fourth P-side, N-side transmission control signal;
A first P-type transistor constituting the first transmission driver for the first transfer mode and a third P-type transistor constituting the third transmission driver for the second transfer mode are the first Formed in the P-type transistor region,
A first N-type transistor constituting the first transmission driver for the first transfer mode and a third N-type transistor constituting the third transmission driver for the second transfer mode are the first Formed in the N-type transistor region,
A second P-type transistor constituting the second transmission driver for the first transfer mode and a fourth P-type transistor constituting the fourth transmission driver for the second transfer mode are second Formed in the P-type transistor region,
A second N-type transistor constituting the second transmission driver for the first transfer mode and a fourth N-type transistor constituting the fourth transmission driver for the second transfer mode are second Formed in the N-type transistor region,
The third transmission circuit includes:
A constant current circuit provided between the first power source and a given node;
A first switch element provided between the node and the first signal line;
Look including a second switch element provided between said second signal line and the nodes,
The first P-type transistor is provided between a first output node that is an output node of the first transmission driver and a first power supply, and the first P-side transmission control signal is provided at a gate thereof. Entered,
The first N-type transistor is provided between the first output node and a second power supply, and the gate thereof receives the first N-side transmission control signal.
The second P-type transistor is provided between a second output node, which is an output node of the second transmission driver, and the first power supply, and has the second P-side transmission control signal at its gate. Is entered,
The second N-type transistor is provided between the second output node and the second power supply, and the gate thereof receives the second N-side transmission control signal.
The third P-type transistor is provided between a third output node, which is an output node of the third transmission driver, and the first power supply, and has a third P-side transmission control signal at its gate. Is entered,
The third N-type transistor is provided between the third output node and the second power source, and the third N-side transmission control signal is input to a gate thereof.
The fourth P-type transistor is provided between a fourth output node, which is an output node of the fourth transmission driver, and the first power supply, and has a fourth P-side transmission control signal at its gate. Is entered,
The fourth N-type transistor is provided between the fourth output node and the second power supply, and the gate thereof receives the fourth N-side transmission control signal.
The first transmission control circuit includes:
The first P-side and N-side transmission control signals output from the second transmission control circuit and the first P having a longer rise time or fall time than the fourth P-side and N-side transmission control signals. Side, N side transmission control signal and the second P side, N side transmission control signal are generated and output . In claim 1,
The third transmission circuit includes:
A current control circuit that variably controls a value of a current flowing from the constant current circuit, and the current from the constant current circuit variably controlled by the current control circuit causes the first switching element to pass through the first switch element. An integrated circuit device, wherein one signal line is driven and the second signal line is driven through the second switch element. In claim 1 or 2,
A first buffer circuit that outputs a first transmission control signal to a gate of a first transistor constituting the first switch element;
A second buffer circuit for outputting a second transmission control signal to the gate of the second transistor constituting the second switch element;
When one of the first and second transmission control signals is set to active, the other transmission control signal is set to inactive,
Each of the first and second buffer circuits includes:
A first inverter;
A second inverter whose input node is connected to the output node of the first inverter;
An integrated circuit device comprising a capacitance adjustment circuit connected to an output node of the first inverter. In any one of Claims 1 thru | or 3 ,
The first P-type transistor region and the first N-type transistor region are formed adjacent to each other;
The integrated circuit device, wherein the second P-type transistor region and the second N-type transistor region are formed adjacent to each other. In any one of Claims 1 thru | or 4 ,
A first damping resistor provided between a first node to which an output node of the first and third transmission drivers is connected and the first signal line;
A second damping resistor provided between the second node to which the output node of the second and fourth transmission drivers is connected and the second signal line;
The first damping resistor is formed in a first resistance region adjacent to the first N-type transistor region;
The integrated circuit device, wherein the second damping resistor is formed in a second resistance region adjacent to the second N-type transistor region. In claim 5 ,
The integrated circuit device, wherein the first and second damping resistors are formed of an N-type diffusion layer. In any one of Claims 1 thru | or 6 .
A first termination resistor circuit provided between a first node to which an output node of the first and third transmission drivers is connected and a second power supply;
A second node connected to an output node of the second and fourth transmission drivers, and a second termination resistor circuit provided between the second power source,
An N-type transistor constituting the first termination resistor circuit is formed in the first N-type transistor region;
An integrated circuit device, wherein an N-type transistor constituting the second termination resistor circuit is formed in the second N-type transistor region. In claim 7 ,
An integrated circuit device comprising: a termination resistance control circuit that variably controls termination resistance values of the first and second termination resistance circuits. In any one of Claims 1 thru | or 8 .
The first P-type transistor and the third P-type transistor are arranged side by side in the first P-type transistor region,
The first N-type transistor and the third N-type transistor are arranged side by side in the first N-type transistor region,
The second P-type transistor and the fourth P-type transistor are arranged side by side in the second P-type transistor region;
The integrated circuit device, wherein the second N-type transistor and the fourth N-type transistor are arranged side by side in the second N-type transistor region. An integrated circuit device according to any one of claims 1 to 9 ,
A processing unit for controlling the integrated circuit device;
An electronic device comprising: