CN115332234A - Fully exposed dual-core series packaging body, packaging method and PCB - Google Patents

Fully exposed dual-core series packaging body, packaging method and PCB Download PDF

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Publication number
CN115332234A
CN115332234A CN202211041008.3A CN202211041008A CN115332234A CN 115332234 A CN115332234 A CN 115332234A CN 202211041008 A CN202211041008 A CN 202211041008A CN 115332234 A CN115332234 A CN 115332234A
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China
Prior art keywords
chip
source
gate
die
conductive plate
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CN202211041008.3A
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Chinese (zh)
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梁志忠
李明芬
陈育锋
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Hefei Big Grid Technology Partnership LP
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Hefei Big Grid Technology Partnership LP
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Priority to CN202211041008.3A priority Critical patent/CN115332234A/en
Publication of CN115332234A publication Critical patent/CN115332234A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector

Abstract

The invention discloses a fully exposed dual-core serial packaging body, a packaging method and a PCB, and belongs to the field of semiconductor packaging. The device comprises a lead frame, a first chip and a second chip, wherein the second chip and the first chip are arranged in an up-and-down stacked mode, and a source electrode of the first chip is arranged opposite to a drain electrode of the second chip; the drain electrode of the first chip is bonded to the drain electrode pin of the lead frame, and the source electrode of the first chip is bonded to the drain electrode of the second chip; the source electrode of the second chip is bonded to the source electrode pin of the lead frame; the grid of the first chip and the grid of the second chip are both bonded to the grid pin of the lead frame, and the source electrode conducting plate is completely exposed out of the plastic package body. The invention can improve the voltage capability; the manufacturing cost of at least one chip plastic package body can be reduced; the development and production of different chips and the inventory cost of the packaging body can be reduced; by exposing the source conductive plate, the heat dissipation efficiency can be improved.

Description

Fully-exposed dual-core serial packaging body, packaging method and PCB
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a fully exposed dual-core serial packaging body, a packaging method and a PCB.
Background
A conventional typical MOSFET power chip package generally adopts a package type of placing a single MOSFET power chip in a package, and the key processes of the MOSFET power chip package process are divided into several package process methods and steps due to different applications. The key process change is mainly the mode of leading out the bonding of the inner lead of the metal lead frame outside the chip from the functional area on the front surface of the chip, and the bonding modes are not limited to pure metal wire bonding, metal tape and metal wire mixed bonding, metal sheet matched metal tin paste bonding and metal wire mixed bonding and full metal sheet matched metal tin paste bonding.
The different bonding techniques have different process flows and methods, but basically, in any bonding manner, a traditional mainstream packaging mode for mounting a single MOSFET power chip in a single package is adopted.
The traditional single MOSFET power chip packaging model has the following defects:
1. if the traditional single power chip packaging type is applied to the situation of higher power, a single MOSFET power chip with higher power needs to be developed particularly and then packaged, so that the development cost needs to be increased, the production cost needs to be increased, and the product development period needs to be prolonged;
2. increasing the development of higher voltage MOSFET power chips will increase the inventory cost of different MOSFET power chips;
3. the other method is to adopt a plurality of single MOSFET power chip packages, then connect a plurality of low-power MOSFET power chips in series, and weld the power chips on a PCB (printed circuit board) to increase voltage, so that the number of the single packages is increased, and the number of the packages and the production cost of the plastic package are also increased;
4. the packaging bodies of a plurality of single MOSFET power chips are serially connected and welded on a PCB (printed circuit board), and meanwhile, the using area of the PCB is increased, so that the production cost and the inventory cost of the area of the PCB are increased.
5. The packaging body of the existing MOSFET power chip completely covers the power chip through the plastic packaging body, when the power is higher, the heat dissipation is not timely, and the power chip is easy to damage due to overhigh temperature.
Therefore, the above-mentioned drawbacks of the conventional single MOSFET power chip are the current trends of overcoming and reducing the cost, and are the difficulties of reducing the cost in the field of fast charging and accelerating the MOSFET power chip.
Disclosure of Invention
The invention provides a fully exposed double-core series packaging body which can solve the problems of high cost, long development period and poor heat dissipation effect of a single power chip packaging mode in the prior art.
The invention also provides a packaging method of the fully exposed dual-core series packaging body, which is used for preparing the packaging body.
The invention also provides a PCB board, which can reduce the area of the circuit board and reduce the production cost of the PCB board.
A fully exposed dual-core series packaging body comprises a lead frame, a first chip, a second chip, a plastic packaging body, a source electrode conductive plate and a grid electrode conductive plate;
the source electrode conductive plate, the grid electrode conductive plate, the second chip, the first chip and the lead frame are sequentially arranged from top to bottom, and the source electrode conductive plate and the grid electrode conductive plate are both positioned above the second chip; wherein the content of the first and second substances,
the drain electrode of the first chip is connected to a drain electrode pin through a base island, and the drain electrode of the second chip is attached to the source electrode of the first chip;
the source electrode of the second chip is connected to a source electrode pin through the source electrode conducting plate;
the grid of the first chip and the grid of the second chip are connected to a grid pin through the grid conductive plate; wherein the content of the first and second substances,
the source electrode conducting plate is completely exposed out of the plastic packaging body.
Preferably, the end face of the source electrode conducting plate facing the lead frame and the end face of the plastic package body far away from the lead frame are in the same plane.
Preferably, the source conductive plate is integrally provided with the source pin, and the gate conductive plate is integrally provided with the gate pin.
Preferably, one end of the source conductive plate extends to the outer side of the plastic package body and extends towards the direction of the base island to form a source pin; one end of the grid conducting plate extends to the outer side of the plastic package body and extends towards the direction of the base island to form a grid pin.
Preferably, a metal spacer is disposed between the first chip and the second chip, the source of the first chip and the drain of the second chip are connected through the metal spacer, and the metal spacer forms a bonding space for accommodating a bonding wire between the first chip and the second chip.
Preferably, the first chip and the second chip are arranged in a staggered manner, so that the projection of the gate of the first chip in the vertical direction is completely exposed to the projection of the second chip.
More preferably, the source conductive plate and the gate conductive plate are made of copper or aluminum.
A packaging method of a fully exposed dual-core serial packaging body comprises the following steps:
s1, coating a bonding substance with conductive property on a base island to connect a drain electrode of a first chip with the base island through the bonding substance;
s2, coating an adhesive substance on the source electrode of the first chip, and connecting the drain electrode of the second chip to the source electrode of the first chip through the adhesive substance;
s3, coating adhesive substances on the grid electrode of the first chip, the source electrode of the second chip, the grid electrode of the second chip, the source electrode pin of the lead frame and the grid electrode pin of the lead frame, and connecting a source electrode conductive plate with the source electrode pin of the second chip through the adhesive substances;
s4, connecting a grid conductive plate with the grid of the first chip, the grid of the second chip and the grid pin through bonding substances;
s5, carrying out plastic packaging to form a plastic packaging body;
and S6, cutting the single chip to obtain the fully exposed dual-core serial packaging body.
A PCB board comprises at least one packaging body.
The invention provides a fully exposed dual-core serial packaging body, which can at least achieve one of the following effects:
1. the voltage capability can be improved under the condition that plastic packaging bodies with the same current and the same area can be realized;
2. by means of the dual-chip heteropolarity series bonding plastic package structure, the manufacturing cost of at least one power chip plastic package body can be reduced;
3. by adopting the power chip heteropolarity series bonding plastic package structure, the development and production of different power chips and the inventory cost of a package body can be reduced;
4. by exposing the source conductive plate, the heat dissipation efficiency can be improved.
The invention provides a packaging method of a fully exposed double-core series packaging body, which is simple in process flow.
The invention provides a PCB (printed circuit board), which can realize a plastic package body with the same area, and reduce the increase of the use area and the cost caused by the increase of higher voltage when the PCB is used.
Drawings
FIG. 1 is a schematic diagram of an internal structure of a fully exposed dual-core serial package according to the present invention;
FIG. 2 is a schematic diagram of a second internal structure of a fully exposed dual-core serial package according to the present invention;
FIG. 3 is a third schematic view of the internal structure of a fully exposed dual-core serial package according to the present invention;
FIG. 4 is a schematic diagram illustrating an internal structure of a fully exposed dual-core serial package according to another embodiment;
FIG. 5 is a schematic structural diagram of a fully exposed dual-core serial package according to the present invention;
FIG. 6 is a schematic diagram illustrating an internal structure of a fully exposed dual-core serial package according to another embodiment;
fig. 7 is a schematic cross-sectional view of a fully exposed dual-core serial package according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional view of an exposed dual-core tandem package according to another embodiment of the present invention.
Description of reference numerals:
00 a bonding substance; 10 base islands; 11 a drain lead; 12 a source lead; 13 a gate pin; 20 a first chip; 30 source conductive plates; 31 a gate conductive plate; 40 a second chip; 60 molding the body; 70 lead frame.
Detailed Description
An embodiment of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the embodiment.
The first embodiment is as follows:
as shown in fig. 1 to 3, a fully exposed dual-chip serial package according to an embodiment of the present invention includes a lead frame 70, a first chip 20, a second chip 40, a source conductive plate 30, and a gate conductive plate 31, where the lead frame 70 includes a base island 10, a drain lead 11, a gate lead 13, and a source lead 12, the second chip 40 and the first chip 20 are stacked one on another, and a source of the first chip 20 is disposed opposite to a drain of the second chip 40; the drain of the first chip 20 is bonded to the drain lead 11 of the lead frame 70, and the source of the first chip 20 is bonded to the drain of the second chip 40; the source of the second chip 40 is bonded to the source lead 12 of the lead frame 70; the gate of the first chip 20 and the gate of the second chip 40 are both bonded to the gate lead 13 of the lead frame 70.
In the present embodiment, the first chip 20 and the second chip 40 are both MOSFET power chips as an example.
As shown in fig. 1 and 2, which show a schematic structural view when a part of the structure is omitted, wherein the source and gate conductive plates 30 and 31, the second chip 40, the first chip 20, and the lead frame 70 are sequentially arranged from top to bottom, the source and gate conductive plates 30 and 31 are both located on the upper side of the second chip 40, and the source and gate conductive plates 30 and 31 are located on the same horizontal plane; wherein, the first and the second end of the pipe are connected with each other,
as shown in fig. 1, the drain electrode of the first chip 20 is coated with an adhesive substance 00, and the adhesive substance 00 may be metal tin paste, conductive silver paste or other adhesive substances 00 with conductive properties. The drain of the first chip 20 is connected to the base island 10 through the adhesive material 00, and is electrically connected to the base island 10; as shown in fig. 2, the second chip 40 is located above the first chip 20, the source of the first chip 20 is coated with the adhesive material 00, and the drain of the second chip 40 is attached to and electrically connected to the source of the first chip 20, it should be noted that the gate of the first chip 20 is exposed out of the second chip 40, that is, the gate of the first chip 20 is not covered when the second chip 40 is attached to the first chip 20; the gate and the source of the second chip 40 are coated with the adhesive substance 00, the source of the second chip 40 is bonded to the source lead 12 through the source conductive plate 30, and the gate of the first chip 20 and the gate of the second chip 40 are bonded to the gate lead 13 through the gate conductive plate 31.
It should be noted that the source conductive plate 30 is completely exposed from the molding compound 60 to improve the heat dissipation efficiency.
Specifically, in one embodiment, as shown in fig. 7, an end surface of the source conductive plate 30 facing the lead frame 70 is coplanar with an end surface of the plastic package body 60 away from the lead frame 70. That is, the lower end surface of the source conductive plate 30 is flush with the upper end surface of the plastic package body 60, so that the source conductive plate 30 is completely exposed to the air, so that the heat in the plastic package body 60 can be better conducted out. It should be noted that the source conductive plate 30 is connected to the source lead 12 through the conductive adhesive 00, and the gate conductive plate 31 is connected to the gate lead 13 through the conductive adhesive 00, which may reduce the strength of the connection and complicate the operation of the connection. Therefore, in the present embodiment, the source conductive plate 30 and the source lead 12 are integrally provided, and the gate conductive plate 31 and the gate lead 13 are integrally provided, so that the conductive adhesive substance 00 connection is eliminated, so that the strength is higher, and the bonding process can be reduced.
In another embodiment, as shown in fig. 8, one side of each of the source conductive plate 30 and the gate conductive plate is extended downward to form a connection portion, and the connection portion may be directly soldered to the PCB. By directly bonding the source conductive plate 30 and the gate conductive plate 31, the source lead 12 and the gate lead 13 can be eliminated, and the structure can be simplified, compared with the conventional bonding wire.
In addition, since the drain of the second chip 40 is bonded to the source of the first chip 20, the gate of the first chip 20 can be smoothly led out of the gate conductive plate 31 or the lead (when wire bonding is used) so as to be bonded, and the following methods can be used to achieve the above object.
In the first mode, a metal spacer is disposed between the first chip 20 and the second chip 40, the metal spacer can achieve conduction between the source of the first chip 20 and the drain of the second chip 40, and at the same time, a certain gap can be formed between the first chip 20 and the second chip 40, so that a lead can be led out through the gap, thereby bonding the gate of the first chip 20 to the gate lead 13, when the gate conductive plate 31 is used, one end of the gate conductive plate 31 is connected to the gate lead 13, and the other end of the gate conductive plate 31 forms two bonding contacts (e.g., two bonding wires), one bonding contact is connected to the gate of the first chip 20, and the other bonding contact is connected to the gate of the second chip 40. In this manner, the projections of the first chip 20 and the second chip 40 in the vertical direction do not need to be arranged offset.
In the second way, the first chip 20 and the second chip 40 may be arranged in a staggered manner such that the gate of the first chip 20 is exposed for bonding. Fig. 2 and 3 show two ways of dislocation arrangement. In the mode of fig. 2, the gate of the first chip 20 and the gate of the second chip 40 are located at two opposite sides, the gate conductive plate 31 is in an M-shaped structure, and three connection terminals extend downward from the gate conductive plate 31 and are respectively connected to the gate of the first chip 20, the gate of the second chip 40, and the gate pin 13. In the manner illustrated in fig. 3, the structure is similar, except that the gate of the first chip 20 and the gate of the second chip 40 are disposed on the same side.
In a third mode, the first chip 20 and the second chip 40 may be arranged in a vertically overlapped manner, and the second chip 40 may be rotated along its central axis, for example, by 45 °, so as to expose the gate of the first chip 20.
In any case, the final purpose is to enable the gate of the first chip 20 and the gate of the second chip 40 to be commonly bonded to the gate lead 13. It should be understood that those skilled in the art can also implement the technical solutions of the present invention according to other general methods capable of achieving the above-mentioned objects, and the technical solutions should also fall into the protection scope of the present invention.
Specifically, the source conductive plate 30 and the gate conductive plate 31 are made of copper or aluminum.
Because the source of the MOSFET power chip is connected with the source pin 12 by adopting the source conducting plate 30, and the grid is connected with the grid pin 13 by adopting the grid conducting plate 31, compared with the existing metal wire bonding, the MOSFET power chip has smaller on-resistance, and in addition, compared with the metal wire bonding, the conducting plate has larger volume, can improve the heat absorption capacity, and further improves the instantaneous temperature fluctuation during the operation.
Example two:
a packaging method of a fully exposed dual-core serial packaging body comprises the following steps:
s1, coating a conductive adhesive substance 00 on a base island 10 to connect a drain electrode of a first chip 20 with the base island 10 through the adhesive substance 00;
s2, coating an adhesive substance 00 on the source electrode of the first chip 20, connecting the drain electrode of the second chip 40 to the source electrode of the first chip 20 through the adhesive substance 00, and exposing the grid electrode of the first chip 20;
s3, coating adhesive substance 00 on the gate of the first chip 20, the source of the second chip 40, the gate of the second chip 40, the source lead 12 of the lead frame 70 and the gate lead 13 of the lead frame 70, and connecting the source conductive plate 30 with the source lead 12 and the source of the second chip 40 through the adhesive substance 00;
s4, connecting the grid conductive plate 31 with the grid of the first chip 20, the grid of the second chip 40 and the grid pin 13 through the bonding substance 00;
s5, carrying out plastic packaging to form a plastic packaging body 60;
and S6, cutting the single chip to obtain the fully exposed dual-core serial packaging body.
By the packaging method, the series connection of the two MOSFET power chips can be realized.
It is understood that the above-described step S4 is not required when the source conductive plate 30 and the source lead 12 are integrally provided, the gate conductive plate 31 and the gate lead 13 are integrally provided, or when the source conductive plate 30 and the gate conductive plate 31 are directly led out of the connection portion.
Example three:
a PCB board comprises at least one packaging body, and the number of the specific packaging bodies is determined according to the design of the PCB board. In the packaging process, the series connection of the double MOSFET power chips is completed, when the application needs higher voltage, as long as a fully exposed double-chip series packaging body is installed and welded on the PCB, the packaging body with more single MOSFET power chips mounted on the PCB can be avoided, the area cost occupied by the PCB can be saved, and the use and production cost of the MOSFET power chip packaging body can be reduced.
The above disclosure is only for a few specific embodiments of the present invention, however, the present invention is not limited to the above embodiments, and any modifications that can be made by those skilled in the art are intended to fall within the scope of the present invention.

Claims (9)

1. A fully exposed dual-core series package body comprises a lead frame (70), a first chip (20), a second chip (40) and a plastic package body (60), and is characterized by further comprising a source electrode conductive plate (30) and a grid electrode conductive plate (31);
the source electrode conducting plate (30), the gate electrode conducting plate (31), the second chip (40), the first chip (20) and the lead frame (70) are sequentially arranged from top to bottom, and the source electrode conducting plate (30) and the gate electrode conducting plate (31) are both located above the second chip (40); wherein, the first and the second end of the pipe are connected with each other,
the drain electrode of the first chip (20) is connected to a drain electrode pin (11) through a base island (10), and the drain electrode of the second chip (40) is attached to the source electrode of the first chip (20);
the source of the second chip (40) is connected to a source pin (12) through the source conductive plate (30);
the gate of the first chip (20) and the gate of the second chip (40) are both connected to a gate pin (13) through the gate conductive plate (31); wherein the content of the first and second substances,
the source electrode conducting plate (30) is completely exposed out of the plastic packaging body (60).
2. A substantially exposed dual-core series package according to claim 1, wherein the end surface of the source conductive plate (30) facing the lead frame (70) is coplanar with the end surface of the molding compound (60) away from the lead frame (70).
3. A fully exposed dual die series package according to claim 1, wherein the source conductor plate (30) is integral with the source lead (12) and the gate conductor plate (31) is integral with the gate lead (13).
4. A substantially exposed dual-die series package according to claim 1, wherein one end of the source conductive plate (30) extends to the outside of the molding compound (60) and extends toward the base island (10) to form a source lead (12); one end of the gate conductive plate (31) extends to the outer side of the plastic package body (60) and extends towards the direction of the base island (10) to form a gate pin (13).
5. A substantially exposed dual-die serial package according to claim 1, wherein a metal spacer is disposed between the first die (20) and the second die (40), the source of the first die (20) and the drain of the second die (40) being connected by the metal spacer, the metal spacer forming a bonding space for receiving bonding wires between the first die (20) and the second die (40).
6. A fully exposed dual-die serial package according to claim 1, wherein the first die (20) and the second die (40) are disposed in a staggered manner such that the projection of the gate of the first die (20) along the vertical direction is completely exposed to the projection of the second die (40).
7. A fully exposed dual die tandem package according to any of claims 1-6, wherein the source conductor plate (30) and the gate conductor plate (31) are made of copper or aluminum.
8. The method for packaging the fully exposed dual-core tandem package according to claim 1 or 2, comprising the steps of:
s1, coating an adhesive substance (00) with conductive property on a base island (10) and connecting a drain electrode of a first chip (20) with the base island (10) through the adhesive substance (00);
s2, coating an adhesive substance (00) on the source electrode of the first chip (20), and connecting the drain electrode of the second chip (40) to the source electrode of the first chip (20) through the adhesive substance (00);
s3, coating an adhesive substance (00) on the gate of the first chip (20), the source of the second chip (40), the gate of the second chip (40), the source lead (12) of the lead frame (70) and the gate lead (13) of the lead frame (70), and connecting the source conductive plate (30) with the source lead (12) and the source of the second chip (40) through the adhesive substance (00);
s4, connecting a grid conductive plate (31) with the grid of the first chip (20), the grid of the second chip (40) and the grid pin (13) through an adhesive substance (00);
s5, carrying out plastic packaging to form a plastic packaging body (60);
and S6, cutting the single chip to obtain the fully exposed double-core serial packaging body.
9. A PCB board comprising at least one package according to any of claims 1 to 6.
CN202211041008.3A 2022-08-29 2022-08-29 Fully exposed dual-core series packaging body, packaging method and PCB Pending CN115332234A (en)

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