CN115332208B - Semiconductor packaging device and manufacturing method - Google Patents
Semiconductor packaging device and manufacturing method Download PDFInfo
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- CN115332208B CN115332208B CN202211264676.2A CN202211264676A CN115332208B CN 115332208 B CN115332208 B CN 115332208B CN 202211264676 A CN202211264676 A CN 202211264676A CN 115332208 B CN115332208 B CN 115332208B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/85801—Soldering or alloying
- H01L2224/85815—Reflow soldering
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The application relates to the technical field of semiconductor device processing, and provides a semiconductor packaging device and a manufacturing method thereof, wherein the semiconductor packaging device comprises a packaging layer and a chip arranged in the packaging layer; a die attach pad fixedly connected to the die; the first functional pins and the bonding pad base islands are arranged at intervals in a first direction; the bridging piece is fixedly connected with the chip and the first functional pin; the first functional pin is provided with a first limiting step arranged at one end in the first direction and a first limiting boss; the bridging piece is provided with a plurality of clamping parts arranged at one end, the clamping parts are arranged at intervals along a second direction, the bridging piece is provided with a clamping groove, and the first direction is vertical to the second direction; the clamping part abuts against the first limiting step, and the first limiting boss is embedded in the clamping groove to limit the positions of the first function pin and the bridging piece. The problem of among the prior art copper bridge and chip and function pin between fixed stability not good, easily arouse the copper bridge poor of off normal is solved.
Description
Technical Field
The present application relates to the field of semiconductor device processing technologies, and more particularly, to a semiconductor package device and a method for manufacturing the same.
Background
At present, consumer products develop towards the direction of miniaturization and high integration, a chip is fixed on a bonding pad base island, a functional pin is arranged around the bonding pad base island, the chip, the bonding pad island and the functional pin are packaged through a packaging layer, and the existing semiconductor packaging structure is widely used with superior service performance and applicability.
However, the following problems exist in the package structure currently used in the market: when the functional pin and the bonding pad base island are arranged at intervals, a bridging piece is needed to be used for connecting the chip and the functional pin, for example, a copper bridge is adopted, in the existing production process, the stability of fixation among the copper bridge, the chip and the functional pin is poor, and the copper bridge is prone to poor deviation due to wind power of a reflow oven or other external force in the process of over-high temperature reflow soldering.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The application aims to provide a semiconductor packaging device and a manufacturing method, and solves the problem that in the prior art, the stability of fixation among a copper bridge, a chip and a functional pin is poor, so that the copper bridge is prone to poor deviation due to the effect of wind force of a reflow oven in a high-temperature reflow soldering process.
In order to achieve the purpose, the technical scheme adopted by the application is as follows:
the application provides a semiconductor package device, including the packaging layer, set up the chip in the packaging layer, wherein, semiconductor package device still includes:
the chip bonding base island is fixedly connected with the chip;
the first functional pin and the bonding pad base island are arranged at intervals in a first direction;
the bridging piece is fixedly connected with the chip and the first functional pin;
the first functional pin is provided with a first limiting step arranged at one end in the first direction, and the first functional pin is provided with a first limiting boss;
the bridge is provided with a plurality of clamping parts which are arranged at one end and are arranged at intervals along a second direction, and the bridge is provided with a clamping groove, wherein the first direction is vertical to the second direction;
the clamping part abuts against the first limiting step, and the first limiting boss is embedded in the clamping groove to limit the positions of the first function pin and the bridging piece.
Optionally, the first limiting boss is located on one side of the first limiting step, which faces the chip, and the clamping groove is located on one side of the clamping portion, which faces the chip;
the screens groove is located the one side of position between the adjacent screens portion in a plurality of screens portion.
Optionally, the detent groove extends to an edge of the bridge in the first direction and forms a notch;
the notch is arranged in a conical shape.
Optionally, a side of the bridge facing the chip is provided with a first dimple portion, and a side of the bridge facing away from the chip is provided with a second dimple portion.
Optionally, the first and second pockmarks are arranged in a staggered manner.
Optionally, one end of the adhesive sheet base island departing from the first function pin in the first direction is provided with a second function pin, a waterproof portion is arranged on the adhesive sheet base island and extends along the second direction, and the waterproof portion is located between the chip and the second function pin.
Optionally, a chip limit groove is formed in the chip bonding base island and used for accommodating a chip;
a second limiting boss is convexly arranged on the side wall of the clamping limit groove and is over against the side surface of the chip so as to limit the position of the chip;
an occlusion gap is formed between the second limit boss and the bottom surface of the clamping limit groove, and the occlusion gap is used for filling the tablet for bonding the chip.
Optionally, a flow guide groove is formed in the bottom surface of the card limit groove, and the flow guide groove extends along the second direction and is used for filling the adhesive tablet for adhering the chip.
Optionally, a second limiting step is arranged at an edge of one side of the die pad base island, which is away from the chip, and the second limiting step is used for filling the packaging layer.
Optionally, the bridge further comprises:
the convex straight part is positioned on one side of the clamping part and extends along the first direction, and the surface of the convex straight part, which is far away from the chip, is a plane;
the first electric connection part is connected to one side, away from the clamping part, of the convex straight part and is used for connecting the chip;
the clearance convex part is arranged at intervals with the chip, and one end of the clearance convex part is connected with the first electric connection part;
and the second electric connection part is connected to the other end of the clearance protrusion part and used for connecting the chip, and the second electric connection part and the first electric connection part are arranged at intervals.
Based on the same concept, the present application also proposes a method of manufacturing a semiconductor package device for producing the semiconductor package device as described above, the method comprising the steps of:
scribing the wafer to form a chip, and adhering the chip to the chip-adhering base island through the wafer-adhering piece;
fixing the chip and the bonding pad base island by reflow soldering, wherein a product is obtained by heating and soldering a soldering material in a vacuum reflow furnace through a plurality of temperature zones with different preset temperatures;
cleaning the welded product, wherein organic matters of the product after reflow soldering are removed through chemical cleaning, and a soldering area of a lead on the product is processed through plasma cleaning;
welding a lead of the cleaned product;
and carrying out plastic package, curing, sub-oxidizing light removal and baking on the product with the lead welded to form a packaging layer.
The semiconductor packaging device and the manufacturing method provided by the application have the beneficial effects that at least: when the bridging piece is fixed with the first function pin, one end (left end) of the first function pin is provided with a first limiting step, and the bridging piece abuts against the left side of the first limiting step through a plurality of clamping parts on the left side, so that the left side of the first function pin is limited, and the first function pin cannot move towards the left side; a clamping groove is formed in the bridging piece, the clamping groove is located around the right side of the clamping portion and is not far away from the clamping portion, a first limiting boss is arranged on the first function pin, and the first limiting boss is embedded in the clamping groove for limiting, so that the first function pin cannot move towards the right side; through above structure, realized the fixed connection of bridgeware and first function pin and chip, when the process of high temperature reflow soldering received reflow oven wind-force and assaulted, formed triangle fixed function between two in a plurality of screens portion and the first spacing boss, still enabled bridgeware and first function pin and firmly connected, avoided the bridgeware because of receiving external force and causing the problem that the product is bad that the off normal leads to, promoted the encapsulation yield of product, promoted the yield.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a cross-sectional view of a semiconductor package device in accordance with an embodiment of the present invention;
fig. 2 is a perspective view of a semiconductor package device in accordance with an embodiment of the present invention;
fig. 3 is a front view of a semiconductor package device according to an embodiment of the present invention before it is unpackaged;
FIG. 4 isbase:Sub>A cross-sectional view of the cross-section A-A of FIG. 3;
FIG. 5 is an enlarged view of portion B of FIG. 4;
fig. 6 is a cross-sectional view of a bridge of a semiconductor package device according to an embodiment of the present invention;
fig. 7 is a cross-sectional view of a semiconductor package device according to another embodiment of the present invention.
Wherein, in the figures, the respective reference numerals:
100. a packaging layer; 200. a chip; 210. sticking tablets; 300. bonding a base island; 310. a clamping limit groove; 311. a second limit boss; 312. an occlusion gap; 313. an inclined surface; 320. a diversion trench; 330. a second limit step; 340. a waterproof section; 400. a bridge member; 410. a first bridge plate; 411. a clamping part; 412. a clamping groove; 413. a notch; 420. a first pockmark part; 430. a second pockmark part; 440. a convex straight portion; 450. a first electrical connection portion; 460. a clearance boss; 461. glue fixing holes; 470. a second electrical connection portion; 500. a first function pin; 510. a pin outer plate; 520. a pin inner plate; 521. a first limit boss; 530. a first limit step; 600. a second function pin; 700. a third function pin; 710. and (6) leading wires.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless explicitly defined otherwise.
As shown in fig. 1 and fig. 2, the present embodiment provides a semiconductor package device, which mainly includes a package layer 100, a chip 200 disposed in the package layer 100, a die pad 300, and a first functional lead 500 disposed on the package layer 100. The outline of the projection of the adhesive sheet base island 300 on the horizontal plane is generally square; for convenience of structural description, a direction of one side of the square adhesive sheet base 300 is taken as a first direction (left-right direction), a direction of the other side thereof is taken as a second direction (front-back direction), the second direction is perpendicular to the first direction, and a direction perpendicular to a horizontal plane is taken as an up-down direction. The die attach pad 300 is located at the lower part of the device, the upper surface of the die attach pad 300 is fixedly connected to the chip 200, the upper part of the chip 200 is fixedly connected to the right end of the bridge 400, the left end of the bridge 400 is connected to the upper surface of the first functional pin 500, the first functional pin 500 is located at the left side of the die attach pad 300 and is arranged at an interval with the die attach pad 300 in a first direction (left-right direction), and the interval space is filled with a packaging material, so as to form a part of the packaging layer 100. The bridging member 400 in this embodiment is a copper bridge. The first functional pin 500 has a first limiting step 530 on the left side thereof, the first functional pin 500 is specifically composed of an outer pin plate 510 and an inner pin plate 520, the lower surface and the side surface of the outer pin plate 510 are exposed out of the package layer 100, the inner pin plate 520 is connected above the outer pin plate 510 and located on the right side of the outer pin plate 510, and the inner pin plate 520 is located in the package layer 100, so that the upper surface of the inner pin plate 520 is higher than the upper surface of the outer pin plate 510, and the first limiting step 530 is formed therebetween. A first limiting boss 521 is disposed on the inner pin plate 520, and the first limiting boss 521 is located at the right side of the first limiting step 530. The bridge member 400 includes a first bridge plate 410, the first bridge plate 410 is connected to the inner pin plate 520, a plurality of positioning portions 411 are formed by bending a left end of the first bridge plate 410 downward, the plurality of positioning portions 411 are spaced apart from each other in the front-rear direction, a positioning groove 412 is formed in the first bridge plate 410, and the positioning groove 412 is located on the right side of the positioning portion 411. When the bridge 400 is connected to the first function pin 500, the locking portion 411 is located at the left side of the first limiting step 530 and abuts against the first limiting step 530, and the first limiting protrusion 521 is embedded in the locking groove 412 to limit the positions of the first function pin 500 and the bridge 400. In this embodiment, the first limiting protrusion 521 is higher than the upper surface of the first bridging plate 410, and the height of the first limiting protrusion 521 may be designed to be 0.3mm; after the first limiting boss 521 is embedded in the clamping groove 412, the first limiting boss 521 abuts against and limits the whole side face of the clamping groove 412, so that the connection is more stable.
In this embodiment, the chip 200 is fixed on the die attach pad 300, the bridge 400 is fixedly connected to the chip 200 and the first functional pin 500, and the chip 200, the die attach pad 300, the bridge 400 and the first functional pin 500 are encapsulated by the encapsulation layer 100, so that a part of the first functional pin 500 is exposed out of the encapsulation layer 100, thereby forming the semiconductor package device. When the bridge 400 is fixed to the first function pin 500, one end (left end) of the first function pin 500 has a first limit step 530, and the bridge 400 abuts against the left side of the first limit step 530 through the plurality of left-side catching portions 411, so that the left side of the first function pin 500 is limited and the first function pin 500 does not move to the left side; a clamping groove 412 is formed in the bridge 400, the clamping groove 412 is located at the right side of the clamping portion 411, and is not far away from the clamping portion 411, a first limiting boss 521 is disposed on the first function pin 500, and the first limiting boss 521 is embedded in the clamping groove 412 for limiting, so that the first function pin 500 does not move to the right side; through the structure, the fixed connection of the bridging piece 400, the first functional pins 500 and the chip 200 is realized, when the high-temperature reflow soldering process is impacted by wind force of a reflow oven, a triangular fixing function is formed between two of the clamping portions 411 and the first limiting boss 521, the bridging piece 400 and the first functional pins 500 can still be firmly connected, the problem that the products are poor due to deviation caused by external force on the bridging piece 400 is avoided, the packaging yield of the products is improved, and the yield is improved.
As shown in fig. 2 and 3, the detent groove 412 of the present embodiment is located on one side of a position between adjacent detent portions 411 of the plurality of detent portions 411. Taking two positioning portions 411 as an example, two positioning portions 411 are arranged at intervals in the front-back direction, and a positioning groove 412 is arranged between the two positioning portions 411 and near the right, so that the two positioning portions 411 in the front-back direction are connected with a first positioning step 530 for positioning, and a first positioning boss 521 on the right is embedded in the positioning groove 412 for positioning, so that a triangular positioning is formed between the two left positioning points and one right positioning point, and the bridge 400 and the first functional pin 500 are connected in a stable and fixed manner.
As shown in fig. 2, the catching groove 412 of the present embodiment extends to the edge of the bridge 400 in the first direction and forms a notch 413; the notch 413 is formed in the left edge of the first bridge plate 410, so that the bridge can be conveniently inserted into the first limiting boss 521 leftwards along the clamping groove 412, the bridge can be conveniently installed and butted with the first function pin 500, the notch 413 of the clamping groove 412 is tapered, the bridge can be guided when moving, and under the condition that the bridge is slightly offset in the installation process, the bridge can be aligned with the first limiting boss 521 through the guide of the tapered notch 413.
As shown in fig. 1 and 6, a side (lower surface) of bridge 400 facing chip 200 in this embodiment is provided with a first dotted portion 420, and a side (upper surface) of bridge 400 facing away from chip 200 is provided with a second dotted portion 430. The first dotted portion 420 and the second dotted portion 430 are in the form of concave points or convex points, the first dotted portion 420 may be distributed on the lower surface of the whole bridge 400, or may be distributed on a partial area of the bridge 400, and the second dotted portion 430 may be distributed on the upper surface of the whole bridge 400, or may be distributed on a partial area of the upper surface of the bridge 400. Since the bridge 400 is fixedly connected with the upper surface of the chip 200 and the upper surface of the first functional pin 500 through the adhesive sheet 210, the adhesive sheet 210 can be filled between the surface of the bridge 400 and the surface of the chip 200 by using the first divot part 420, the adhesive sheet 210 can be filled between the surface of the bridge 400 and the surface of the first functional pin 500, and the adhesive sheet 210 covers the surface of the first divot part 420, so that the bonding area of the bridge 400 and the adhesive sheet 210 is increased; similarly, the upper surface of the bridge 400 is fixedly connected to the package layer 100, and the second dotted portion 430 increases the contact area between the bridge 400 and the package material of the package layer 100, thereby improving the reliability of the product.
As shown in fig. 1 and 6, the first dotted portion 420 and the second dotted portion 430 of the present embodiment are arranged in a staggered manner. Through the staggered design of the pits on the upper surface and the lower surface, the bridge piece 400 is not thinned at the pit position, the structural stability of the bridge piece 400 is ensured, the bonding area of the bridge piece 400, the sheet adhesive 210 and the packaging material is increased, and the product reliability is improved.
As shown in fig. 1 and fig. 6, the bridge 400 of the present embodiment further includes: the bump straight portion 440, the first electrical connection portion 450, the space-saving bump 460, and the second electrical connection portion 470. The convex flat portion 440 is located on the right side of the snap portion 411 and connected to the left side of the first bridging plate 410, the right side of the first bridging plate 410 is bent upward to form the convex flat portion 440, the convex flat portion 440 extends along the right side, and a surface (upper surface) of the convex flat portion 440 departing from the chip 200 is a plane, i.e., the second pits 430 are not disposed on the upper surface. The upper surface of the raised flat portion 440 is a smooth structure, so that the external die bonder can be sucked by the suction nozzle through the vacuum suction and the upper surface of the raised flat portion 440 during the die bonding process, and the smooth surface can firmly suck the bridge member 400 without vacuum leakage. The bridge member 400 is stably moved in the production process, which is beneficial to the automatic production of conductor devices.
As shown in fig. 1 and 6, the first electrical connection portion 450 is connected to a side of the raised flat portion 440 away from the positioning portion 411, and is formed by bending the right side of the raised flat portion 440 downward, and the adhesive sheet 210 is provided between the lower surface of the first electrical connection portion 450 and the upper surface of the chip 200, so as to fixedly connect the chip 200. The right end of the first electrical connection portion 450 is bent upward to form a space-avoiding protrusion 460, and the space-avoiding protrusion 460 is located above the chip 200 and spaced apart from the chip 200. The right end of the dummy projection 460 is bent downward to form a second electrical connection portion 470, and an adhesive sheet 210 is disposed between the lower surface of the second electrical connection portion 470 and the upper surface of the chip 200, so as to fixedly connect the chip 200. The second electrical connection portion 470 is spaced apart from the first electrical connection portion 450, and forms a package space below the space-saving protrusion 460, and the package space is filled with a package material, so that the bridge is stably fixed in the package layer 100. The upper surface of the clearance boss 460 is penetrated with a glue fixing hole 461, and the glue fixing hole 461 is communicated with the packaging space, so that the packaging material can smoothly flow into the packaging space, and the situation of forming a packaging fault in the packaging space is avoided. And the sealing material is solidified in the glue fixing hole 461 to form a part of the packaging layer 100, so that the bridge 400 is limited and fixed, and the bridge 400 and the chip 200 are not easy to loosen in the packaging layer 100.
As shown in fig. 1, 3 and 4, a card-limit groove 310 is disposed on the upper surface of the die pad 300 in this embodiment, and the card-limit groove 310 is used for accommodating the chip 200. In the specific structure, an inward-concave clamping position is formed by recessing the middle position of the bonding pad base island 300, and when the chip 200 is installed, the installation position of the chip 200 can be determined, so that the chip 200 can be conveniently aligned when being installed. The recessed depth of the card-limiting groove 310 is 1/2 of the height of the chip 200, so that the upper surface of the chip 200 can protrude above the upper surface of the die pad 300 while the chip 200 is aligned, and the chip 200 has a sufficient height to abut against the bridge 400. The depth of the card-limiting groove 310 in this embodiment is 50 μm.
As shown in fig. 3, 4 and 5, the side walls of the left and right sides of the card limit groove 310 in this embodiment are provided with a second limit boss 311 in a protruding manner, for example, the left side wall of the card limit groove 310 is provided with a second limit boss 311 in a protruding manner, the second limit boss 311 on the side extends towards the right, the second limit boss 311 faces the side surface of the chip 200, so that the chip 200 is located between the second limit bosses 311 on the left and right sides, thereby limiting the position of the chip 200 and realizing the positioning function of the chip 200. A snap gap 312 is formed between the second limit projection 311 and the bottom surface of the card limit groove 310, and the snap gap 312 is used for filling the adhesive sheet 210 of the adhesive chip 200. Before the chip 200 is connected to the die pad 300, the die pad 210 is filled in the card-defining groove 310, and the die pad 210 penetrates into the engaging gap 312 by the die pad pressure, thereby accommodating the die pad 210. After the chip 200 is placed in the card-limiting groove 310, downward pressure is provided through the second limiting boss 311, so that the adhesive 210 can fully enter between the lower surface of the chip 200 and the bottom surface of the card-limiting groove 310 and fully fill between the side surface of the chip 200 and the second limiting boss 311, the adhesive 210 in the space between the chip 200 and the card-limiting groove 310 is full, poor layering between the adhesive 210 and the inner surface of the card-limiting groove 310 in the using process is prevented, and the product reliability is further improved.
As shown in fig. 5, an inclined surface 313 is provided at a connection portion between the engagement gap 312 and the bottom surface of the card-limiting groove 310, and the inclined surface 313 inclines downward along the outer side of the card-limiting groove 310, so that the adhesive 210 can flow along the inclined surface 313, thereby filling the adhesive 210 in the engagement gap 312 fully, increasing the connection stability of the chip 200, and after the adhesive 210 is cured, the engagement gap 312 is not easily removed, thereby realizing stable engagement.
As shown in fig. 1 and 4, the bottom surface of the card-limiting groove 310 in this embodiment is provided with a guiding groove 320, and the guiding groove 320 extends along the second direction and is used for filling the adhesive 210 of the adhesive chip 200. The adhesive 210 between the chip 200 and the adhesive base island 300 is sufficient through the diversion trench 320, and the thickness of the adhesive 210 (silver colloid, solder, sintered silver, solder paste, etc.) is increased; the gas in the clamping groove 310 is shunted in the process of filling the sticking agent 210, so that the gas can be discharged from two ends, and the situation of hollow filling of the sticking agent 210 is avoided; the bonding surface of the sticker sheet 210 and the sticker base island 300 is increased, so that the bonding force is increased, and the bonding stability is stronger.
As shown in fig. 1 and 4, in the specific structure, the second limiting step 330 is disposed at the left edge of the lower surface of the die attach base island 300 in this embodiment, the second limiting step 330 is formed on the left side of the lower surface of the die attach base island 300 by etching or punch forming, a gap formed between the second limiting step 330 and the first function pin 500 is used for filling the encapsulant to form the encapsulant layer 100, and the encapsulant layer 100 is formed after the encapsulant material is filled on the second limiting step 330, so that the lower surface of the encapsulant layer 100 is flush with the lower surface of the first function pin 500 and the lower surface of the die attach base island 300, and the encapsulant layer 100 filled on the second limiting step 330 serves as a position for positioning the lower surface of the die attach base island 300, thereby enhancing the bonding performance between the encapsulant layer 100 and the die attach base island 300, and making the die attach base island 300 difficult to separate from the encapsulant layer 100.
As shown in fig. 1 and fig. 2, in the present embodiment, a second function pin 600 is disposed at one end (right end) of the die attach pad 300 that is away from the first function pin 500 in the first direction, the second function pins 600 may be disposed in multiple numbers and all located at the right end of the die attach pad 300, and the multiple second function pins 600 are disposed side by side at intervals in the second direction (front-back direction). Waterproof portions 340 are formed on the upper surface of the adhesive sheet base 300, the waterproof portions 340 extend along a second direction (front-back direction), and the waterproof portions 340 are located between the chip 200 and the second functional pins 600. As shown in fig. 1 and 7, the waterproof portion 340 may be designed in a groove or/and protruding strip structure, the waterproof portion 340 is covered by the encapsulation layer 100, so that one or more step surfaces are formed between the encapsulation layer 100 and the waterproof portion 340, and when water vapor enters the device from the bonding surface between the second functional pin 600 and the encapsulation layer 100, the water vapor is blocked by the step surfaces formed by the waterproof portion 340, so that the water vapor is effectively prevented from penetrating from the bonding surface between the second functional pin 600 and the encapsulation material, and the product reliability is improved.
As shown in fig. 1 and fig. 2, the semiconductor package device in this embodiment further includes a third functional lead 700, the third functional lead 700 is disposed at a distance from the first functional lead 500 and the die attach pad 300, and is fixedly connected to the package layer 100 by a package, and the third functional lead 700 is connected to the chip 200 by a lead 710. The first functional pin 500 in this embodiment may be an S-pole, the second functional pin 600 may be a D-pole, and the third functional pin 700 may be a G-pole.
Based on the same concept, the present application also proposes a manufacturing method of a semiconductor package device for manufacturing and producing the semiconductor package device as described above, the method comprising the steps of:
and S100, scribing the wafer to form a chip, and adhering the chip to the bonding pad base island through the bonding pad.
And S200, fixing the chip and the bonding pad base island through reflow soldering, wherein the welding material is heated and soldered in a vacuum reflow oven through a plurality of temperature zones with different preset temperatures to obtain a product.
In the specific process, the bonded chip and the bonding pad substrate are placed in a vacuum reflow furnace, the reflow soldering temperature is sequentially divided into different temperature zones according to the time sequence, the temperature of 7 temperature zones (soldering temperature zones) is respectively set to be 140 ℃, 180 ℃, 220 ℃, 260 ℃, 360 ℃, 370 ℃ and 300 ℃, the temperature of the former soldering temperature zones is gradually increased and increased to be 360-370 ℃, so that the soldering material (solder paste) is in a molten state at high temperature, and the 7 different temperature zones are adopted for soldering, so that the solder paste can better wet the surface of the soldering position of the bonding pad substrate and the bottom surface of the chip. Meanwhile, in the high-temperature reflow soldering process of 360-370 ℃, because the furnace body is vacuum, the gas in the furnace is extracted by vacuum when the soldering material (solder paste) is in a high-temperature melting state, so that bubbles in the soldering material (solder paste) can be extracted, a compact soldering layer is formed between the bottom of the chip and the surface of the bonding pad base island after the product is solidified, the formation of an internal cavity is reduced, and the heat dissipation performance of the product is improved.
And step S300, cleaning the welded product, wherein organic matters of the product subjected to reflow soldering are removed through chemical cleaning, and a soldering area of a lead on the product is processed through plasma cleaning.
In the specific process, a two-section cleaning mode is adopted in the cleaning process: in the first step, chemical cleaning is adopted, and the chemical cleaning is mainly used for removing organic matters from the products after reflow soldering. And putting the product subjected to high-temperature welding on a placing rack of a cleaning tank, and sequentially performing a first-layer soaking, a first-layer ultrasonic oscillation cleaning, a second-layer soaking, a second-layer ultrasonic oscillation cleaning, a third-layer soaking and a cooling process to finish the chemical cleaning process. Wherein, the first layer and the second layer need to be added with proper amount of chemical cleaning agent. The purpose is as follows: organic matters adhered to the surface of the product and organic matters volatilized from welding materials in the welding process are accelerated to be softened and fall off in the soaking process of the product; in the first-layer ultrasonic oscillation cleaning and the second-layer ultrasonic oscillation cleaning of the product after the first-layer soaking and the second-layer soaking, the ultrasonic waves generate oscillation to generate heat so that organic matter residues on the surface fall off. And finally, soaking, washing and cooling by using distilled water for three layers. And finishing the cleaning process of the organic residue on the surface.
And a second step of adopting plasma cleaning: the plasma cleaning is mainly carried out before the lead welding, and the weldability of a welding area is enhanced. In the cleaning process, a product to be welded is placed in the cleaning cavity, and the mixed action of argon and nitrogen in the cavity is controlled, so that the mixed ions of argon and nitrogen clean the welding surface under the conditions of cavity pressure (30-150 Pa), radio frequency power (220-460 watt) and radio frequency time (5-30 sec), and the weldability of a welding area is improved.
And S400, carrying out lead welding on the cleaned product.
For example: the third functional pin is connected to the chip by a bonding wire.
And S500, carrying out plastic package, curing, matte oxide removal and baking forming on the product with the lead welded to form a packaging layer.
And step S600, separating, testing and packaging the product with the packaging layer.
In summary, the semiconductor package device and the manufacturing method thereof provided by the present application achieve the fixed connection between the bridging element and the first functional pin as well as the chip, when the high temperature reflow soldering process is impacted by the wind force of the reflow oven, two of the plurality of clamping portions and the first limiting boss form a triangular fixing function, so that the bridging element and the first functional pin can still be firmly connected, the problem of poor product caused by deviation of the bridging element due to external force is avoided, the package yield of the product is improved, and the yield is improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A semiconductor package device comprising a package layer, a chip disposed in the package layer, the semiconductor package device further comprising:
the chip bonding base island is fixedly connected with the chip;
the first functional pin and the bonding pad base island are arranged at intervals in a first direction;
the bridge is fixedly connected with the chip and the first functional pin;
the first functional pin is provided with a first limiting step arranged at one end in a first direction, and the first functional pin is provided with a first limiting boss;
the bridge is provided with a plurality of clamping parts which are arranged at one end and are arranged at intervals along a second direction, and the bridge is provided with a clamping groove, wherein the first direction is vertical to the second direction;
the clamping portion abuts against the first limiting step, and the first limiting boss is embedded in the clamping groove to limit the position of the first functional pin and the position of the bridging piece.
2. The semiconductor package device of claim 1, wherein the first limiting projection is located on a side of the first limiting step facing the chip, and the locking groove is located on a side of the locking portion facing the chip;
the screens groove is located a plurality of one side of position between the screens portion that is adjacent in the screens portion.
3. The semiconductor package device of claim 2, wherein the detent groove extends to an edge of the bridge in the first direction and forms a notch;
the notch is tapered.
4. The semiconductor package device of claim 1, wherein a side of the bridge toward the chip is provided with a first divot portion, and a side of the bridge away from the chip is provided with a second divot portion.
5. The semiconductor package device of claim 4, wherein the first divot portion and the second divot portion are disposed in a staggered manner.
6. The semiconductor package device of claim 1, wherein a second function pin is disposed on an end of the adhesive sheet base that is away from the first function pin in the first direction, a waterproof portion is disposed on the adhesive sheet base, the waterproof portion extends in the second direction, and the waterproof portion is located between the chip and the second function pin.
7. The semiconductor package device of claim 1, wherein a die-bonding pad is disposed on the die-bonding pad, the die-bonding pad being configured to receive the chip;
a second limiting boss is convexly arranged on the side wall of the clamping limit groove and is over against the side face of the chip so as to limit the position of the chip;
an occlusion gap is formed between the second limiting boss and the bottom surface of the clamping limiting groove, and the occlusion gap is used for filling a bonding agent for bonding the chip;
and the bottom surface of the clamping limit groove is provided with a flow guide groove, and the flow guide groove extends along the second direction and is used for filling and bonding the bonding agent of the chip.
8. The semiconductor packaging device of claim 7, wherein a second limiting step is arranged at an edge of one side of the die pad substrate, which is away from the chip, and the second limiting step is used for filling the packaging layer.
9. The semiconductor package device of any one of claims 1-8, wherein the bridge member further comprises:
the convex straight part is positioned on one side of the clamping part and extends along a first direction, and the surface of the convex straight part departing from the chip is a plane;
the first electric connection part is connected to one side, away from the clamping part, of the raised flat part and is used for connecting the chip;
the clearance convex part is arranged at intervals with the chip, and one end of the clearance convex part is connected with the first electric connection part;
and the second electric connection part is connected to the other end of the clearance protrusion part and is used for connecting the chip, and the second electric connection part and the first electric connection part are arranged at intervals.
10. A method of manufacturing a semiconductor package device, for producing a semiconductor package device according to any one of claims 1 to 9, the method comprising the steps of:
scribing the wafer to form a chip, and adhering the chip to the chip-adhering base island through the wafer-adhering piece;
fixing the chip and the bonding pad base island by reflow soldering, wherein a product is obtained by heating and soldering a soldering material in a vacuum reflow furnace through a plurality of temperature zones with different preset temperatures;
cleaning the welded product, wherein organic matters of the product after reflow soldering are removed through chemical cleaning, and a soldering area of a lead on the product is processed through plasma cleaning;
welding a lead of the cleaned product;
and carrying out plastic package, curing, sub-light oxide removal and baking on the product with the lead welded so as to form a packaging layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014197634A (en) * | 2013-03-29 | 2014-10-16 | 新電元工業株式会社 | Lead frame, semiconductor device, and manufacturing method of the same |
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| KR101862705B1 (en) * | 2017-09-29 | 2018-05-30 | 제엠제코(주) | Clip and leadframe for semiconductor package with finely engraved patterns and the semiconductor package having the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102006060484B4 (en) * | 2006-12-19 | 2012-03-08 | Infineon Technologies Ag | Semiconductor device with a semiconductor chip and method for producing the same |
| US8519525B2 (en) * | 2010-07-29 | 2013-08-27 | Alpha & Omega Semiconductor, Inc. | Semiconductor encapsulation and method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014197634A (en) * | 2013-03-29 | 2014-10-16 | 新電元工業株式会社 | Lead frame, semiconductor device, and manufacturing method of the same |
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| KR101862705B1 (en) * | 2017-09-29 | 2018-05-30 | 제엠제코(주) | Clip and leadframe for semiconductor package with finely engraved patterns and the semiconductor package having the same |
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