CN115328432A - Audio format conversion device - Google Patents
Audio format conversion device Download PDFInfo
- Publication number
- CN115328432A CN115328432A CN202210883921.1A CN202210883921A CN115328432A CN 115328432 A CN115328432 A CN 115328432A CN 202210883921 A CN202210883921 A CN 202210883921A CN 115328432 A CN115328432 A CN 115328432A
- Authority
- CN
- China
- Prior art keywords
- audio
- data
- format
- module
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/16—Sound input; Sound output
- G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention provides an audio format conversion device based on a field programmable gate array, which comprises a clock management module, a first conversion module and a second conversion module, wherein the clock management module is used for providing one or more clock signals; the device comprises: the device comprises a data processing module, and a serial-parallel conversion module, a storage unit operation module and a parallel-serial conversion module which are electrically connected with the data processing module. The device provided by the invention can convert the audio data in the HDAudio format into the audio data in the I2S format.
Description
Technical Field
The invention relates to an audio format conversion technology, in particular to an audio format conversion device based on a Field Programmable Gate Array (FPGA).
Background
The HD Audio (High Definition Audio) is a new-generation Audio specification which is promoted by the combination of Intel and Dolby companies, and has the characteristics of large data transmission bandwidth, high Audio playback precision, support for multi-channel array microphone Audio input, lower occupancy rate of a CPU (Central processing Unit), universal use of a bottom layer driver and the like. HD Audio has been introduced, the advantages are obvious, and the development potential is huge. The HD Audio specification is widely used in many CPUs, however, HD Audio decoders are currently held only by REALTEK corporation and there is a risk of a product outage in the domestic market.
An Inter-IC Sound (I2S) bus is a bus standard established by philips for audio data transmission between digital audio devices, and is also a widely used audio standard. Meanwhile, the existing I2S decoder in the market is mature in technology, and a plurality of manufacturers exist.
However, no apparatus or method for converting Audio data in HD Audio format into Audio data in I2S format exists in the market at present. Therefore, a technology for converting the Audio data in the HD Audio format into the Audio data in the I2S format is urgently needed to be developed by those skilled in the art, so that the risk of goods outage of the real decoder can be solved, and the normal use of the Audio data in the HD Audio format can be ensured.
Disclosure of Invention
In order to solve the defect that the Audio data in the HD Audio format cannot be converted into the Audio data in the I2S format, the invention provides an Audio format conversion device based on a field programmable gate array, and aims to provide a device which can convert the Audio data in the HD Audio format into the Audio data in the I2S format on the field programmable gate array of any model, so that the normal use of the Audio in the HD Audio format is ensured.
In order to achieve the purpose, the invention adopts a technical scheme that: an audio format conversion device based on a field programmable gate array, the device comprising a clock management module for providing one or more clock signals; the device converts the Audio data in the HD Audio format into the Audio data in the I2S format according to the clock signal; the device comprises: the device comprises a data processing module, and a serial-parallel conversion module, a storage unit operation module and a parallel-serial conversion module which are electrically connected with the data processing module; the data processing module collects the Audio data in the HD Audio format, and the parallel-serial conversion module outputs the Audio data in the I2S format obtained by conversion of the device.
In a preferred embodiment, said data processing module and said clock management module receive an Audio clock signal for said HD Audio formatted Audio data; the clock management module generates the clock signal according to the audio clock signal.
In a preferred embodiment, the clock signal comprises at least a second clock signal having a frequency 2 times the audio clock signal; the data processing module collects the Audio data in the HD Audio format and comprises the following steps: and the data processing module acquires the Audio data in the HD Audio format on the rising edge and the falling edge of the Audio clock signal or on the rising edge of the second clock signal.
In a preferred embodiment, the device for converting the Audio data in the HD Audio format into the Audio data in the I2S format according to the clock signal includes: the serial-parallel conversion module receives the Audio data in the HD Audio format, executes serial-parallel conversion, and returns parallel Audio data obtained by conversion to the data processing module; the data processing module identifies left channel data and right channel data in the parallel audio data and sets a sound channel marking bit; the apparatus stores the left channel data and/or the right channel data, and outputs the audio data of the I2S format.
In a preferred embodiment, the apparatus storing the left channel data and/or the right channel data comprises: the storage unit operation module receives the left channel data and/or the right channel data through the serial-parallel conversion module, and respectively stores the left channel data and/or the right channel data according to the channel mark bit and the audio clock signal or the second clock signal.
In a preferred embodiment, the clock signals include an output audio clock and a channel switching clock; the outputting the I2S formatted audio data includes: the storage unit operation module reads the left channel data and/or the right channel data according to the sound channel switching clock and transmits the left channel data and/or the right channel data to the parallel-serial conversion module; and the parallel-serial conversion module is used for converting the left channel data and/or the right channel data in parallel-serial mode according to the output audio clock and outputting the audio data in the I2S format.
In a preferred embodiment, the memory unit operation module is electrically connected with at least one memory, and the memory can be a memory unit inside the device or any device with a memory function which can be externally connected with the device.
In a preferred embodiment, the memory includes at least 2 FIFO memories, and the 2 FIFO memories store the left channel data and the right channel data, respectively.
In a preferred embodiment, the data processing module further receives a frame synchronization clock signal, the frame synchronization signal for identifying and synchronizing the instructions and the audio data; the performing a serial-to-parallel conversion includes: a serial-to-parallel conversion is performed at each falling edge of the synchronous clock signal.
Compared with the prior art, the invention has the advantages that: (1) The output limit that the HD Audio format Audio can only be realized by the REALTEK decoder is broken; (2) The conversion of the audio data is realized based on the field programmable gate array of any model, the technical scheme is flexible to realize, does not depend on hardware equipment, namely, the chip has more selectivity and the price is lower; (3) The left channel data and the right channel data of the Audio in the HD Audio format are respectively processed, so that the integrity of the Audio data is ensured; (4) The audio output mode is flexible, and the audio can be output by double channels or single channel; (5) And the audio data in the I2S format is output, so that the time sequence error caused by sampling can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1: the invention provides an overall structure schematic diagram of an audio format conversion device based on a field programmable gate array.
FIG. 2: another embodiment of the present invention provides a schematic diagram of an overall structure of an audio format conversion apparatus based on a field programmable gate array.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As used herein, the words "upper", "lower", "left", "right", and the like are used for convenience in description and not by way of limitation.
Herein, "first" and "second" are terms divided for the names of the components used herein in the same relation, and the present invention is not limited to the order described herein.
Herein, "at least one" means one, two, three, four, five, six, seven, eight or more.
Herein, "plurality" means two(s), three(s), four(s), five(s), six(s), seven(s), eight(s) or more(s).
In this context, "field programmable gate array" or other similar term includes any form of programmable logic device. It should be understood that as computer technology and electronic technology evolves, any chip used for logic function design, digital circuit design, no matter how its model, size, structure, component elements, materials, performance, etc. changes or updates, should be included in the scope of field programmable gate array.
As used herein, the terms "comprising," "including," "containing," and "having" are open-ended and do not exclude additional unrecited elements, steps, or components. The expression "consisting of 8230comprises" excludes any element, step or ingredient not specified. The phrase "consisting essentially of 8230comprises elements, steps or components that are limited in scope to the elements, steps or components specified, plus optional elements, steps or components that do not materially affect the basic and novel characteristics of the claimed subject matter. It should be understood that the term "comprising" encompasses the terms "consisting essentially of 8230; and" consisting of 8230.
The invention provides an audio format conversion device based on a field programmable gate array, which comprises a clock management module, a first audio conversion module and a second audio conversion module, wherein the clock management module is used for providing one or more clock signals; the device converts the Audio data in the HD Audio format into the Audio data in the I2S format according to the clock signal; the device comprises: the data processing module, and a serial-parallel conversion module, a storage unit operation module and a parallel-serial conversion module which are connected with the data processing module through circuits; the data processing module collects Audio data in HD Audio format, and the parallel-serial conversion module outputs Audio data in I2S format obtained by device conversion.
The audio format conversion device provided by the invention can use Field Programmable Gate Arrays (FPGA) of any type on a hardware circuit. Specifically, the Audio format conversion apparatus may include one or more general-purpose input or output pins or other interfaces for communication, which may be electrically connected with an interface for Audio data in HD Audio format, which may be output by any type of processor (CPU) or any other electronic device having such a function, with the level standard being guaranteed to be in conformity.
It should be understood that, without limiting the present invention, the audio data in the I2S format referred to in the following embodiments may be data of any number of bits (hereinafter referred to as "sampling bit number"), such as 16 bits, 32 bits, and the like, which are commonly used.
It should be understood that, without limiting the invention, the sampling frequency for the I2S format audio data may be set to 8K to 48K Hz or other non-standard frequencies (hereinafter referred to as "sampling frequency"), but in general, the higher the sampling frequency, the better the output audio quality; and for audio data in I2S format, the maximum sampling frequency that the decoder can support is 48K Hz. Therefore, for I2S formatted audio data, its best output audio quality can be achieved using a sampling frequency of 48K Hz. The audio data obtained by the audio format conversion device according to the present invention can be applied to audio data in the I2S format with a sampling frequency of 48 khz.
It should be understood that the Audio format conversion apparatus provided by the present invention may be electrically connected to any apparatus capable of generating Audio data in HD Audio format to receive the Audio data in HD Audio format and convert it into Audio data in I2S format for output. For convenience of explanation, and not as a limitation to the present invention, a processor (CPU) is taken as an example of an Audio data generating device in HD Audio format in the following embodiments.
An embodiment of the present invention provides an audio format conversion apparatus based on a field programmable gate array, as shown in fig. 1.
As shown in fig. 1, the field programmable gate array based audio format conversion apparatus includes a clock management module for providing one or more clock signals. The Audio format conversion device converts the Audio data in HD Audio format into Audio data in I2S format according to the clock signal.
Specifically, the audio format conversion device comprises a data processing module, and a serial-parallel conversion module, a storage unit operation module and a parallel-serial conversion module which are electrically connected with the data processing module. The data processing module collects Audio data in HD Audio format, and the parallel-serial conversion module outputs the converted Audio data in I2S format.
Data processing module
The processor (CPU) may generate Audio data in HD Audio format that includes an Audio clock signal (BCLK), which in this embodiment has a frequency of 24 mhz. Alternatively, the Audio format conversion apparatus may be electrically connected to a processor (CPU) through a pin/interface to receive Audio data in HD Audio format and an Audio clock signal (BCLK) to complete format conversion. The original Audio data in HD Audio format is serial Audio data, and the processor (CPU) may transmit the Audio data to the Audio format conversion apparatus through a serial data interface (SDO). Alternatively, the Audio format conversion apparatus receives or samples the Audio data in the HD Audio format through the data processing block, and receives an Audio clock signal (BCLK).
In an alternative embodiment, the data processing block may sample the Audio data in HD Audio format on the rising and falling edges of the Audio clock signal (BCLK), as shown in fig. 1; to implement the timing constraints of a field programmable gate array, sampling may also be performed on the rising edge of the second clock signal (CLK 2), as shown in fig. 2.
Further, in other optional embodiments, the data processing module also receives a synchronous clock Signal (SYNC) of the processor (CPU), which is used for data transmission and processing integrity.
Further, the data processing module may receive the parallel audio data returned by the serial-to-parallel conversion module, and process and determine the parallel audio data, specifically, the data processing module determines a first parallel data converted at a falling edge of each synchronous clock Signal (SYNC), taking 32-bit data as an example, if the first parallel data is "00H, 07H, 06H, 00", the subsequent data is marked as audio data of a left channel; if the first parallel data is "00H, 07H, 06H, 01", the subsequent data is marked as audio data of the right channel. In other alternative embodiments, the data processing module may set the flag bit (LR) separately so that the serial-to-parallel conversion module and the memory cell operation module can recognize the left channel data and the right channel data, for example, set the flag bit (LR) to 1 if it is the left channel data currently; if it is the right channel data, the flag bit (LR) is set to 0.
Clock management module
The clock management module receives an Audio clock signal (BCLK) of the HD Audio format Audio data to generate one or more clock signals. Wherein, the field programmable gate array can also generate a system Clock (CLK) for the operation of the audio format conversion device; further, the clock management module may generate any required clock signal from the system Clock (CLK), such as a clock signal for I2S formatted audio data output; the system Clock (CLK) may be a clock generated by a crystal oscillator circuit, any commonly used frequency of which may be used in the present invention. The audio format conversion device may perform conversion operations including, but not limited to, sampling, receiving, transmitting, storing, reading audio data, and serial-to-parallel or parallel-to-serial converting the audio data according to the clock signal.
In this embodiment, the clock management module may generate a plurality of clock signals including at least a second clock signal (CLK 2). The second clock signal (CLK 2) may be generated from the audio clock signal (BCLK) at a frequency 2 times the audio clock signal (BCLK).
Further, in other alternative embodiments, the audio format conversion device ensures alignment of the data by a synchronization clock Signal (SYNC) issued by the processor (CPU) that serves as a frame synchronization signal for identifying and synchronizing command words, data streams, etc. The data processing module samples the Audio data in the HD Audio format at the falling edge of a synchronous clock Signal (SYNC); because the Audio data in the HD Audio format is serial data, the integrity of Audio data sampling can be ensured using a synchronous clock Signal (SYNC).
Still further, in other alternative embodiments, the clock management module further generates an output audio clock (BCLK _ I2S) and a channel switching clock (LRCLK _ I2S), wherein the frequency of the channel switching clock (LRCLK _ I2S) is the same as the sampling frequency, according to the sampling frequency that an I2S decoder (i.e., a decoder for decoding audio data in I2S format, the following same applies) can support, the output audio clock (BCLK _ I2S) being 2 times the sampling frequency multiplied by the number of sampling bits (the sampling frequency is typically but not limited to 48 khz, and the number of sampling bits is typically but not limited to 16 or 32 bits).
Still further, in other optional embodiments, the clock management module further generates a master clock (MCLK _ I2S) for the I2S decoder to decode and output the I2S format audio data generated by the audio format conversion device. In the present embodiment, the frequency of the master clock (MCLK _ I2S) is 256 times the sampling frequency.
Serial-to-parallel conversion module
The serial-parallel conversion module receives the Audio data in the HD Audio format collected by the data processing module and converts the Audio data in the serial HD Audio format into parallel Audio data so that the data processing module can process and judge the parallel Audio data conveniently.
Memory cell operation module
The storage unit operation module receives the parallel audio data identified and processed by the data processing module through the serial-parallel conversion module, and stores and reads the parallel audio data. The storage unit operation module controls and manages the storage space to perform read-write operation on the parallel audio data.
In this embodiment, the memory space is stored using a FIFO memory, as shown in fig. 1 or 2. Specifically, the storage unit operation module stores left channel data and right channel data according to a flag bit (LR) and a clock signal, wherein the clock signal may be a clock signal according to which the data processing module receives or samples the Audio data in the HD Audio format, that is, an Audio clock signal (BCLK) or a second clock signal (CLK 2). In this embodiment, the storage space comprises at least 2 FIFO memories for storing left channel data and right channel data, respectively. Further, when the value (e.g., a value of 1) of the flag bit (LR) indicates left channel data, the memory cell operation block writes the audio data into the FIFO memory storing the left channel data; when the value (e.g., 0) of the flag bit (LR) indicates right channel data, the memory cell operation module writes the audio data into the FIFO memory storing the right channel data.
Further, in other alternative embodiments, the storage space may be an internal storage space of the audio format conversion apparatus and/or an external memory externally connected to the audio format conversion apparatus, and the storage unit operation module is configured to control reading and writing of the storage space.
In the present embodiment, the memory cell operation block performs a read operation according to the channel switching clock (LRCLK _ I2S) and the output audio clock (BCLK _ I2S). Specifically, when the channel switching clock (LRCLK _ I2S) is a left channel data signal (e.g., the signal is high), the memory cell operation module reads the memory storing the left channel data based on the output audio clock (BCLK _ I2S) and transmits to the parallel-to-serial conversion module; when the channel switching clock (LRCLK _ I2S) is the right channel data signal (e.g., the signal is low), the memory cell operation block reads the memory storing the right channel data based on the output audio clock (BCLK _ I2S) and transmits to the parallel-to-serial conversion block.
Further, in other optional embodiments, the storage unit operation module may determine whether to perform a read operation according to a current state of the memory, for example, when the memory state is non-empty, the storage unit operation module determines that the read operation is possible.
Parallel-serial conversion module
The parallel-serial conversion module is electrically connected with the storage unit operation module and can receive the parallel audio data read and transmitted by the storage unit operation module. Specifically, the parallel-to-serial conversion module may receive parallel audio data according to the output audio clock (BCLK _ I2S) and the channel switching clock (LRCLK _ I2S), and convert the audio data into I2S format audio data.
Further, the parallel-to-serial conversion module receives the left channel data and/or the right channel data according to the channel switching clock (LRCLK _ I2S), and converts the left channel data and the right channel data into audio data that is serial and recognizable by the I2S decoder, i.e., I2S format, according to the output audio clock (BCLK _ I2S).
Further, in other optional embodiments, the parallel-to-serial conversion module may output the I2S formatted audio data to the I2S decoder, and the I2S decoder performs decoding output according to the master clock (MCLK _ I2S), the output audio clock (BCLK _ I2S), and the channel switching clock (LRCLK _ I2S).
Still further, in other optional embodiments, the parallel-to-serial conversion module may select the left channel data and/or the right channel data to output according to actual needs.
The main modules/devices in the audio format conversion apparatus are described above, wherein there are multiple optional embodiments in each module/device, and it should be understood that each module/device can be combined with other modules/devices to form a complete audio format conversion apparatus, so as to achieve the technical effects of the present invention.
The audio format conversion apparatus based on the fpga provided by the present invention is introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the above description is only used to help understand the core idea of the present invention; while the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. An audio format conversion device based on a field programmable gate array, which is characterized by comprising a clock management module, a first conversion module and a second conversion module, wherein the clock management module is used for providing one or more clock signals; the device converts the Audio data in the HD Audio format into the Audio data in the I2S format according to the clock signal; the device comprises:
the device comprises a data processing module, and a serial-parallel conversion module, a storage unit operation module and a parallel-serial conversion module which are electrically connected with the data processing module;
the data processing module collects the Audio data in the HD Audio format, and the parallel-serial conversion module outputs the Audio data in the I2S format obtained by conversion of the device.
2. The apparatus of claim 1, wherein the data processing module and the clock management module receive an Audio clock signal for the Audio data in the HD Audio format; the clock management module generates the clock signal according to the audio clock signal.
3. The apparatus of claim 2, wherein the clock signal comprises at least a second clock signal having a frequency 2 times the audio clock signal; the data processing module collects the Audio data in the HD Audio format and comprises the following steps:
and the data processing module acquires the Audio data in the HD Audio format on the rising edge and the falling edge of the Audio clock signal or on the rising edge of the second clock signal.
4. The apparatus of claim 3, wherein the apparatus for converting the Audio data in HD Audio format into Audio data in I2S format according to the clock signal comprises:
the serial-parallel conversion module receives the Audio data in the HD Audio format, executes serial-parallel conversion, and returns parallel Audio data obtained by conversion to the data processing module;
the data processing module identifies left channel data and right channel data in the parallel audio data and sets a sound channel marking bit;
the apparatus stores the left channel data and/or the right channel data, and outputs the audio data in the I2S format.
5. The apparatus of claim 4, wherein the apparatus stores the left channel data and/or the right channel data comprises:
the storage unit operation module receives the left channel data and/or the right channel data through the serial-parallel conversion module, and respectively stores the left channel data and/or the right channel data according to the channel mark bit and the audio clock signal or the second clock signal.
6. The apparatus of claim 4, wherein the clock signal comprises an output audio clock and a channel switch clock; the outputting the I2S formatted audio data includes:
the storage unit operation module reads the left channel data and/or the right channel data according to the channel switching clock and transmits the left channel data and/or the right channel data to the parallel-serial conversion module;
and the parallel-serial conversion module is used for converting the left channel data and/or the right channel data in parallel-serial mode according to the output audio clock and outputting the audio data in the I2S format.
7. The apparatus of claim 5, wherein the storage unit operation module is electrically connected to at least one memory, and the memory can be a storage unit inside the apparatus or any device with storage function externally connected to the apparatus.
8. The apparatus of claim 7, wherein the memory comprises at least 2 FIFO memories, and wherein the 2 FIFO memories store the left channel data and the right channel data, respectively.
9. The apparatus of claims 4-8, wherein the data processing module further receives a frame synchronization clock signal, the frame synchronization signal identifying and synchronizing the command and the audio data; the performing a serial-to-parallel conversion includes: performing a serial-to-parallel conversion on a falling edge of each of the synchronous clock signals.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210883921.1A CN115328432A (en) | 2022-07-26 | 2022-07-26 | Audio format conversion device |
| PCT/CN2022/108274 WO2024020860A1 (en) | 2022-07-26 | 2022-07-27 | Audio format conversion apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210883921.1A CN115328432A (en) | 2022-07-26 | 2022-07-26 | Audio format conversion device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115328432A true CN115328432A (en) | 2022-11-11 |
Family
ID=83918892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210883921.1A Pending CN115328432A (en) | 2022-07-26 | 2022-07-26 | Audio format conversion device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115328432A (en) |
| WO (1) | WO2024020860A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9009032B2 (en) * | 2006-11-09 | 2015-04-14 | Broadcom Corporation | Method and system for performing sample rate conversion |
| US20080155230A1 (en) * | 2006-12-21 | 2008-06-26 | General Instrument Corporation | Method and System for Providing Simultaneous Transcoding of Multi-Media Data |
| CN101482856B (en) * | 2009-01-05 | 2010-07-14 | 东南大学 | Serial-parallel protocol conversion apparatus based on field programmable gate array |
| CN201449727U (en) * | 2009-01-20 | 2010-05-05 | 深圳市同洲电子股份有限公司 | Conversion device based on field programmable gate array |
| US9338394B2 (en) * | 2010-11-15 | 2016-05-10 | Cisco Technology, Inc. | System and method for providing enhanced audio in a video environment |
-
2022
- 2022-07-26 CN CN202210883921.1A patent/CN115328432A/en active Pending
- 2022-07-27 WO PCT/CN2022/108274 patent/WO2024020860A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024020860A1 (en) | 2024-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4048673A (en) | Cpu - i/o bus interface for a data processing system | |
| CN101178921B (en) | Method and system for processing audio signal | |
| JPH01241935A (en) | Synchronized formatter | |
| CN114817114A (en) | MIPI interface, control method, device and medium thereof | |
| CN112218020A (en) | Audio data transmission method and device for multi-channel platform | |
| CN102387369A (en) | Device for receiving signal and method for receiving clock signal | |
| TWI760880B (en) | Storage-device-associated transmission control circuit, data transmission system and method for operating a data transmission system | |
| CN116737624B (en) | High-performance data access device | |
| WO2024078089A1 (en) | Chip and data transmission method therefor | |
| CN115328432A (en) | Audio format conversion device | |
| JP2023547185A (en) | Serdes interface circuit | |
| CN115905067A (en) | Data transmission control method, chip, device and storage medium | |
| GB1581839A (en) | I/o bus transceiver for a data processing system | |
| JP2001298494A (en) | Controller and method for controlling interface with data link | |
| CN113806277B (en) | FPGA and DSP data transmission system based on SRIO protocol | |
| CN211791821U (en) | Satellite-borne video compression device for directly transmitting video data to ground | |
| US11169947B2 (en) | Data transmission system capable of transmitting a great amount of data | |
| US8775690B2 (en) | Control apparatus, switch, optical transmission apparatus, and control method | |
| CN111930176B (en) | Multi-path LVDS data processing device and method | |
| US7248663B2 (en) | Apparatus and method for transforming data transmission speed | |
| CN115437988A (en) | Synchronization method, device and application of I2S audio clock data | |
| CN112581809A (en) | Classroom all-in-one machine equipment | |
| CN116820867B (en) | Chip debugging method and device and chip | |
| CN112637602A (en) | JPEG interface and digital image processing system | |
| CN106791547B (en) | Portable HDMI video acquisition device and method based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |