WO2024078089A1

WO2024078089A1 - Chip and data transmission method therefor

Info

Publication number: WO2024078089A1
Application number: PCT/CN2023/108911
Authority: WO
Inventors: 刘明; 石昊明
Original assignee: 声龙(新加坡)私人有限公司
Priority date: 2022-10-09
Filing date: 2023-07-24
Publication date: 2024-04-18
Also published as: CN115292237A; CN115292237B

Abstract

The present text discloses a chip and a data transmission method therefor. The chip comprises an SPI protocol conversion module and a plurality of blocks. Blocks which are directly connected to the SPI protocol conversion module among the plurality of blocks are used as stage-1 blocks, blocks not directly connected to the SPI protocol conversion module are used as multi-stage blocks, and the SPI protocol conversion module is connected to each stage-1 block by means of a bus, and is connected to the multi-stage blocks stage by stage via the stage-1 blocks by means of the bus. The SPI protocol conversion module is configured to obtain communication information by means of communicating with an upper computer by means of an SPI protocol, convert a transmission protocol of the communication information into a bus protocol, and transmit the bus protocol to a corresponding block by means of the bus. The blocks are configured to parse the communication information and a required configuration parameter in the blocks after receiving the communication information, and perform a corresponding operation according to the parsing result.

Description

Chip and data transmission method thereof

cross reference

This disclosure claims the priority of the Chinese patent application filed with the China Patent Office on October 9, 2022, with application number 202211223804.9 and invention name “A chip and its data transmission method”, the content of which should be understood as incorporated into this disclosure by reference.

Technical Field

The embodiments of the present disclosure relate to, but are not limited to, the field of data processing technology, and in particular, to a chip and a data transmission method thereof.

Background technique

With the continuous development of semiconductor technology and the increasing demand for big data and computing, more and more computing and storage functions require dedicated chips to complete. For high-throughput chips with relatively simple computing functions but high parallel computing of data volume, SPI (Serial Peripheral Interface) is usually used to communicate with the main control system to transmit some configuration parameters, data and feedback chip status information.

The usual design will directly parse the parameters in the block where the SPI interface signal is located, and then distribute the parameters to each level of sub-blocks for use. As the number of computing units and storage units in the chip gradually increases, the number of blocks divided into chips also gradually increases. Transmitting from the block where the parameters are parsed to other blocks, especially blocks that are far away, needs to pass through multiple blocks. There are a large number of routing lines between blocks, which not only affects the cutting of the chip, but also brings huge pressure on the layout and wiring of each block.

SUMMARY OF THE INVENTION

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the present disclosure provides a chip, which may include an SPI interface protocol conversion module and a plurality of blocks divided therefrom; the blocks directly connected to the SPI interface protocol conversion module among the plurality of blocks are used as primary blocks, and the blocks not directly connected to the SPI interface protocol conversion module are used as multi-level blocks; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and through the bus, through the The first-level blocks corresponding to the multi-level blocks are connected to the multi-level blocks level by level;

The SPI interface protocol conversion module is configured to communicate with the host computer through the SPI interface protocol to obtain communication information, convert the transmission protocol of the communication information into a bus protocol, and transmit the communication information to the corresponding block through the bus based on the bus protocol;

The block is configured to parse the communication information and the required configuration parameters within the block itself after receiving the communication information, and perform corresponding operations according to the parsing results.

In an exemplary embodiment of the present disclosure, a register is provided in each of the blocks; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and is connected to the multi-level blocks step by step through the primary blocks corresponding to the multi-level blocks through the bus, which may include:

The SPI interface protocol conversion module is connected to the registers in all the first-level blocks through a bus, and is connected to the registers in the multi-level blocks subsequent to the first-level block step by step through the bus.

In an exemplary embodiment of the present disclosure, each of the blocks includes one or more functional units; parsing the communication information and the required configuration parameters within the block itself and performing corresponding operations according to the parsing results may include:

The communication information and the required configuration parameters are parsed in the register of the block itself according to the preset configuration parameters and data address table, and the parsing results are distributed to the functional units, which perform corresponding operations.

In an exemplary embodiment of the present disclosure, the communication information includes write data information, and the write data information may include: write enable, write address and write data; the register is a write register;

The bus may be configured to transmit the write data information.

In an exemplary embodiment of the present disclosure, the function unit performing the corresponding operation may include:

The functional unit writes the write data into the write address according to the write enable.

In an exemplary embodiment of the present disclosure, the communication information includes read data information, and the read data information may include: read enable and read address; the register is a read register;

The bus may be configured to transmit the read data information.

In the exemplary embodiment of the present disclosure, the functional unit performs the corresponding operation, which may To include:

The functional unit reads data from the read address according to the read enable to obtain read data;

Returning the read data to the read register;

The read register may be configured to transmit the read data to the SPI interface protocol conversion module via a bus.

In an exemplary embodiment of the present disclosure, the functional unit may include any one or more of the following: a cache control unit, a calculation unit, and a test unit.

In an exemplary embodiment of the present disclosure, the SPI interface protocol conversion module can also be configured to convert the transmission protocol of the information to be transmitted to the host computer from the bus protocol to the SPI interface protocol, and transmit the information to be transmitted to the host computer to the host computer according to the SPI interface protocol.

In an exemplary embodiment of the present disclosure, the number of levels of the multi-level blocks is positively correlated with the number of blocks required to be passed through to connect to the SPI interface protocol conversion module.

In an exemplary embodiment of the present disclosure, the SPI interface protocol conversion module is provided in a primary block, or is provided separately.

The embodiment of the present disclosure further provides a data transmission method based on the chip; the method may include:

Communicate with the host computer through the SPI interface protocol to obtain communication information, convert the transmission protocol of the communication information into a bus protocol, and transmit the communication information to the corresponding block in the chip through the bus based on the bus protocol;

The communication information and the required configuration parameters are parsed within the block itself, and corresponding operations are performed according to the parsing results.

Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

FIG1 is a schematic diagram of a chip connection structure according to an embodiment of the present disclosure;

FIG2 is a schematic diagram of a first chip connection in a related solution;

FIG3 is a schematic diagram of a second chip connection in a related solution;

FIG4 is a schematic diagram of an example of chip connection according to an embodiment of the present disclosure;

FIG5 is a flow chart of a data transmission method according to an embodiment of the present disclosure.

Details

The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and/or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

Furthermore, when describing representative embodiments, the specification may have presented a method and/or process as a particular sequence of steps. However, in the case where the method or process does not rely on the particular sequence of steps described herein, To the extent that the steps are described in a specific order, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and/or process should not be limited to performing their steps in the order written, and those skilled in the art can readily appreciate that these orders can be changed without departing from the scope of the present disclosure.

The present disclosure provides a chip 1, as shown in FIG1, which may include a SPI interface protocol conversion module 11 and a plurality of divided blocks 12; the blocks directly connected to the SPI interface protocol conversion module in the plurality of blocks 12 are taken as primary blocks 12-1, and the blocks not directly connected to the SPI interface protocol conversion module are taken as multi-level blocks 12-i (i is a positive integer greater than 1, for example, 2, 3, 4 ... N, N is a positive integer), and the number of levels i of the multi-level blocks is the same as the number of processes required for the multi-level blocks to be connected to the SPI interface protocol conversion module 11. The number of blocks is positively correlated (i.e., the more blocks any block passes through when connected to the SPI interface protocol conversion module, the greater the level of the block); the levels of the primary block 12-1 and the multi-level block 12-i are continuous (i.e., when there are multiple blocks, the levels of the multiple blocks are continuous, such as: primary block, secondary block, tertiary block, ...); the SPI interface protocol conversion module 11 is connected to each of the primary blocks 12-1 through bus a, and is connected to the multi-level block 12-i level by level through bus a through the primary block 12-1 corresponding to the multi-level block 12-i;

The SPI interface protocol conversion module 11 is configured to communicate with the host computer through the SPI interface protocol to obtain communication information, convert the transmission protocol of the communication information into a bus protocol, and transmit the communication information to the corresponding block 12 (for example, any primary block and multi-level block) through the bus based on the bus protocol;

The block 12 is configured to parse the communication information and the required configuration parameters within the block itself after receiving the communication information, and perform corresponding operations according to the parsing results.

Compared with the related art, the chip of the embodiment of the present disclosure may include an SPI interface protocol conversion module and a plurality of blocks divided therefrom; the blocks directly connected to the SPI interface protocol conversion module among the plurality of blocks are used as primary blocks, and the blocks not directly connected to the SPI interface protocol conversion module are used as multi-level blocks; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and is connected to the multi-level blocks step by step through the primary blocks corresponding to the multi-level blocks through the bus; the SPI interface protocol conversion module is configured to communicate with the host computer through the SPI interface protocol to obtain communication information, and the The transmission protocol of the communication information is converted into a bus protocol, and the communication information is transmitted to the corresponding block through the bus; the block is configured to parse the communication information and the required configuration parameters within the block itself after receiving the communication information, and perform corresponding operations according to the parsing results. Through this embodiment, the number of long lines is greatly reduced, and the wiring pressure is alleviated.

Spi (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that only requires four signal lines, saving pins and facilitating PCB (printed circuit board) layout. The communication principle of spi is relatively simple. It works in a master-slave mode, usually with one master device and multiple slave devices.

In a traditional related scheme, usually in FPGA (Field-Programmable Gate Array), spi parsing module A is connected to host computer B, and directly connected to other functional modules C (such as C1, C2, C3, ..., CM) in FPGA. As shown in Figure 2, spi parsing module A parses the parameters of other functional modules and the data to be transmitted, and transmits them to the corresponding functional modules C respectively. Generally, the M (M is a positive integer) functional modules in Figure 2 are all sub-modules of the same level.

In another traditional related scheme, in the chip, the spi analysis module A is connected to the host computer B and is directly connected to the first-level block in each group of blocks (such as Block0, Block1, Block2, ..., BlockX-1, X is a positive integer). The front-end design is based on the physical position relationship divided by the back-end design. The parameters and data signals transmitted from the spi analysis module A to the second-level block need to be routed through the first-level block, and the parameters and data signals entering the third-level block need to be routed through the first-level block and the second-level block. As shown in Figure 3, each level of the block in each group of blocks is connected to the first-level block step by step and then connected to the spi analysis module A. The spi analysis module A parses all the configuration parameters and data of each block according to the address allocation table, parses out a large number of register signals, and distributes them to the corresponding functional modules. Each level of the block in each group of blocks requires multiple routings to be connected to the spi analysis module A, and the wiring is complicated (not reflected in Figure 3). When the number of levels and groups of blocks is more, the routing between the spi analysis module A and the blocks is more and more, and the wiring is more and more complicated. As shown in Figure 3, multiple configuration parameters after SPI parsing need to go through a large number of routing lines to reach each level of block. In actual applications, there are as many as 50,000 routing lines. These configuration parameters intersect with the data read and write channels, which brings great trouble to the layout and wiring of the chip.

In an exemplary embodiment of the present disclosure, in order to solve the problem caused by a large number of cross-wires and long wires of the chip, the present disclosure proposes a method for parsing SPI configuration parameters separately within the block. The schematic diagram of the scheme structure is shown in Figure 1.

In an exemplary embodiment of the present disclosure, the host computer 2 transmits communication information to the chip 1 through the SPI protocol, and the SPI interface protocol conversion module 11 converts the SPI protocol, which can be converted into a bus protocol. The converted transmission protocol can be a transmission protocol set according to the interface signal and timing relationship of the write SRAM (static random access memory). The bus between the SPI interface protocol conversion module 11 and each block 12 can be used as a write configuration path bus, or can be set as a read configuration path bus, and the number of signal lines of this group of buses is limited.

In an exemplary embodiment of the present disclosure, as shown in FIG1 , the SPI interface protocol conversion module 11 is interconnected with the first-level block 12-1 in each group of blocks (such as Block0, Block1, Block2, ..., BlockK-1, K is a positive integer) through a bus, and the configuration bus passes through the first-level block 12-1 to reach the second-level block 12-2, and the configuration bus passes through the first-level block 12-1 and the second-level block 12-2 to reach the third-level block, or even more levels of blocks 12-N. The configuration parameters and data required by this block are parsed in the K blocks of each level.

In an exemplary embodiment of the present disclosure, as shown in FIG4 , each of the blocks 12 is provided with a register; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and is connected to the multi-level blocks step by step through the primary blocks corresponding to the multi-level blocks through the bus, and may include:

The SPI interface protocol conversion module 11 is connected to the registers in all the first-level blocks 12-1 through bus a, and is connected to the registers in the multi-level blocks 12-i subsequent to the first-level block 12-1 step by step through the bus a.

In an exemplary embodiment of the present disclosure, the registers in FIG. 4 are illustrated by taking write registers (e.g., spi_wr_reg1, spi_wr_reg2, spi_wr_reg3, spi_wr_reg4, spi_wr_reg5, spi_wr_reg6, spi_wr_reg7, spi_wr_reg8, spi_wr_reg9, spi_wr_reg10, spi_wr_reg11) as an example.

The block's own registers are parsed according to the preset configuration parameters and data address table. The communication information and the configuration parameters are analyzed, and the analysis results are distributed to the functional units, which perform corresponding operations.

In an exemplary embodiment of the present disclosure, registers (such as write registers and read registers) are distributed in each block, receive communication signals from the SPI interface protocol conversion module 11, and then parse the parameters of the block according to the designed configuration parameters and data address table, and distribute them to other functional units of the block.

In an exemplary embodiment of the present disclosure, the SPI interface protocol conversion module 11 is arranged in a primary block 12 - 1 , or is arranged independently of the multiple blocks 12 .

In an exemplary embodiment of the present disclosure, a chip may include a spi interface protocol conversion module 11 (spi_convert); the spi interface protocol conversion module 11 may be set in one of the multiple blocks 12; each block 12 in the chip may include but is not limited to: a spi write register spi_wr_reg, a cache control unit Mc, a calculation unit Alu (arithmetic and logic unit), and a test unit dft. Among them, Alu is a combinational logic circuit that can realize multiple groups of arithmetic operations and logic operations.

In an exemplary embodiment of the present disclosure, the SPI interface protocol conversion module 11 converts the SPI protocol for communicating with the host computer 2 outside the chip 1 into a bus protocol, and then interconnects with the block where the SPI interface protocol conversion module 11 is located and the registers inside other blocks. The registers in each block are connected to the functional units in the block. For the sake of clarity, this connection relationship is not shown in Figure 4.

In an exemplary embodiment of the present disclosure, the chip in FIG. 4 can be divided into 11 blocks, namely, block0, block1, block2, block3, block4, block5, block6, block7, block8, block9, and block10. The SPI interface protocol conversion module 11 can be arranged in block0, wherein block0 can be used as a primary block 12-1, and the SPI interface protocol conversion module 11 is directly connected to the register in block0 through a bus; block1, block3, and block5 can be used as secondary blocks 12-2, and the SPI interface protocol conversion module 11 is connected to the registers in block1, block3, and block5 in the secondary block 12-2 through bus a respectively through block0; block2, block4, block6, and block8 can be used as tertiary blocks, and after passing through block0, the SPI interface protocol conversion module 11 is connected to the registers in block2 through block1 through bus a, is connected to the registers in block4 through block3 through bus a, is connected to the registers in block6 and the registers in block8 through block5 through bus a respectively; block7, Block9 can be used as a four-level block. After passing through block0, the SPI interface protocol conversion module 11 is connected to the registers in block7 through block5 and block6 through bus a, and is connected to the registers in block9 through block5 and block8 through bus a; block10 can be used as a five-level block. After passing through block0, the SPI interface protocol conversion module 11 is connected to the registers in block10 through bus a through block5, block8, and block9.

In an exemplary embodiment of the present disclosure, registers (such as write registers and read registers) are distributed in each block, receive communication signals from the SPI interface protocol conversion module 11, and then parse the parameters of the block according to the designed configuration parameters and data address table, and distribute them to other functional modules of the block, such as the cache control unit Mc, the computing unit Alu, the test unit DFT, etc.

In an exemplary embodiment of the present disclosure, the cache control unit Mc needs a large number of configuration parameters and refresh parameters of the read and write DRAM (dynamic random access memory) when writing data. The configuration parameters and refresh parameters can be obtained by parsing the write register of the block where they are located. Mc(64) means that the block where they are located contains 64 cache control units Mc, and Mc(128) means that the block where they are located contains 128 cache control units Mc.

In the exemplary embodiment of the present disclosure, the computing unit Alu in the chip needs to configure many computing-related parameters and read the computing results and report them to the host computer when reading data. These parameters can be obtained by parsing the write register of the block. Alu (8) indicates that the block contains 8 computing units Alu.

In an exemplary embodiment of the present disclosure, the test unit DFT needs SPI to configure test parameters and read test results during testing. The test parameters can be obtained by parsing the write register of the block where the test unit DFT is located.

In an exemplary embodiment of the present disclosure, the communication information may include write data information, and the write data information may include: write enable (Wr_en), write address (Wr_addr) and write data (Wr_data); the register is a write register;

The bus may be configured to transmit the write data information.

In an exemplary embodiment of the present disclosure, the host computer 2 transmits communication information to the chip 1 through the SPI protocol, and the SPI interface protocol conversion module 11 converts the SPI protocol to a bus protocol. The bus between the SPI interface protocol conversion module 11 and each block 12 can be used as a write configuration path bus. The SPI interface protocol conversion module 11 is interconnected with the write register in the primary block 12-1 in each group of blocks (such as Block0, Block1, Block2, ..., BlockN-1) through the write configuration path bus. The write configuration path bus passes through the primary block 12-1 to reach the write register of the secondary block 12-2. The write configuration path bus passes through a The first-level block 12-1 and the second-level block 12-2 reach the write register of the third-level block 12-3, or even the write registers of the blocks of more levels. The configuration parameters and data required by the block are parsed in the write registers of the N blocks of each level.

In an exemplary embodiment of the present disclosure, the write register distributes the configuration parameters and data, write enable, write address and write data required by the block to the corresponding functional modules, such as the cache control unit Mc, the computing unit Alu, etc., and the cache control unit Mc and the computing unit Alu complete the data write operation according to the configuration parameters and data, write enable, write address and write data.

In an exemplary embodiment of the present disclosure, the communication information is read data information, and the read data information may include: read enable and read address; the register is a read register;

The bus may be configured to transmit the read data information.

In an exemplary embodiment of the present disclosure, the host computer 2 transmits communication information to the chip 1 through the SPI protocol, and the SPI interface protocol conversion module 11 converts the SPI protocol to a bus protocol. The bus between the SPI interface protocol conversion module 11 and each block 12 can be used as a read configuration path bus. The SPI interface protocol conversion module 11 is interconnected with the read register in the first-level block 12-1 in each group of blocks (such as Block0, Block1, Block2, ..., BlockN-1) through the read configuration path bus. The read configuration path bus passes through the first-level block 12-1 to reach the read register of the second-level block 12-2. The read configuration path bus passes through the first-level block 12-1 and the second-level block 12-2 to reach the read register of the third-level block 12-3, and even the read registers in more levels of blocks. The configuration parameters and data required for this block are parsed in the read registers in the N blocks of each level.

Returning the read data to the read register;

The read register may be configured to transmit the read data to the SPI interface protocol conversion module 11 via a bus.

In an exemplary embodiment of the present disclosure, the read register distributes the configuration parameters and data, read enable, and read address required by the block to the corresponding functional modules, such as the cache control unit Mc, the computing unit Alu, etc. The cache control unit Mc and the computing unit Alu complete the data reading operation according to the configuration parameters and data, read enable, and read address, and return the read data (i.e., read data) to the SPI interface protocol conversion module 11 through the read configuration path bus through the read register.

In an exemplary embodiment of the present disclosure, the SPI interface protocol conversion module 11 can also be configured to convert the transmission protocol of the information that needs to be transmitted to the host computer 2 from the bus protocol to the SPI interface protocol, and transmit the information that needs to be transmitted to the host computer 2 to the host computer 2 according to the SPI interface protocol.

In an exemplary embodiment of the present disclosure, for data that chip 1 needs to transmit to the host computer 2, the read data and/or test results of the corresponding block can be written into the read configuration path bus and uniformly transmitted to the SPI interface protocol conversion module 11. After the bus protocol is converted into the SPI interface protocol, it is transmitted to the host computer through the SPI interface protocol.

The present disclosure also provides a data transmission method based on the chip; as shown in FIG5 , the method may include steps S101-S102:

S101, communicating with a host computer through an SPI interface protocol to obtain communication information, converting a transmission protocol of the communication information into a bus protocol, and transmitting the communication information to a corresponding block in the chip through a bus based on the bus protocol;

S102: Parse the communication information and required configuration parameters in the block itself, and perform corresponding operations according to the parsing results.

In the exemplary embodiments of the present disclosure, any of the aforementioned chip embodiments are applicable to the method embodiments, and will not be described one by one here.

It will be understood by those skilled in the art that all or some of the steps, systems, and functional units/units in the above disclosed methods may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the divisions between the functional units/units mentioned in the above description do not necessarily correspond to the divisions of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or may be implemented as hardware. The software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media generally contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

A chip comprises a serial peripheral interface (SPI) interface protocol conversion module and a plurality of divided blocks; the blocks directly connected to the SPI interface protocol conversion module among the plurality of blocks are used as primary blocks, and the blocks not directly connected to the SPI interface protocol conversion module are used as multi-level blocks; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and is connected to the multi-level blocks level by level through the bus via the primary blocks corresponding to the multi-level blocks;

The SPI interface protocol conversion module is configured to communicate with the host computer through the SPI interface protocol to obtain communication information, convert the transmission protocol of the communication information into a bus protocol, and transmit the communication information to the corresponding block through the bus based on the bus protocol;

The block is configured to parse the communication information and the required configuration parameters within the block itself after receiving the communication information, and perform corresponding operations according to the parsing results.
The chip according to claim 1, wherein each of the blocks is provided with a register; the SPI interface protocol conversion module is connected to each of the primary blocks through a bus, and is connected to the multi-level blocks step by step through the primary blocks corresponding to the multi-level blocks through the bus, comprising:

The SPI interface protocol conversion module is connected to the registers in all the first-level blocks through a bus, and is connected to the registers in the multi-level blocks subsequent to the first-level block step by step through the bus.
The chip according to claim 2, wherein each of the blocks comprises one or more functional units; and the parsing of the communication information and the required configuration parameters within the block itself and performing corresponding operations according to the parsing results comprises:

The communication information and the required configuration parameters are parsed in the register of the block itself according to the preset configuration parameters and data address table, and the parsing results are distributed to the functional units, which perform corresponding operations.
The chip according to claim 3, wherein the communication information includes write data information, and the write data information includes: write enable, write address and write data; the register is a write register;

The bus is configured to transmit the write data information.
The chip according to claim 4, wherein the corresponding operation performed by the functional unit comprises:

The functional unit writes the write data into the write address according to the write enable.
The chip according to claim 3, wherein the communication information includes read data information, and the read data information includes: read enable and read address; the register is a read register;

The bus is configured to transmit the read data information.
The chip according to claim 6, wherein the corresponding operation performed by the functional unit comprises:

The functional unit reads data from the read address according to the read enable to obtain read data;

Returning the read data to the read register;

The read register is configured to transmit the read data to the SPI interface protocol conversion module via a bus.
The chip according to claim 3, wherein the functional unit includes any one or more of the following: a cache control unit, a computing unit, and a testing unit.
According to the chip according to claim 1, wherein the SPI interface protocol conversion module is also configured to convert the transmission protocol of the information to be transmitted to the host computer from the bus protocol to the SPI interface protocol, and transmit the information to be transmitted to the host computer to the host computer according to the SPI interface protocol.
The chip according to claim 1, wherein:

The number of levels of the multi-level blocks is positively correlated with the number of blocks required to pass through to connect to the SPI interface protocol conversion module.
The chip according to claim 1, wherein:

The SPI interface protocol conversion module is arranged in a primary block, or is arranged separately.
A data transmission method, based on the chip according to any one of claims 1 to 11; the method comprising:

Communicate with the host computer through the SPI interface protocol to obtain communication information, convert the transmission protocol of the communication information into a bus protocol, and transmit the communication information to the corresponding block in the chip through the bus based on the bus protocol;

The communication information and the required configuration parameters are parsed within the block itself, and corresponding operations are performed according to the parsing results.