CN1153145C - 预加载不同缺省地址转换属性的方法和装置 - Google Patents

预加载不同缺省地址转换属性的方法和装置 Download PDF

Info

Publication number
CN1153145C
CN1153145C CNB971255857A CN97125585A CN1153145C CN 1153145 C CN1153145 C CN 1153145C CN B971255857 A CNB971255857 A CN B971255857A CN 97125585 A CN97125585 A CN 97125585A CN 1153145 C CN1153145 C CN 1153145C
Authority
CN
China
Prior art keywords
default
page
address
unit
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB971255857A
Other languages
English (en)
Chinese (zh)
Other versions
CN1192009A (zh
Inventor
ɽ��һ��
山田康一
�����ɵ�
G·N·哈蒙德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1192009A publication Critical patent/CN1192009A/zh
Application granted granted Critical
Publication of CN1153145C publication Critical patent/CN1153145C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/654Look-ahead translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB971255857A 1996-12-23 1997-12-23 预加载不同缺省地址转换属性的方法和装置 Expired - Fee Related CN1153145C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US771,845 1977-02-25
US771845 1996-12-23
US08/771,845 US5918251A (en) 1996-12-23 1996-12-23 Method and apparatus for preloading different default address translation attributes

Publications (2)

Publication Number Publication Date
CN1192009A CN1192009A (zh) 1998-09-02
CN1153145C true CN1153145C (zh) 2004-06-09

Family

ID=25093117

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971255857A Expired - Fee Related CN1153145C (zh) 1996-12-23 1997-12-23 预加载不同缺省地址转换属性的方法和装置

Country Status (5)

Country Link
US (1) US5918251A (enExample)
EP (1) EP0851357B1 (enExample)
JP (1) JP3998787B2 (enExample)
CN (1) CN1153145C (enExample)
DE (1) DE69724572T2 (enExample)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6041366A (en) * 1998-02-02 2000-03-21 International Business Machines Corporation System and method for dynamic specification of input/output attributes
US6205531B1 (en) * 1998-07-02 2001-03-20 Silicon Graphics Incorporated Method and apparatus for virtual address translation
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8065504B2 (en) * 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6301648B1 (en) * 1999-08-18 2001-10-09 Ati International Srl Method and apparatus for processing memory accesses utilizing a TLB
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US6393544B1 (en) * 1999-10-31 2002-05-21 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for calculating a page table index from a virtual address
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US6560689B1 (en) * 2000-03-31 2003-05-06 Intel Corporation TLB using region ID prevalidation
US6636955B1 (en) * 2000-08-31 2003-10-21 Hewlett-Packard Development Company, L.P. Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
US6751721B1 (en) * 2000-08-31 2004-06-15 Hewlett-Packard Development Company, L.P. Broadcast invalidate scheme
US6622225B1 (en) 2000-08-31 2003-09-16 Hewlett-Packard Development Company, L.P. System for minimizing memory bank conflicts in a computer system
US6654858B1 (en) 2000-08-31 2003-11-25 Hewlett-Packard Development Company, L.P. Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol
US6779142B1 (en) 2000-08-31 2004-08-17 Hewlett-Packard Development Company, L.P. Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment
US7099913B1 (en) 2000-08-31 2006-08-29 Hewlett-Packard Development Company, L.P. Speculative directory writes in a directory based cache coherent nonuniform memory access protocol
US6961781B1 (en) 2000-08-31 2005-11-01 Hewlett-Packard Development Company, L.P. Priority rules for reducing network message routing latency
US6662319B1 (en) * 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Special encoding of known bad data
US6668335B1 (en) 2000-08-31 2003-12-23 Hewlett-Packard Company, L.P. System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths
US6678840B1 (en) * 2000-08-31 2004-01-13 Hewlett-Packard Development Company, Lp. Fault containment and error recovery in a scalable multiprocessor
US6715057B1 (en) 2000-08-31 2004-03-30 Hewlett-Packard Development Company, L.P. Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
US7213087B1 (en) 2000-08-31 2007-05-01 Hewlett-Packard Development Company, L.P. Mechanism to control the allocation of an N-source shared buffer
US6671822B1 (en) 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
US6681295B1 (en) 2000-08-31 2004-01-20 Hewlett-Packard Development Company, L.P. Fast lane prefetching
US6754739B1 (en) 2000-08-31 2004-06-22 Hewlett-Packard Development Company Computer resource management and allocation system
US6738836B1 (en) * 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US6704817B1 (en) * 2000-08-31 2004-03-09 Hewlett-Packard Development Company, L.P. Computer architecture and system for efficient management of bi-directional bus
US6546453B1 (en) 2000-08-31 2003-04-08 Compaq Information Technologies Group, L.P. Proprammable DRAM address mapping mechanism
US6546465B1 (en) 2000-08-31 2003-04-08 Hewlett-Packard Development Company, L.P. Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
US6633960B1 (en) * 2000-08-31 2003-10-14 Hewlett-Packard Development Company, L.P. Scalable directory based cache coherence protocol
US6567900B1 (en) 2000-08-31 2003-05-20 Hewlett-Packard Development Company, L.P. Efficient address interleaving with simultaneous multiple locality options
US6662265B1 (en) 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Mechanism to track all open pages in a DRAM memory system
DE10131124A1 (de) * 2001-06-28 2003-01-23 Infineon Technologies Ag Konfigurierbare Adressierungsvorrichtung
GB2378779B (en) * 2001-08-14 2005-02-02 Advanced Risc Mach Ltd Accessing memory units in a data processing apparatus
US6782446B2 (en) * 2001-08-22 2004-08-24 Intel Corporation Method to prevent corruption of page tables during flash EEPROM programming
US7124273B2 (en) * 2002-02-25 2006-10-17 Intel Corporation Method and apparatus for translating guest physical addresses in a virtual machine environment
US7581010B2 (en) * 2003-07-14 2009-08-25 Microsoft Corporation Virtual connectivity with local connection translation
US20050160229A1 (en) * 2004-01-16 2005-07-21 International Business Machines Corporation Method and apparatus for preloading translation buffers
US7206916B2 (en) * 2004-03-08 2007-04-17 Sun Microsystems, Inc. Partial address compares stored in translation lookaside buffer
JP4233492B2 (ja) * 2004-06-02 2009-03-04 富士通マイクロエレクトロニクス株式会社 アドレス変換装置
US7424584B2 (en) * 2004-08-12 2008-09-09 International Business Machines Corporation Key-controlled object-based memory protection
US7617380B2 (en) * 2005-08-25 2009-11-10 Broadcom Corporation System and method for synchronizing translation lookaside buffer access in a multithread processor
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
US7886112B2 (en) * 2006-05-24 2011-02-08 Sony Computer Entertainment Inc. Methods and apparatus for providing simultaneous software/hardware cache fill
EP2527972A3 (en) 2006-11-14 2014-08-06 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US8799620B2 (en) * 2007-06-01 2014-08-05 Intel Corporation Linear to physical address translation with support for page attributes
US9244855B2 (en) * 2007-12-31 2016-01-26 Intel Corporation Method, system, and apparatus for page sizing extension
JP5347024B2 (ja) * 2009-06-24 2013-11-20 パナソニック株式会社 メモリアクセス制御装置、集積回路、メモリアクセス制御方法及びデータ処理装置
US8364933B2 (en) * 2009-12-18 2013-01-29 International Business Machines Corporation Software assisted translation lookaside buffer search mechanism
US8694755B1 (en) * 2010-03-17 2014-04-08 Ambarella, Inc. Virtual memory management for real-time embedded devices
EP3156896B1 (en) 2010-09-17 2020-04-08 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
EP2689326B1 (en) 2011-03-25 2022-11-16 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9842005B2 (en) 2011-03-25 2017-12-12 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101639853B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당
CN103649931B (zh) 2011-05-20 2016-10-12 索夫特机械公司 用于支持由多个引擎执行指令序列的互连结构
EP2783281B1 (en) 2011-11-22 2020-05-13 Intel Corporation A microprocessor accelerated code optimizer
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US9378150B2 (en) * 2012-02-28 2016-06-28 Apple Inc. Memory management unit with prefetch ability
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9430410B2 (en) 2012-07-30 2016-08-30 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
CN103116555B (zh) * 2013-03-05 2014-03-05 中国人民解放军国防科学技术大学 基于多体并行缓存结构的数据访问方法
CN105210040B (zh) 2013-03-15 2019-04-02 英特尔公司 用于执行分组成块的多线程指令的方法
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175398A3 (en) * 1984-08-17 1989-08-30 Koninklijke Philips Electronics N.V. Data processing system comprising a memory access controller which is provided for combining descriptor bits of different descriptors associated with virtual addresses
US5060137A (en) * 1985-06-28 1991-10-22 Hewlett-Packard Company Explicit instructions for control of translation lookaside buffers
US4774659A (en) * 1986-04-16 1988-09-27 Astronautics Corporation Of America Computer system employing virtual memory
US4881075A (en) * 1987-10-15 1989-11-14 Digital Equipment Corporation Method and apparatus for adaptive data compression
US4980816A (en) * 1987-12-18 1990-12-25 Nec Corporation Translation look-aside buffer control system with multiple prioritized buffers
US5179674A (en) * 1988-07-25 1993-01-12 Digital Equipment Corporation Method and apparatus for predicting valid performance of virtual-address to physical-address translations
US5058003A (en) * 1988-12-15 1991-10-15 International Business Machines Corporation Virtual storage dynamic address translation mechanism for multiple-sized pages
JPH02205953A (ja) * 1989-02-03 1990-08-15 Nec Corp アドレス変換装置
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5412787A (en) * 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
EP0506236A1 (en) * 1991-03-13 1992-09-30 International Business Machines Corporation Address translation mechanism
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
US5278963A (en) * 1991-06-21 1994-01-11 International Business Machines Corporation Pretranslation of virtual addresses prior to page crossing
US5465337A (en) * 1992-08-13 1995-11-07 Sun Microsystems, Inc. Method and apparatus for a memory management unit supporting multiple page sizes
US5493660A (en) * 1992-10-06 1996-02-20 Hewlett-Packard Company Software assisted hardware TLB miss handler
US5442766A (en) * 1992-10-09 1995-08-15 International Business Machines Corporation Method and system for distributed instruction address translation in a multiscalar data processing system
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5526504A (en) * 1993-12-15 1996-06-11 Silicon Graphics, Inc. Variable page size translation lookaside buffer
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5652872A (en) * 1994-03-08 1997-07-29 Exponential Technology, Inc. Translator having segment bounds encoding for storage in a TLB
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US5809563A (en) * 1996-11-12 1998-09-15 Institute For The Development Of Emerging Architectures, Llc Method and apparatus utilizing a region based page table walk bit

Also Published As

Publication number Publication date
CN1192009A (zh) 1998-09-02
EP0851357A1 (en) 1998-07-01
JPH10228419A (ja) 1998-08-25
EP0851357B1 (en) 2003-09-03
DE69724572T2 (de) 2004-04-08
DE69724572D1 (de) 2003-10-09
US5918251A (en) 1999-06-29
JP3998787B2 (ja) 2007-10-31

Similar Documents

Publication Publication Date Title
CN1153145C (zh) 预加载不同缺省地址转换属性的方法和装置
US5918250A (en) Method and apparatus for preloading default address translation attributes
US6308247B1 (en) Page table entry management method and apparatus for a microkernel data processing system
CN1993683B (zh) 体系结构事件期间维持处理器资源
US7783859B2 (en) Processing system implementing variable page size memory organization
US5630097A (en) Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses
EP0797149B1 (en) Architecture and method for sharing tlb entries
US8140820B2 (en) Data processing apparatus and method for handling address translation for access requests issued by processing circuitry
US5479627A (en) Virtual address to physical address translation cache that supports multiple page sizes
US6560690B2 (en) System and method for employing a global bit for page sharing in a linear-addressed cache
US6003123A (en) Memory system with global address translation
US20090187731A1 (en) Method for Address Translation in Virtual Machines
CN1084005C (zh) 用于动态控制地址空间分配的方法和设备
EP0215544A1 (en) Virtual memory address fetching
JPH07262092A (ja) 仮想メモリ管理システム、変換索引バッファ管理方法、及び変換索引バッファパージオーバーヘッド最小化方法
CN1841343A (zh) 改进任务切换的系统和方法
CN115061955B (zh) 处理器、电子设备、地址翻译方法以及缓存页表项方法
US6990551B2 (en) System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
CN1299206C (zh) 扩展处理器的局部存储器地址空间的方法、设备和系统
EP2159707A1 (en) Arithmetic processing unit, entry control program, and entry control method
US7519791B2 (en) Address conversion technique in a context switching environment
CN114840332A (zh) 页交换方法、装置和电子设备
CN1269043C (zh) 内存地址的重新映射方法
CN115080464B (zh) 数据处理方法和数据处理装置
US20090024798A1 (en) Storing Data

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040609

Termination date: 20121223