CN115314451B - Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip - Google Patents
Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip Download PDFInfo
- Publication number
- CN115314451B CN115314451B CN202211013610.6A CN202211013610A CN115314451B CN 115314451 B CN115314451 B CN 115314451B CN 202211013610 A CN202211013610 A CN 202211013610A CN 115314451 B CN115314451 B CN 115314451B
- Authority
- CN
- China
- Prior art keywords
- chip
- power
- msu
- nms1800
- domestic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Sources (AREA)
Abstract
The invention discloses a method for treating insufficient power down caused by current backflow of a domestic SRIO exchange chip, belonging to the field of domestic chip application, comprising the following steps: for a domestic SRIO exchange chip, the upper and lower current ranges of the domestic SRIO exchange chip are optimized: the level of the control pin is firstly pulled down in the power-on process, and the corresponding control pin is pulled up after the power-on is finished; in the power-down process, the control pin level is pulled down first, and then the power chip is controlled to be pulled down by 3.3V. The invention ensures that the NMS1800 chip can normally work after the current process is carried out up and down, simultaneously has no backward current, reduces the useless power consumption on the circuit and ensures the low power consumption requirement of the design.
Description
Technical Field
The invention relates to the field of domestic chip application, in particular to a method for treating insufficient power-down caused by current backflow of a domestic SRIO exchange chip.
Background
The integrated electronic system is characterized in that most of functions in the system are realized by filling different software into a general hardware module. The embedded processor commonly used by the general hardware module comprises a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP) and a General Purpose Processor (GPP). The FPGA has rich input and output pins and task parallel executability, the DSP has high-efficiency data processing capability and convenient and flexible debugging development environment, the GPP can effectively support control intensive applications of the non-digital signal processing types, the three embedded processors have advantages, and the three embedded processors are used for running different programs in the integrated system to process different types of tasks, and the powerful performance of the embedded processors is exerted by running the programs in the embedded processors.
The current integrated electronic information system mainly comprises a general Data Processing Module (DPM), a general Signal Processing Module (SPM), a network switching module (RCM), a System Control Module (SCM) and a high-speed mass storage module (MMM). The module is carried out according to the general function framework requirements of the module in the aspects of function unit division and design. The general function framework of the module requires: each module consists of a Module Supporting Unit (MSU), a Processing Unit (PU), a Routing Unit (RU), a Network Interface Unit (NIU), a power source supporting unit (PSE), a Module Physical Interface (MPI) and other units, and standardized and generalized design of module hardware circuits is realized. The MSU is a unit of each hardware module, is generally connected with the system control through a control bus, and is used for receiving a system control instruction to complete board-level management such as power-on control, reset control, program loading, program updating, current acquisition, voltage acquisition, temperature acquisition, health status reporting and the like.
NMS1800 is a domestic first-generation autonomous RapIDIO second-generation exchange chip developed by the information technology innovation center of the coastal new area of Tianjin, accords with the RapIDIO second-generation specification, provides 240Gbps non-blocking exchange capacity, can support 18 ports and 48 paths at most, is suitable for chip-to-chip interconnection, inter-board interconnection and inter-cabinet interconnection in boards, is a current integrated electronic system dominant exchange chip, and is generally used for integrated electronic system network exchange hardware modules. In the process of applying the NMS1800 chip, the invention discovers the technical problem of insufficient power down caused by current backflow and provides a solution for the problem.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a domestic SRIO exchange chip current backflow caused insufficient power-down processing method, which ensures that the NMS1800 chip can normally work after the current process is performed, meanwhile, no backflow current exists, the useless power consumption on a circuit is reduced, and the low power consumption requirement of the design is ensured.
The invention aims at realizing the following scheme:
a domestic SRIO exchange chip current backflow caused insufficient power-down treatment method comprises the following steps:
for a domestic SRIO exchange chip, the upper and lower current ranges of the domestic SRIO exchange chip are optimized: the level of the control pin is firstly pulled down in the power-on process, and the corresponding control pin is pulled up after the power-on is finished; in the power-down process, the control pin level is pulled down first, and then the power chip is controlled to be pulled down by 3.3V.
Further, the step of first pulling down the level of the control pin in the power-up process and then pulling up the corresponding control pin after the power-up process is completed includes the following steps:
s1, MSU controls a control pin of NMS1800 chip to set the control pin to be low level;
s2, the MSU controls the power chip to pull up 3.3V;
s3, the MSU controls the power chip to pull up 1.2V;
s4, MSU pulls up control pin of NMS1800 chip;
s5, MSU pulls up reset signal of NMS1800 chip to release reset.
Further, the step of firstly pulling down the control pin level in the power-down process and then controlling the power chip to pull down 3.3V includes the following substeps:
SS1, MSU pulls down reset signal of NMS1800 chip, reset NMS1800 chip;
SS2, MSU pulls down the control pin of NMS1800 chip;
SS3, MSU controls the power chip to pull down 1.2V;
SS4, MSU controls the power chip to pull down 3.3V.
Further, the power chip includes JSR23797-SP or an alternate model thereof.
Further, the NMS1800 chip is connected to the MSU.
Further, the MSU is connected with the JSR23797-SP, and controls the 3.3V output to be fed into the NMS1800 chip.
Further, the NMS1800 chip is connected to the MSU through control pins SPD, tsi_ads, FSEL.
Further, GPIO of the MSU is connected with JSR23797-SP, and 3.3V output is controlled to be sent into an NMS1800 chip.
Further, the domestic SRIO switching chip comprises an NMS1800 chip.
The beneficial effects of the invention include:
aiming at the situation that 3.3V of the control pins SPD, TSI_ADS and FSEL are insufficient in power down caused by current backflow in the power down process of the NMS1800 chip, the residual value is 1.2V, the functions of initializing and building a chain of SRIO, connecting nodes to the network and the like are affected, the power-on and power-off process of the NMS1800 chip is optimized, the power-on and power-off process of the NMS1800 chip is firstly carried out, the control pin level is firstly pulled down, and the corresponding control pin is pulled up after the power-on is completed; in the power-down process, the control pin level is pulled down first, and then the power supply chip is controlled to be pulled down by 3.3V. The NMS1800 chip can work normally after up-down current process. Meanwhile, no backward current exists, the useless power consumption on the circuit is reduced, and the low power consumption requirement of the design is ensured.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a method for treating insufficient power down caused by current backflow of a domestic SRIO exchange chip according to an embodiment of the invention;
fig. 2 is a schematic circuit diagram of a domestic SRIO switching chip according to an embodiment of the present invention.
Detailed Description
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
In the schematic diagram, the control pins SPD, tsi_ads, FSEL of NMS1800 are connected to a 3.3V power supply via pull-up resistors, as shown in fig. 2. The inventor practices of the present invention found that, during the power-down process of the NMS1800 chip, if the MSU does not control the corresponding control pins of the NMS1800, the pins are in a high level state, a current backflow phenomenon occurs, so that the 3.3V voltage of the NMS1800 is remained, and the residual voltage value is about 1.2V. If the resistance of the pull-up circuit is turned off, the 3.3V voltage residual disappears. This further confirms that a high level of the control pin causes current to flow backward, resulting in an unclean residual value for the 3.3V voltage. This phenomenon may affect the initialization chaining of SRIOs, resulting in nodes connected to NMS1800 not being able to access the network, further resulting in overall network paralysis. Meanwhile, if the group of 3.3V power supplies are used by other circuit units, the circuit units can be abnormal in function under the condition of power-on time sequence requirement.
In order to solve the technical problems found above, the invention provides a power-on and power-off management method for an NMS1800 chip, aiming at the defect that 3.3V voltage remains in the power-off process caused by current backflow without controlling the control pins SPD, TSI_ADS and FSEL of the NMS1800 chip.
As shown in FIG. 1, the method for treating insufficient power down caused by current backflow of the domestic SRIO exchange chip provided by the embodiment of the invention comprises a power-up process and a power-down process. Wherein the power-on process comprises the following steps:
s1, MSU controls a control pin of NMS1800 chip to set the control pin to be low level;
s2, the MSU controls the power chip to pull up 3.3V;
s3, the MSU controls the power chip to pull up 1.2V;
s4, MSU pulls up control pin of NMS1800 chip;
s5, MSU pulls up reset signal of NMS1800 chip to release reset.
Wherein, the power-down process comprises the following steps:
SS1, MSU pulls down reset signal of NMS1800 chip, reset NMS1800 chip;
SS2, MSU pulls down the control pin of NMS1800 chip;
SS3, MSU controls the power chip to pull down 1.2V;
SS4, MSU controls the power chip to pull down 3.3V. In an alternative scheme, the power chip is JSR23797-SP or an alternative model thereof.
As shown in fig. 2, the corresponding circuit of the NMS1800 chip circuit schematic provided in the embodiment of the present invention mainly includes a domestic SRIO switching chip, a module supporting unit MSU, and a power supply chip HCE4630. Wherein the NMS1800 chip is connected with the MSU through the control pins SPD, TSI_ADS and FSEL, the GPIO of the MSU is connected with the JSR23797-SP, and the 3.3V output is controlled to be sent into the NMS1800 chip.
Example 1
A domestic SRIO exchange chip current backflow caused insufficient power-down treatment method comprises the following steps:
for a domestic SRIO exchange chip, the upper and lower current ranges of the domestic SRIO exchange chip are optimized: the level of the control pin is firstly pulled down in the power-on process, and the corresponding control pin is pulled up after the power-on is finished; in the power-down process, the control pin level is pulled down first, and then the power chip is controlled to be pulled down by 3.3V.
Example 2
Based on embodiment 1, the step of first pulling the level of the control pin low during the power-up process, and then pulling the corresponding control pin high after the power-up process is completed includes the following sub-steps:
s1, MSU controls a control pin of NMS1800 chip to set the control pin to be low level;
s2, the MSU controls the power chip to pull up 3.3V;
s3, the MSU controls the power chip to pull up 1.2V;
s4, MSU pulls up control pin of NMS1800 chip;
s5, MSU pulls up reset signal of NMS1800 chip to release reset.
Example 3
Based on embodiment 1, the step of first pulling down the control pin level during the power-down process and then controlling the power chip to pull down 3.3V includes the following substeps:
SS1, MSU pulls down reset signal of NMS1800 chip, reset NMS1800 chip;
SS2, MSU pulls down the control pin of NMS1800 chip;
SS3, MSU controls the power chip to pull down 1.2V;
SS4, MSU controls the power chip to pull down 3.3V.
Example 4
On the basis of embodiment 2 or embodiment 3, the power chip includes JSR23797-SP or an alternative model thereof.
Example 5
Based on embodiment 2 or embodiment 3, the NMS1800 chip is connected to the MSU.
Example 6
On the basis of example 5, the MSU is connected with the JSR23797-SP, and controls the 3.3V output to be fed into the NMS1800 chip.
Example 7
On the basis of embodiment 6, the NMS1800 chip is connected to the MSU via control pins SPD, tsi_ads, FSEL.
Example 8
Based on the embodiment 7, the GPIO of the MSU is connected with the JSR23797-SP, and the 3.3V output is controlled to be sent into the NMS1800 chip.
Example 9
Based on the embodiment 1, the domestic SRIO switching chip comprises an NMS1800 chip
The invention is not related in part to the same as or can be practiced with the prior art.
The foregoing technical solution is only one embodiment of the present invention, and various modifications and variations can be easily made by those skilled in the art based on the application methods and principles disclosed in the present invention, not limited to the methods described in the foregoing specific embodiments of the present invention, so that the foregoing description is only preferred and not in a limiting sense.
In addition to the foregoing examples, those skilled in the art will recognize from the foregoing disclosure that other embodiments can be made and in which various features of the embodiments can be interchanged or substituted, and that such modifications and changes can be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. A domestic SRIO exchange chip current backflow caused insufficient power-down treatment method is characterized by comprising the following steps:
for a domestic SRIO exchange chip, the current process is up and down: the level of the control pin is firstly pulled down in the power-on process, and the corresponding control pin is pulled up after the power-on is finished; in the power-down process, the level of a control pin is firstly pulled down, and then the power chip is controlled to be pulled down by 3.3V;
the power-on process comprises the following steps of:
s1, MSU controls a control pin of NMS1800 chip to set the control pin to be low level;
s2, the MSU controls the power chip to pull up 3.3V;
s3, the MSU controls the power chip to pull up 1.2V;
s4, MSU pulls up control pin of NMS1800 chip;
s5, MSU pulls up reset signal of NMS1800 chip to release reset;
the power chip is controlled to be pulled down by 3.3V after the control pin level is pulled down in the power-down process, and the method comprises the following substeps:
SS1, MSU pulls down reset signal of NMS1800 chip, reset NMS1800 chip;
SS2, MSU pulls down the control pin of NMS1800 chip;
SS3, MSU controls the power chip to pull down 1.2V;
SS4, MSU controls the power chip to pull down 3.3V.
2. The method for processing insufficient power down caused by current backflow of domestic SRIO exchange chip according to claim 1, wherein the power chip comprises JSR23797-SP.
3. The method for processing the underpower down caused by the backward flow of the domestic SRIO switching chip current according to claim 1, wherein the NMS1800 chip is connected with the MSU.
4. The method for processing insufficient power down caused by current backflow of domestic SRIO exchange chips according to claim 2, wherein the MSU is connected with the JSR23797-SP, and the 3.3V output is controlled to be fed into the NMS1800 chip.
5. A domestic SRIO switch chip current back-off caused by insufficient power down processing method as claimed in claim 3, wherein said NMS1800 chip is connected to MSU through control pins SPD, tsi_ads, FSEL.
6. The method for processing insufficient power down caused by current backflow of domestic SRIO exchange chip according to claim 4, wherein GPIO of the MSU is connected with JSR23797-SP, and 3.3V output is controlled to be fed into an NMS1800 chip.
7. The method for processing insufficient power down caused by current backflow of domestic SRIO switching chips according to claim 1, wherein the domestic SRIO switching chips comprise NMS1800 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211013610.6A CN115314451B (en) | 2022-08-23 | 2022-08-23 | Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211013610.6A CN115314451B (en) | 2022-08-23 | 2022-08-23 | Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115314451A CN115314451A (en) | 2022-11-08 |
| CN115314451B true CN115314451B (en) | 2023-06-06 |
Family
ID=83864705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211013610.6A Active CN115314451B (en) | 2022-08-23 | 2022-08-23 | Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115314451B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102053567A (en) * | 2010-10-19 | 2011-05-11 | 北京星网锐捷网络技术有限公司 | Safety power-on time sequence control circuit system |
| CN103887973A (en) * | 2012-12-24 | 2014-06-25 | 中兴通讯股份有限公司 | Method and system controlling reverse current to generate power tube voltage stress |
| CN112019457A (en) * | 2020-08-31 | 2020-12-01 | 北京计算机技术及应用研究所 | High-speed switching device based on localization SRIO |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003134809A (en) * | 2001-10-26 | 2003-05-09 | Fuji Electric Co Ltd | Switching power circuit |
| CN103365222B (en) * | 2012-03-26 | 2017-04-12 | 中兴通讯股份有限公司 | Power sequence control circuit and integrated circuit |
| CN103746684B (en) * | 2014-01-16 | 2020-10-23 | 上海斐讯数据通信技术有限公司 | System and method for preventing power supply from flowing backwards |
| CN105388982B (en) * | 2015-11-16 | 2019-01-08 | 中国电子科技集团公司第十研究所 | Multiprocessor electrification reset circuit |
| WO2018079033A1 (en) * | 2016-10-27 | 2018-05-03 | 住友電気工業株式会社 | Voltage converting device, step-down control method for voltage converting circuit, step-up control method for voltage converting circuit, and computer program |
| CN107920001A (en) * | 2017-12-07 | 2018-04-17 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The debugging apparatus of RapidIO communication middlewares |
| CN209120219U (en) * | 2018-12-29 | 2019-07-16 | 西安希德雷达科技有限公司 | A kind of SRIO high-speed figure interchanger |
| CN214409638U (en) * | 2021-03-12 | 2021-10-15 | 湖南艾科诺维科技有限公司 | Radio frequency data acquisition and processing mainboard and device |
| CN214586880U (en) * | 2021-05-12 | 2021-11-02 | 湖南泽天智航电子技术有限公司 | Information processing apparatus |
| CN114363728B (en) * | 2021-12-30 | 2024-06-18 | 锐捷网络股份有限公司 | Electronic equipment and method for preventing current backflow |
| CN217216610U (en) * | 2022-04-29 | 2022-08-16 | 中国第一汽车股份有限公司 | Wake up source indicator signal output device |
-
2022
- 2022-08-23 CN CN202211013610.6A patent/CN115314451B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102053567A (en) * | 2010-10-19 | 2011-05-11 | 北京星网锐捷网络技术有限公司 | Safety power-on time sequence control circuit system |
| CN103887973A (en) * | 2012-12-24 | 2014-06-25 | 中兴通讯股份有限公司 | Method and system controlling reverse current to generate power tube voltage stress |
| CN112019457A (en) * | 2020-08-31 | 2020-12-01 | 北京计算机技术及应用研究所 | High-speed switching device based on localization SRIO |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115314451A (en) | 2022-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107070795B (en) | Channel selection in a multi-channel switching network | |
| CN100465907C (en) | Apparatus and method of CMOS parameter setting and maintaining | |
| CN110347625B (en) | Method, device and equipment for switching GPU topology through wireless cable | |
| CN101882097A (en) | Main control board, embedded system and backup method for embedded system | |
| CN113127302A (en) | Method and device for monitoring GPIO (general purpose input/output) of board card | |
| CN111209241A (en) | Management system of whole cabinet server | |
| CN107038104A (en) | A kind of method of remote monitoring isomery accelerator card | |
| CN115314451B (en) | Method for treating insufficient power-down caused by current backflow of domestic SRIO exchange chip | |
| CN114124656A (en) | Ground integrated measurement and control system for carrier rocket | |
| CN102103712B (en) | Power supply configuration method and device | |
| CN113204375A (en) | Method, system and equipment for partitioning multi-path server | |
| CN113177019B (en) | Switch board and server | |
| US6658634B1 (en) | Logic power optimization algorithm | |
| CN101958797B (en) | Ethernet power supply system and operating method | |
| WO2017080006A1 (en) | Centralized storage method saving memory chips, and multifunctional module system | |
| CN106575276A (en) | Sub-system power management control | |
| CN115543907B (en) | Control method and device based on PCIe chip in storage device | |
| CN210666783U (en) | Control circuit of high-density ARM micro server | |
| CN114363728B (en) | Electronic equipment and method for preventing current backflow | |
| CN113778930B (en) | AVS (Audio video Standard) adjusting system, method, device and equipment | |
| CN115499293B (en) | SRIO network access abnormality recovery method, equipment and medium of domestic DSP | |
| CN112307697B (en) | FPGA logic reload circuit | |
| CN109582609A (en) | A kind of apparatus control method, system and associated component | |
| CN112445657B (en) | Circuit switching method and system supporting fault removal | |
| CN113778732A (en) | Fault positioning method and device for service board card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |